Reduced underlayer oxidation during gap fill

Abstract

Exemplary processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be located within this processing region. A layer of a first silicon-containing material defining one or more features may be disposed on the substrate. These methods may include contacting the substrate with one or more deposition precursors. This contact may deposit a pad material on the first silicon-containing material. These methods may include performing an atomic layer deposition (ALD) process. The ALD process may deposit a silicon- and oxygen-containing material in one or more features.

Description

Technical Field

[0001] This application declares the benefit and priority of U.S. Patent Application No. 18 / 761,660, filed July 2, 2024, entitled “Reducing Underlying Oxidation During Gap Filling,” the entire contents of which are hereby incorporated.

[0002] This technology relates to semiconductor processing. More specifically, this technology relates to a method for reducing interstitial filling of silicon-containing materials with reduced underlying oxidation. Prior Technology

[0003] The realization of integrated circuits relies on processes that create finely patterned material layers on a substrate surface. Producing patterned material on a substrate requires controlling the methods for forming and removing exposed material. As device dimensions continue to shrink, material formation can impact subsequent operations. For example, in gap-filling operations, material may be formed or deposited to fill trenches or other features formed on a semiconductor substrate. These gap-filling operations can face challenges as feature aspect ratios increase and critical dimensions decrease. For instance, because deposition can occur on the top and sidewalls of a feature, continued deposition can cause the feature to become trapped between inner sidewalls, potentially creating voids within the feature. This can affect device performance and subsequent processing operations.

[0004] Therefore, it is necessary to improve systems and methods for producing high-quality components and structures. This technology addresses these and other needs. Summary of the Invention

[0005] Exemplary processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A substrate may be located within this processing region. A layer of first silicon-containing material defining one or more features may be disposed on the substrate. These methods may include contacting the substrate with one or more deposition precursors. This contact may deposit a pad material on the first silicon-containing material. These methods may include performing an atomic layer deposition (ALD) process. The ALD process may deposit silicon- and oxygen-containing material in one or more features.

[0006] In some embodiments, the deposition precursor may be or includes a silicon-containing precursor, a carbon-containing precursor, or a nitrogen-containing precursor. The deposition precursor may be or includes diatomic nitrogen (N2) or ammonia (NH3). The first silicon-containing material may be or includes a silicon-and-germanium-containing material. Layers of the first silicon-containing material may be deposited alternately with layers of the second silicon-containing material on the substrate. The pad material may be characterized by a thickness of less than or about 10 nm. The pad material may be or includes a silicon-and-nitrogen-containing material. Contacting one or more deposition precursors to deposit the pad material may include performing an ALD process on the pad material. Performing this ALD process may reduce the upper surface thickness of the first silicon-containing material layer by less than or about 5 nm. Performing this ALD process may convert the pad material to a silicon-and-oxygen-containing material. This ALD process may be a gap-filling operation.

[0007] Some embodiments of this technology may include semiconductor processing methods. These methods may include performing a first atomic layer deposition (ALD) process on a substrate located within a processing region of a semiconductor processing chamber. A silicon-containing material defining one or more features may be deposited on the substrate. The first ALD process may deposit a silicon- and nitrogen-containing material on the silicon-containing material. These methods may include stopping the first ALD process. These methods may include performing a second ALD process on the substrate. The second ALD process may deposit a silicon- and oxygen-containing material in one or more features.

[0008] In some embodiments, the silicon and nitrogen-containing material may be conformal. A first ALD process may involve sequentially exposing a substrate to a silicon-containing precursor and a nitrogen-containing precursor. The nitrogen-containing precursor may be or include ammonia (NH3). After a second ALD process, the silicon and nitrogen-containing material may be converted to a silicon and oxygen-containing material. The silicon and nitrogen-containing material may reduce the underlying oxidation of the silicon-containing material layer.

[0009] Some embodiments of this technology may include semiconductor processing methods. These methods may include performing a first atomic layer deposition (ALD) process on a substrate located within a processing region of a semiconductor processing chamber. Alternating silicon-containing material layers and silicon-and-germanium material layers defining one or more features may be disposed on the substrate. The first ALD process may conformally deposit a silicon-and-nitrogen-containing pad material on the alternating silicon-containing and silicon-and-germanium-containing material layers. These methods may include stopping the first ALD process after the thickness of the silicon-and-nitrogen-containing pad material is greater than or approximately 2 nm. These methods may include performing a second ALD process on the substrate. The second ALD process deposits silicon-and-oxygen-containing material in one or more features.

[0010] In some embodiments, the deposition of silicon and nitrogen-containing pad material may be self-limiting. After the second ALD process, the silicon and nitrogen-containing pad material may be converted to a silicon and oxygen-containing material.

[0011] This technology may offer numerous advantages over conventional systems and techniques. For example, by depositing the liner material, oxidation of the underlying material can be avoided, which may reduce or prevent corner rounding of the underlying material. Furthermore, by performing ALD or plasma-enhanced ALD (PEALD) processes to deposit silicon-containing materials, such as silicon- and oxygen-containing materials, the liner material may be altered so that unwanted components from the liner material do not appear in the interstitial material. These and other embodiments, along with many of their advantages and features, will be described in more detail in the following description and figures. Simple Explanation of the Diagram

[0012] For a further understanding of the nature and advantages of this disclosed technology, please refer to the remainder of this specification and the accompanying drawings.

[0013] Figure 1 shows a schematic cross-sectional view of an exemplary processing chamber according to certain embodiments of the present technology.

[0014] Figure 2 shows an example operation in a processing method according to certain embodiments of the present technology.

[0015] Figures 3A-3E show schematic cross-sectional views of a substrate during processing according to certain embodiments of the present technology.

[0016] Several figures are included in the form of illustrations. It should be understood that these figures are for illustrative purposes only and should not be considered to be to scale unless specifically stated otherwise. Furthermore, these figures are provided as illustrations to aid understanding and may not include all appearances or information compared to a realistic representation, and may contain exaggerated material for illustrative purposes.

[0017] In the accompanying drawings, similar elements and / or features may have the same element symbol. Furthermore, various elements of the same type can be distinguished by adding letters after the element symbol. If only element symbols are used in the specification, the description applies to any similar element having the same element symbol, regardless of the following letters. Implementation

[0018] Silicon-containing materials can be used in a variety of structures and processes in semiconductor device fabrication. Some embodiments involve using silicon-containing materials as sacrificial materials. For example, silicon-oxygen-containing materials can be used as (but not limited to) dummy gate materials or as trench fill materials. In other embodiments, silicon-containing materials can be used in deep trench isolation (DTI) structures. In gap-filling operations, certain processes may utilize plasma-enhanced deposition under process conditions to improve deposition directionality, which may allow the deposited material to better fill features on the substrate.

[0019] As feature sizes continue to shrink, the distance between interstitial features, sometimes referred to as column width, may also decrease. Depending on the material defining the feature, the overlying material may readily react with interstitial precursors. For example, in silicon- and oxygen-containing interstitials, the overlying material defining the feature may readily react with oxygen-containing substances, leading to oxidation of the material. Conventional techniques attempt to address this issue by depositing barrier materials to prevent the material defining the feature from reacting with one or more precursors used for interstitial filling. However, these conventional techniques often deposit excessive amounts of barrier material over the material defining the feature. This excessive deposition can negatively impact subsequent interstitial filling processes, potentially leading to the formation of seams or pores within the interstitial material. Furthermore, some of the barrier material may undesirably remain in the final structure.

[0020] This technique overcomes these limitations by depositing a padding material on the material defining one or more features. The padding material can be deposited using atomic layer deposition (ALD) or plasma-enhanced ALD (PEALD) processes. By using ALD or PEALD processes, the deposition of the padding material can be self-limiting. Therefore, the thickness of the padding material can be controlled by the number of cycles in the ALD or PEALD process. Thus, this technique avoids depositing excessive padding material over the material defining the features. Furthermore, by depositing a padding material of controlled thickness, subsequent gap-filling processes can convert the padding material into the material being deposited within the features. Therefore, this technique reduces or prevents reaction formation between the material defining the features and one or more precursors used for gap filling, while also reducing or preventing the formation of seams or pores in the gap-filling material.

[0021] After describing a general configuration of a chamber capable of performing the gap-filling operations described below according to certain embodiments of the present technology, specific methodologies will be discussed. It should be understood that the present technology is not intended to be limited to the specific membrane, chamber, or process discussed, as the described technology can be used to improve a variety of membrane formation processes and may be applicable to a wide range of processing chambers and operations.

[0022] Figure 1 shows a cross-sectional view of an exemplary processing chamber 100 according to certain embodiments of the present technology. This figure may show an overview of a system incorporating one or more aspects of the present technology, and / or performing one or more deposition or other processing operations according to embodiments of the present technology. Additional details of the chamber 100 or the performed methods may be further described below. The chamber 100 can be used to form thin film layers according to certain embodiments of the present technology; however, it should be understood that the method can also be similarly performed in any chamber capable of thin film formation. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a cover assembly 106 connected to the chamber body 102 and enclosing the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 via an opening 126, which may be conventionally sealed using a slit valve or door for processing. During processing, the substrate 103 may be placed on a surface 105 of the substrate support. The substrate support 104 may be rotatable, as indicated by arrow 145, rotating along axis 147, where axis 144 of the substrate support 104 may lie on axis 147. Alternatively, the substrate support 104 may be raised for rotation as needed during the deposition process.

[0023] A plasma profile modulator 111 may be placed within the processing chamber 100 to control the distribution of plasma on a substrate 103 located on a substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be adjacent to the chamber body 102 and may separate the chamber body 102 from other elements of the cover assembly 106. The first electrode 108 may be part of the cover assembly 106 or a separate sidewall electrode. The first electrode 108 may be a ring electrode. The first electrode 108 may be a continuous loop surrounding the periphery of the processing chamber 100, surrounding the processing space 120, or, if desired, may be discontinuous at selected locations. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor.

[0024] One or more isolators 110a, 110b, which may be dielectric materials, such as ceramics or metal oxides, such as alumina and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 (also referred to as a panel) and the chamber body 102. The gas distributor 112 may define an orifice 118 to distribute process precursors into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, RF power supply, DC power supply, pulsed DC power supply, pulsed RF power supply, or any other power source that can be connected to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0025] The gas distributor 112 can be a conductive or non-conductive gas distributor. The gas distributor 112 can also be composed of conductive and non-conductive components. For example, the body of the gas distributor 112 can be conductive, while the panel of the gas distributor 112 can be non-conductive. The gas distributor 112 can be electrically driven, for example, powered by the first power supply 142 shown in FIG. 1, or in some embodiments, the gas distributor 112 can be grounded.

[0026] The first electrode 108 may be connected to a first tuning circuit 128, which controls the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit elements. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit within the processing space 120 during processing that can achieve variable or controllable impedance. In some embodiments, as shown, the first tuning circuit 128 may include a first circuit branch and a second circuit branch that are parallelly coupled between ground and the first electronic sensor 130. The first circuit branch may include a first inductor 132A. The second circuit branch may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B may be located between the first electronic controller 134 and the node connecting the first and second circuit branches to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be connected to the first electronic controller 134, which can realize closed-loop control of plasma conditions within the processing space 120.

[0027] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, perforated plate, mesh, wire mesh, or any other distributed conductive element configuration. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136 via a conduit 146 (e.g., a cable with a selected resistance, such as 50 ohms), which may be located within the axis 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, the second electronic controller 140 being a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control over plasma conditions in the processing space 120.

[0028] The third electrode 124, which may be a bias electrode and / or an electrostatic adsorption electrode, may be connected to the substrate support 104. The third electrode may be connected to the second power supply 150 via a filter 148, which may be an impedance matching circuit. The second power supply 150 may be a DC power supply, a pulsed DC power supply, an RF bias power supply, a pulsed RF source, or a bias power supply, or a combination of these or other power supplies. In some embodiments, the second power supply 150 may be an RF bias power supply.

[0029] The cover assembly 106 and substrate support 104 in Figure 1 can be used in any plasma or thermal processing chamber. During operation, the processing chamber 100 can provide real-time control of plasma conditions within the processing space 120. The substrate 103 can be placed on the substrate support 104, and processing gases can flow through the cover assembly 106 via inlet 114 according to any desired flow rate plan. The gases can be discharged from the processing chamber 100 via outlet 152. Electricity can be connected to the gas distributor 112 to generate plasma within the processing space 120. In some embodiments, the substrate can be electrically biased using a third electrode 124.

[0030] When plasma is initiated in processing space 120, a potential difference may be generated between the plasma and the first electrode 108. A potential difference may also be generated between the plasma and the second electrode 122. Electronic controllers 134 and 140 can then be used to adjust the flow characteristics of the ground path represented by two tuning circuits 128 and 136. Setpoints can be provided to the first tuning circuit 128 and the second tuning circuit 136 to independently control the deposition rate and plasma density uniformity from center to edge. In embodiments where the electronic controllers can both be variable capacitors, electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0031] Each tuning circuit 128, 136 may have a variable impedance, which can be adjusted using its respective electronic controller 134, 140. When the electronic controllers 134, 140 are variable capacitors, the capacitance range of each variable capacitor, as well as the inductance values ​​of the first inductor 132A and the second inductor 132B, may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in minimal area or side coverage of the plasma shape on the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the area coverage of the plasma may increase to its maximum, effectively covering the entire operating area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls, and the area coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect; when the capacitance of the second electronic controller 140 changes, the area coverage of the plasma on the substrate support will increase or decrease.

[0032] Electronic sensors 130 and 138 can be used to adjust their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, each sensor may have a current or voltage setpoint, and control software may be provided for the sensor to determine adjustments to each associated electronic controller 134 and 140 to minimize deviations from the setpoint. Therefore, plasma shape can be selected and dynamically controlled during processing. It should be understood that while the foregoing discussion is based on electronic controllers 134 and 140, which may be variable capacitors, any electronic component with adjustable characteristics can be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0033] Processing chamber 100 may be used in processing methods in some embodiments of the present technology, which may include interstitial materials for semiconductor structures. It should be understood that the described chamber should not be considered limiting, and any chamber that can be configured to perform the described operations can be used similarly. Figure 2 shows an example operation in processing method 200 according to some embodiments of the present technology. The method can be performed in various processing chambers and on one or more hosts or tools, including the processing chamber 100 described above. Method 200 may include a number of optional operations, which may or may not be specifically related to the methods of some embodiments of the present technology. For example, many operations are described to provide a broader scope of structure formation but are not critical to the technology, or may be performed by other methods that will be apparent. Method 200 may describe operations schematically shown in Figures 3A-3E, which will be described together with the operations of method 200. It should be understood that these figures show only partial schematics, and the substrate may contain any number of additional materials and features having the various properties and patterns shown in the figures.

[0034] Method 200 may include additional operations prior to the listed operations. For example, additional processing operations may include forming structures on the substrate, which may involve forming and removing material. For example, transistor structures, memory structures, or any other structures may be formed. The preceding processing operations may be performed within the chamber in which method 200 is performed, or in one or more other processing chambers prior to feeding the substrate into the semiconductor processing chamber. In any case, method 200 may selectively include feeding the semiconductor substrate into a processing region of the semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may contain the aforementioned elements. The substrate may be deposited on a substrate support, which may be a base such as substrate support 104, and may be located within the processing region of the chamber, such as processing space 120 described above.

[0035] As shown in Figure 3A, the substrate after several operations may be substrate 305 of structure 300, which shows a partial view of the substrate undergoing semiconductor processing. It should be understood that structure 300 may only show a few upper layers during processing to illustrate certain aspects of the technology. Substrate 305 can be any material used in semiconductor processing. The substrate material may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials, which may be the materials formed in substrate 305 or in structure 300. Substrate 305 may include material 310, in which one or more features 315 may be formed. Material 310 may be a layer of silicon-containing material. In some embodiments, the silicon-containing material of material 310 may be a silicon-and-germanium-containing material. Although not shown in Figure 3A, it is conceivable that material 310 may be a layer of alternating silicon-and-germanium-containing materials, which includes silicon-containing materials (e.g., silicon) and silicon-and-germanium-containing materials (e.g., silicon-germanium). More specifically, material 310 may be an uppermost silicon- and germanium-containing material deposited above substrate 305, alternating with layers of a second silicon-containing material (e.g., silicon). Substrate 305 may comprise multiple pairs of alternating silicon- and germanium-containing materials and silicon-containing materials. Features 315 formed in material 310 may have any shape or configuration according to the present invention. In some embodiments, features 315 may be or include trench structures or holes formed within material 310 and / or substrate 305.

[0036] Although feature 315 can have any shape or size, in some embodiments, feature 315 may have a high aspect ratio, that is, the ratio between the depth and width of the feature. For example, in some embodiments, the aspect ratio of feature 315 may be greater than or about 1:1, and may be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, greater than or about 60:1, greater than or about 70:1, greater than or about 80:1, greater than or about 90:1, or higher. Furthermore, these features may have a narrower width or diameter, including the dimension between the sidewalls, for example, less than or about 100 nm, and the width of the feature may be less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 40 nm, less than or about 30 nm, or smaller. Furthermore, the depth of these features may be greater than or approximately 100 nm, and may be greater than or approximately 250 nm, greater than or approximately 500 nm, greater than or approximately 750 nm, greater than or approximately 1 µm, greater than or approximately 1.5 µm, greater than or approximately 2 µm, greater than or approximately 2.5 µm, greater than or approximately 3 µm, greater than or approximately 3.5 µm, greater than or approximately 4 µm, greater than or approximately 4.5 µm, greater than or approximately 5 µm, or more.

[0037] Furthermore, although Figure 3A shows that feature 315 extends partially into material 310, it is anticipated that feature 315 may completely penetrate material 310. In addition, feature 315 may extend through other materials beneath material 310, and / or even extend into substrate 305.

[0038] Method 200 may include a gap-filling material for the semiconductor structure. However, to reduce or prevent oxidation of one or more underlying materials deposited within the feature—a phenomenon that may occur in conventional ALD and / or PEALD processes—method 200 may include depositing a pad material on the material deposited beneath the feature to reduce or prevent unwanted oxidation. Therefore, method 200 may include providing one or more deposition precursors to the processing region in step 205. In step 210, method 200 may include contacting substrate 305 with one or more deposition precursors. As shown in FIG3B, this contact may form a pad material 320 that may at least partially cover the feature 315. In some embodiments, the pad material 320 may completely cover the feature 315. As shown in FIG3B, the pad material 320 may be conformal. Depending on the deposition precursor used, the pad material 320 may be a silicon-containing material in some embodiments, such as a silicon-nitrogen-containing material or a silicon, carbon-nitrogen-containing material. After forming the liner material 320, method 200 may include performing an ALD or PEALD process in operation 220, as shown in Figure 3C. The ALD or PEALD process may be a silicon-containing ALD or PEALD process to deposit silicon-containing material 325 in feature 315, for example, in a gap-filling process.

[0039] The one or more deposition precursors provided to the processing area in operation 205 may be or include precursors that can form silicon-containing materials, such as silicon- and nitrogen-containing materials or silicon, carbon, and nitrogen-containing materials. Therefore, the deposition precursors may include one or more of silicon-containing precursors, carbon-containing precursors, nitrogen-containing precursors, or include one or more of silicon, carbon, and / or nitrogen precursors. While any silicon-containing precursor can be used, in some embodiments, the silicon-containing precursors that may be provided in operation 205 include, but are not limited to, silanes (SiH4), bissilanes (Si2H6), trisilanes (Si3H8), tetrasilanes (Si4H10), pentasilanes (Si5H12) or other organosilanes, including cyclohexanes, aminosilanes, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilanes (SiH2Cl2), tetraethoxysilanes (TEOS), and any other silicon-containing materials that can be used or are useful in semiconductor processing. Furthermore, while any carbon-containing precursor can be used, in some embodiments, the carbon-containing precursors that may be provided in operation 205 include, but are not limited to, carbon tetrafluoride (CF4), tetrafluoroethylene (C2F4), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), hydrofluoric acid (or trifluoromethane) (CHF3), difluoromethane (CH2F2), fluoromethane (or methyl fluorine) (CH3F), or other hydrocarbons or chlorofluorocarbons, carbon dioxide (CO2), chlorine sulfite (SO2), carbon monoxide (CO), and any other carbon-containing material that can be used or is useful in semiconductor processing. Similarly, while any nitrogen-containing precursor can be used, in some embodiments, the nitrogen-containing precursors that may be provided in operation 205 include, but are not limited to, diatomic nitrogen (N2), nitrogen trifluoride (NF3), ammonia (NH3), nitrogen dioxide (NO2), nitrous oxide (N2O), and any other nitrogen-containing material that can be used or is useful in semiconductor processing. An exemplary nitrogen-containing precursor might be NH3, which could lead to self-limiting deposition of the pad material 320. NH3 can also act as an inhibitor to reduce or prevent the deposition of silicon-containing material 325 on top of feature 315. This poisoning effect may reduce or prevent clamping or closure on top of feature 315, which could lead to seams or pores in the silicon-containing material 325. In some embodiments, one or more deposition precursors may be oxygen-free to reduce or prevent oxidation of the underlying material (e.g., material 310). Thus, the processing area can be kept oxygen-free during operation 205 while the substrate 305 is in contact with one or more deposition precursors during operation 210. In some embodiments, these one or more deposition precursors may be provided with one or more diluents or carrier gases, such as inert gases or other gases provided with these one or more deposition precursors.

[0040] Some embodiments may include plasma effluents forming one or more deposition precursors. The power applied during deposition may be low-power plasma, which may reduce dissociation and deposition rates. Therefore, in some embodiments, the plasma power source may provide less than or about 5,000 W of plasma power to the panel, chamber, or substrate support, and may provide less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 2,000 W, less than or about 1,500 W, less than or about 1,000 W, less than or about 500 W, or lower. However, in order to deposit higher quality or denser pad material 320, the plasma power source may provide plasma power greater than or about 250W to the panel, chamber or substrate support, and may provide power greater than or about 500W, greater than or about 750W, greater than or about 1,000W, greater than or about 1,250W, greater than or about 1,500W, greater than or about 2,000W, greater than or about 2,500W, greater than or about 3,000W or more.

[0041] In some embodiments, the deposited pad material 320 may be deposited using an ALD or PEALD process. Any other thermal deposition or plasma-enhanced deposition process may also be considered for depositing the pad material 320. However, performing an ALD or PEALD process to deposit the pad material 320 may increase the conformability of the pad material 320. The ALD or PEALD process may also make the deposition of silicon- and nitrogen-containing pad materials self-limiting. For depositing the pad material 320, the ALD or PEALD process may involve layer-by-layer deposition, such as of silicon- and nitrogen-containing materials. The ALD or PEALD process may include a first precursor dose, such as a silicon-containing precursor dose or a nitrogen-containing precursor dose. In the PEALD process, a plasma effluent of the first precursor dose may be formed. The first precursor dose or the plasma effluent formed therefrom may be adsorbed onto the substrate 305 or material 310 by means of chemisorption or the like. A first purification may be performed to remove excess portions of the first precursor dose, such as the first precursor that was not adsorbed onto the substrate 305 or the material 310.

[0042] Following the first cleanup, the ALD or PEALD process may include a second precursor dose, such as a silicon-containing precursor dose or a nitrogen-containing precursor dose (as opposed to the first precursor dose). During the PEALD process, plasma effluent of the second precursor dose may be formed. The second precursor, or the plasma effluent formed therefrom, may react with the first precursor dose adsorbed on substrate 305 or material 310. The reaction between the first and second precursor doses may form a pad material 320. A second cleanup may be performed to remove excess portions of the second precursor dose, such as second precursor that did not react with the first precursor to form the pad material 320. After the second cleanup, the operations of first precursor dose, first cleanup, second precursor dose, and second cleanup may be repeated any number of times to continue forming the pad material 320.

[0043] In some embodiments, the deposition thickness of the pad material 320 is less than or about 10 nm. When the thickness increases, for example, to more than 10 nm, the pad material 320 may not be able to be converted into a gap-filling material, such as silicon-containing material 325, in subsequent ALD or PEALD processes, as described below. Therefore, the deposition thickness of the pad material 320 may be less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4.8 nm, less than or about 4.6 nm, less than or about 4.4 nm, less than or about 4.2 nm, less than or about 4.0 nm, less than or about 3.8 nm, less than or about 3.6 nm, less than or about 3.5 nm, less than or about 3.4 nm, less than or about 3.3 nm, less than or about 3.2 nm, less than or about 3.1 nm, less than or about 3.0 nm, or less. However, with reduced thickness, the liner material 320 may not be sufficient to prevent the diffusion of oxygen-containing precursors used in subsequent ALD or PEALD processes through the liner material, and may cause oxidation of the material 310. Therefore, the deposition thickness of the liner material 320 may be greater than or about 1.0 nm, greater than or about 1.2 nm, greater than or about 1.4 nm, greater than or about 1.6 nm, greater than or about 1.8 nm, greater than or about 2.0 nm, greater than or about 2.1 nm, greater than or about 2.2 nm, greater than or about 2.3 nm, greater than or about 2.4 nm, greater than or about 2.5 nm, greater than or about 2.6 nm, greater than or about 2.7 nm, greater than or about 2.8 nm, greater than or about 2.9 nm, greater than or about 3.0 nm, or more.

[0044] After a period of time has elapsed since the formation of the pad material 320, method 200 may include stopping the flow of one or more deposition precursors. Stopping the flow of one or more deposition precursors may halt deposition, such as in an ALD or PEALD process. This period may be sufficient to form the pad material 320 to the desired thickness, such as any thickness previously discussed, to reduce or prevent oxidation of the material 310. By reducing or preventing oxidation of the material 310 on top of the feature 315, the silicon-containing material 325 can be deposited without damaging the underlying material 320. Thus, the deposited pad material 320 may reduce or prevent oxidation, which may result in rounding of the upper surface of the material 320 defining the feature 315.

[0045] As previously discussed, in operation 220, after forming the pad material 320, method 200 may include performing an ALD or PEALD process, such as a silicon-containing ALD or PEALD process. Similar to the ALD or PEALD process for depositing the pad material 320, the silicon-containing ALD or PEALD process may involve layer-by-layer deposition of the silicon-containing material 325. The silicon-containing ALD or PEALD process may include a first precursor dose, such as a silicon-containing precursor dose or an oxygen-containing precursor dose. In the PEALD process, a plasma effluent of the first precursor dose may be formed. The first precursor dose, or if formed, plasma effluent, may be adsorbed onto the substrate 305 or material 310 by chemisorption. A first cleanup may be performed to remove excess portions of the first precursor dose, such as first precursor that has not yet been adsorbed onto the substrate 305 or material 310.

[0046] Following the first purification, the silicon-containing ALD or PEALD process may include a second precursor dose, such as a silicon-containing precursor dose or an oxygen-containing precursor (a component opposite to the first precursor dose). During the PEALD process, plasma effluent of the second precursor dose may form. The second precursor, or if formed, its plasma effluent may react with the first precursor dose adsorbed on substrate 305 or material 310. The reaction between the first and second precursor doses can form silicon-containing material 325. A second purification may be performed to remove excess second precursor dose, such as second precursors that have not reacted with the first precursor to form silicon-containing material 325.

[0047] During the oxygen-containing precursor dosage, whether it is the first precursor dosage or the second precursor dosage, the liner material 320 may be at least partially, if not completely, converted into a silicon- and oxygen-containing material. The oxygen-containing precursor or its plasma effluent may react with, for example, the silicon- and carbon-containing material of the liner material 310 to form volatiles that can be decontaminated from the processing area. For example, the oxygen-containing precursor may react with the silicon- and carbon-containing material of the liner material 310 to form CO, CO2, N2O, NO2, or other gaseous carbon-, nitrogen-, and / or oxygen-containing materials that can be discharged from the processing area. Reducing or removing the liner material 320 may facilitate the deposition of silicon-containing materials to fill features 315 after filling those features without the presence of the liner material 320, such as carbon or nitrogen in the liner material 320. Therefore, as shown in Figures 3C-3E, the silicon-containing ALD or PEALD process can fill feature 315 with silicon-containing material 325 without allowing the liner material 320 to be inserted into or present between material 310 and silicon-containing material 325. These operations, including second purification, first precursor dosage, first purification, second precursor dosage, and second purification, can be repeated multiple times to continuously form silicon-containing material 325.

[0048] While any silicon-containing precursor can be used, in some embodiments, the silicon-containing precursors used in silicon-containing ALD or PEALD processes may include, but are not limited to, SiH4, Si2H6, Si3H8, Si4H10, Si5H12, or other organosilanes, including cyclohexane, aminosilane, SiF4, SiCl4, SiH2Cl2, TEOS, and any other silicon-containing materials that can be used or are useful in semiconductor processing. Similarly, while any oxygen-containing precursor can be used, in some embodiments, the oxygen-containing precursors used in silicon-containing ALD or PEALD processes may include, but are not limited to, diatomic oxygen (O2), N2O, hydrogen peroxide (H2O2), ozone (O3), or other oxygen-containing materials that can be used or are useful in semiconductor processing.

[0049] In the case of plasma enhancement, the power applied in silicon-containing PEALD may be greater than or approximately 100W from the plasma power source to the panel, chamber, or substrate support, and may be greater than or approximately 250W, greater than or approximately 500W, greater than or approximately 1,000W, greater than or approximately 1,500W, greater than or approximately 2,000W, greater than or approximately 2,500W, greater than or approximately 3,000W, greater than or approximately 3,500W, greater than or approximately 4,000W, greater than or approximately 4,500W, greater than or approximately 5,000W, greater than or approximately 5,500W, greater than or approximately 6,000W, greater than or approximately 7,000W, greater than or approximately 8,000W, or more. Plasma power may affect deposition rate, conformability, and / or the quality of the deposited material. For example, higher plasma power may deposit higher quality materials and / or deposit materials at a higher deposition rate, but may damage other materials or structures on substrate 305.

[0050] As previously described, these operations can be repeated any number of times after the second purification, the first precursor dosage, the first purification, the second precursor dosage, and the second purification to continue forming the silicon-containing material 325. However, in order to maintain a bottom-up, zipper-like filling method while reducing the formation of seams or pores, method 200 may include intermittently performing operations 205-210 to deposit the liner material 310.

[0051] Because of the presence of the backing material 320, performing an ALD or PEALD process to deposit the silicon-containing material 325 may reduce (or oxidize) the thickness of the upper surface of the material 310, as shown in the thickness d in Figure 3E, by less than or approximately 5 nm. In some embodiments, the presence of the pad material 320 may result in a reduction (or oxidation) in the upper surface thickness of the layer of material 310 by less than or about 4.8 nm, less than or about 4.6 nm, less than or about 4.4 nm, less than or about 4.2 nm, less than or about 4.0 nm, less than or about 3.8 nm, less than or about 3.6 nm, less than or about 3.4 nm, less than or about 3.2 nm, less than or about 3.0 nm, less than or about 2.8 nm, less than or about 2.6 nm, less than or about 2.4 nm, less than or about 2.2 nm, less than or about 2.0 nm, less than or about 1.9 nm, less than or about 1.8 nm, less than or about 1.7 nm, less than or about 1.6 nm, less than or about 1.5 nm, or less.

[0052] Temperature may affect the operation of this technique. For example, method 200 can be performed at a temperature less than or about 600°C, or at a temperature less than or about 575°C, less than or about 550°C, less than or about 525°C, less than or about 500°C, less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, less than or about 325°C, less than or about 300°C, or lower. Furthermore, method 200 can be performed at temperatures greater than or approximately 100°C, or at temperatures greater than or approximately 300°C, and can be performed at temperatures greater than or approximately 325°C, greater than or approximately 350°C, greater than or approximately 375°C, greater than or approximately 400°C, greater than or approximately 425°C, greater than or approximately 450°C, greater than or approximately 475°C, greater than or approximately 500°C, greater than or approximately 525°C, greater than or approximately 550°C, greater than or approximately 575°C, greater than or approximately 600°C, or higher. Throughout the entire process of method 200, including during poisoning and deposition, the temperature can be maintained within any of these ranges. However, it is also considered that the temperature may be adjusted between operations.

[0053] Pressure may also affect the operation of this technique. For example, method 200 may be performed under pressure less than or about 50 Torr, and may be performed under pressure less than or about 40 Torr, less than or about 30 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr or lower.

[0054] In the foregoing description, numerous details have been set forth for illustrative purposes in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without or with additional details thereof.

[0055] After disclosing several embodiments, those skilled in the art will recognize that various modifications, alternative constructions, and equivalent changes can be made without departing from the spirit of these embodiments. Furthermore, to avoid unnecessarily obscuring the art, many well-known processes and elements have not been described. Therefore, the above description should not be considered as limiting the scope of the art. Additionally, methods or processes may be described as sequential or step-by-step, but it should be understood that these operations may be performed simultaneously or in a different order than listed.

[0056] If a range of values ​​is provided, it should be understood that every intermediate value between the upper and lower limits of the range, especially the smallest decimal part, is specifically disclosed unless the context explicitly specifies otherwise. Any narrow range within a specified range, whether an explicitly stated value or an unstated intermediate value, and any other explicitly stated or intermediate value within that specified range, are included. The upper and lower limits of these narrow ranges may be independently included or excluded from the range, and each range, whether any, both, or both of its limitations are included within the narrow range, is also included in the technique along with any limitations explicitly excluded from the specified range. If a specified range includes one or two of its boundaries, ranges excluding any one or both included boundaries are also included.

[0057] In the scope of this document and the appended claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly specifies otherwise. Thus, for example, reference to “first silicon-containing material” includes a plurality of such materials, and reference to “the deposition precursor” includes reference to one or more precursors and their equivalents, as will be apparent to those skilled in the art.

[0058] Furthermore, when the words "comprising," "including," "having," and "containing" are used in this specification and the following claims, they are intended to specify the presence of the stated features, integers, elements, or operations, but do not preclude the presence or addition of one or more other features, integers, elements, operations, behaviors, or groups.

[0059] 100: Processing Chamber 102: Main body of the chamber 103:Substrate 104: Substrate support 105: Substrate support 106: Cover component 108: First electrode 110a: Isolator 110b: Isolator 111: Plasma Profile Modulator 112: Gas distributor 114: Entrance 118: Kong 120: Processing space 122: Second electrode 124: Third electrode 126: Opening 128: Tuning Circuit 130: Electronic sensor 132: Inductor 132A: First Inductor 132B: Second Inductor 134: Electronic Controller 136: Tuning Circuit 138: Electronic Sensor 140: Electronic Controller 142: First Power Supply 144: Axis 145: Arrow 146: Catheter 147: Axis 148: Filter 150: Second power supply 152: Exports 200: Method 205: Operation 210: Operation 220: Operation 300: Structure 305:Substrate 310: Materials 315: Features 320: Padding material 325: Silicon-containing materials d: thickness

Claims

1. A semiconductor processing method comprising the steps of: providing one or more deposition precursors to a processing region of a semiconductor processing chamber, wherein a substrate is located within the processing region, and wherein a first silicon-containing material defining one or more features is disposed on the substrate; contacting the substrate with the one or more deposition precursors, wherein the contact deposits a pad material on the first silicon-containing material; performing an atomic layer deposition (ALD) process, wherein the ALD process deposits a silicon and oxygen-containing material in the one or more features, wherein performing the ALD process reduces the thickness of an upper surface of the layer of the first silicon-containing material to less than or about 5 nm.

2. The semiconductor processing method as claimed in claim 1, wherein the deposition precursors include a silicon-containing precursor, a carbon-containing precursor, or a nitrogen-containing precursor.

3. The semiconductor processing method as claimed in claim 1, wherein the deposition precursors comprise diatomic nitrogen (N2) or ammonia (NH3).

4. The semiconductor processing method as claimed in claim 1, wherein the first silicon-containing material comprises a silicon- and germanium-containing material.

5. The semiconductor processing method as claimed in claim 1, wherein the layer of the first silicon-containing material and the layer of the second silicon-containing material are alternately disposed on the substrate.

6. The semiconductor processing method as claimed in claim 1, wherein the thickness of the pad material is less than or about 10 nm.

7. The semiconductor processing method as claimed in claim 1, wherein the pad material comprises a silicon- and nitrogen-containing material.

8. The semiconductor processing method of claim 1, wherein contacting the substrate with the one or more deposition precursors to deposit the pad material includes performing an ALD process for the pad material.

9. The semiconductor processing method as claimed in claim 1, wherein performing the ALD process converts the pad material into a silicon- and oxygen-containing material.

10. The semiconductor processing method as claimed in claim 1, wherein the ALD process includes a gap-filling operation.

11. A semiconductor processing method comprising the steps of: performing a first atomic layer deposition (ALD) process on a substrate located in a processing region of a semiconductor processing chamber, wherein a silicon-containing material defining one or more features is disposed on the substrate, and wherein the first ALD process deposits a silicon- and nitrogen-containing material on the silicon-containing material; stopping the first ALD process; and performing a second ALD process on the substrate, wherein the second ALD process deposits a silicon- and oxygen-containing material in the one or more features, wherein the silicon- and nitrogen-containing material reduces the underlying oxidation of the layer of the silicon-containing material.

12. The semiconductor processing method as claimed in claim 11, wherein the silicon- and nitrogen-containing material is conformal.

13. The semiconductor processing method of claim 11, wherein the first ALD process includes sequentially exposing the substrate to a silicon-containing precursor and a nitrogen-containing precursor.

14. The semiconductor processing method as claimed in claim 13, wherein the nitrogen-containing precursor comprises ammonia (NH3).

15. The semiconductor processing method as described in claim 11, wherein, After the second ALD process, the silicon and nitrogen-containing material is converted into a silicon and oxygen-containing material.

16. A semiconductor processing method comprising the steps of: performing a first atomic layer deposition (ALD) process on a substrate located in a processing region of a semiconductor processing chamber, wherein alternating layers of a silicon-containing material and a silicon-and-germanium-containing material defining one or more features are disposed on the substrate, and wherein the first ALD process conformally deposits a silicon-and-nitrogen-containing pad material on the alternating layers of the silicon-containing material and the silicon-and-germanium-containing material; stopping the first ALD process after the silicon-and-nitrogen-containing pad material has been formed to a thickness greater than or about 2 nm; performing a second ALD process on the substrate, wherein the second ALD process deposits a silicon-and-oxygen-containing material in the one or more features, wherein the silicon-and-nitrogen-containing pad material reduces the underlayer oxidation of the alternating layers of the silicon-containing material and the silicon-and-germanium-containing material.

17. The semiconductor processing method of claim 16, wherein the deposition of the silicon and nitrogen-containing pad material is self-limiting.

18. The semiconductor processing method as described in claim 16, wherein, Following the second ALD process, the silicon and nitrogen-containing liner material is converted into a silicon and oxygen-containing material.

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