Method and apparatus of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes depositing a photoresist composition over a target layer on a substrate to form a photoresist layer. This photoresist layer is selectively exposed to photochemical radiation. After selective exposure, a vacuum is applied to the photoresist layer. O2 and H2O are introduced into the selectively exposed photoresist layer. The selectively exposed photoresist layer is baked. After baking, the photoresist layer is developed. The target layer is etched using this photoresist layer as an etch mask.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generations of ICs, each smaller and more complex than the previous one. In the development of ICs, functional density (i.e., the number of interconnects per die area) typically increases, while geometric dimensions (i.e., the smallest element (or wiring) that can be created using manufacturing processes) decrease. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. Such scaling also increases the complexity of handling and manufacturing ICs. For continued progress, similar advancements in IC handling and manufacturing are necessary. However, as the size of individual devices shrinks, the process window for photolithography becomes increasingly tight. Therefore, advancements in photolithography are essential to maintaining the ability to scale down devices, and further improvements are needed to meet desired design standards, enabling continued progress towards increasingly smaller devices. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various embodiments disclosed herein are best understood from the following description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 illustrates a process flow for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 2 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figures 3A and 3B illustrate the sequential operation of process stages according to embodiments of the present disclosure. Figure 4 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figures 5A and 5B illustrate the sequential operation of process stages according to embodiments of the present disclosure. Figure 6 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figure 7 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figures 8A and 8B illustrate organometallic precursors according to embodiments of the present disclosure. Figure 8C illustrates the reactions experienced by the organometallic precursors upon exposure to photochemical radiation. Figure 8D illustrates an example of an organometallic precursor according to embodiments of the present disclosure. Figure 9 illustrates a deposition apparatus according to an embodiment of this disclosure. Figure 10 illustrates a post-exposure baking apparatus according to an embodiment of this disclosure. Figure 11A illustrates the reaction experienced by a photoresist layer according to an embodiment of the present disclosure due to exposure to photochemical radiation and heating. Figure 11B illustrates the reaction experienced by a photoresist layer according to an embodiment of the present disclosure due to exposure to photochemical radiation and heating. Figures 12A and 12B illustrate controllers used to control photoresist deposition operations and / or post-exposure baking operations and / or other baking operations during the methods disclosed herein. Figure 13 illustrates the sequential operation of a process stage according to an embodiment of the present disclosure. Figures 14A and 14B illustrate the sequential operation of process stages according to embodiments of the present disclosure. Figure 15 illustrates the sequential operation of a process stage according to an embodiment of the present disclosure. Figures 16A and 16B illustrate the sequential operation of process stages according to embodiments of the present disclosure. Figure 17 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figure 18 illustrates the sequential operation of process stages according to an embodiment of the present disclosure. Figures 19A and 19B illustrate the sequential operation of process stages according to embodiments of the present disclosure. Implementation

[0005] It should be understood that the following disclosure provides many different embodiments or instances for implementing various features of this disclosure. Specific embodiments or instances of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired nature of the apparatus. Furthermore, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed to insert into the first and second features, such that the first and second features are not in direct contact. For simplicity and clarity, various features may be drawn at arbitrary different scales.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower part," "above," "upper part," "top," "bottom," "middle," and similar terms may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures, without excluding additional structures above, below, or between said features. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of."

[0007] Furthermore, in subsequent manufacturing processes, one or more additional operations may exist between the described operations, and the order of operations may be changed. In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C (A, B, C, A and B, A and C, B and C, or A, B, and C)," and unless otherwise described, does not mean an element from A, an element from B, and an element from C. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more drawings) may be used in other embodiments, and detailed descriptions thereof may be omitted.

[0008] To achieve smaller feature sizes and feature pitches in semiconductor devices, improved contrast between exposed and unexposed areas of the photoresist layer is desirable. Embodiments disclosed herein provide improved contrast between exposed and unexposed areas of the photoresist layer during semiconductor device fabrication. Embodiments disclosed herein provide improved integrity of the photoresist pattern and reduced linewidth and line edge roughness, as well as reduced dross. Embodiments disclosed herein allow for reduced exposure dose.

[0009] Figure 1 illustrates a flowchart of a method 100 for manufacturing a semiconductor device according to some embodiments. Figures 2 through 18 illustrate cross-sectional views of a semiconductor device at various manufacturing stages according to some embodiments. These figures collectively describe method 100 and the systems utilized in the method.

[0010] In some embodiments, method 100 includes an operation S105 of forming a target layer 60 over a substrate 10. In some embodiments, the substrate 10 is a semiconductor substrate. In some embodiments, the semiconductor substrate 10 is a semiconductor wafer, such as a silicon wafer. In some embodiments, the target layer 60 is an insulating layer; in other embodiments, the target layer 60 is a semiconductor layer; and in other embodiments, the target layer 60 is a conductive layer.

[0011] In some embodiments, a resist layer composition is subsequently coated onto the surface of the substrate 10 or the target layer 60 in operation S110 to form a resist layer 15, as shown in Figure 2. In some embodiments, the resist layer 15 is a photoresist layer. Then, in some embodiments, the resist layer 15 undergoes a first baking operation S115 (or a pre-exposure baking operation) to evaporate the solvent in the resist composition or to cure the resist layer. The resist layer 15 is baked at a temperature and time sufficient to cure and dry the photoresist layer 15. In some embodiments, the resist layer is heated at a temperature of about 40°C to about 150°C for about 10 seconds to about 10 minutes.

[0012] Following the first (or pre-exposure) baking operation S115 of the photoresist layer 15, in operation S120, the photoresist layer 15 is selectively exposed to photochemical radiation 45 / 97 (see Figures 3A and 3B). In some embodiments, the radiation is electromagnetic radiation, such as g-line (436 nm wavelength), i-line (365 nm wavelength), ultraviolet radiation, deep ultraviolet radiation, extreme ultraviolet radiation, or an electron beam, or the like. In some embodiments, the radiation source is selected from the group consisting of: mercury vapor lamps, xenon lamps, carbon arc lamps, KrF excimer laser light (248 nm wavelength), ArF excimer laser light (193 nm wavelength), F2 excimer laser light (157 nm wavelength), or Sn plasma excited by CO2 laser light (extreme ultraviolet, 13.5 nm wavelength).

[0013] As shown in Figure 3A, in some embodiments, exposure radiation 45 passes through the photomask 30 before irradiating the photoresist layer 15. In some embodiments, the photomask has a pattern to be replicated in the photoresist layer 15. In some embodiments, the pattern is formed by an opaque pattern 35 on the photomask substrate 40. The opaque pattern 35 may be formed of a material that is opaque to ultraviolet radiation (such as chromium), while the photomask substrate 40 may be formed of a material that is transparent to ultraviolet radiation (such as fused silica).

[0014] In some embodiments, extreme ultraviolet (EUV) lithography is used to selectively expose the photoresist layer 15 to form exposed regions 50 and unexposed regions 52. In some embodiments of EUV lithography operation, a reflective photomask 65 is used to form patterned exposure light, as shown in Figure 3B. The reflective photomask 65 includes a low thermal expansion glass substrate 70 on which a Si and Mo reflective multilayer 75 is formed. A capping layer 80 and an absorption layer 85 are formed on the reflective multilayer 75. A rear conductive layer 90 is formed on the back side of the low thermal expansion glass substrate 70. In EUV lithography, extreme ultraviolet radiation 95 is directed toward the reflective photomask 65 at an incident angle of approximately 6°. A portion 97 of the EUV radiation is reflected by the Si / Mo multilayer 75 toward the photoresist-coated substrate 10, while a portion of the EUV radiation 95 incident on the absorption layer 85 is absorbed by the photomask. In some embodiments, additional optics, including a mirror, are positioned between the reflective photomask 65 and the photoresist-coated substrate.

[0015] The region 50 of the photoresist layer exposed to radiation 45 undergoes a chemical reaction, thereby altering its solubility in a subsequently applied developer relative to the region 52 of the photoresist layer not exposed to radiation. In some embodiments, the portion 50 of the photoresist layer exposed to radiation 45 undergoes a crosslinking reaction.

[0016] The amount of electromagnetic radiation can be characterized by flux or dose, which is obtained by integrating the radiative flux over exposure time. Suitable radiative flux ranges in some embodiments are from about 1 mJ / cm² to about 150 mJ / cm², in other embodiments from about 2 mJ / cm² to about 100 mJ / cm², and in still other embodiments from about 3 mJ / cm² to about 50 mJ / cm². Those skilled in the art will recognize that additional ranges of radiative flux within the aforementioned defined ranges are contemplated and are within the scope of this disclosure.

[0017] In some embodiments, selective or patterned exposure is performed using a scanning electron beam. Electron beam lithography is employed, where the electron beam induces secondary electrons that modify the irradiated material. High resolution can be achieved using electron beam lithography and the metal-containing resists disclosed herein. The electron beam can be characterized by its energy, and in some embodiments, a suitable energy range is from about 5 V to about 200 kV, while in other embodiments, a suitable energy range is from about 7.5 V to about 100 kV. The near-corrected beam dose at 30 kV is from about 0.1 μC / cm² to about 100 μC / cm² in some embodiments, from about 0.5 μC / cm² to about 25 μC / cm² in others, and from about 1 μC / cm² to about 5 μC / cm² in still others. Those skilled in the art can calculate the corresponding dose at other beam energies based on the teachings herein, and will recognize that an additional range of electron beam properties within the aforementioned defined ranges is contemplated and falls within the scope of this disclosure.

[0018] Next, in operation S125, the photoresist layer 15 undergoes a second bake (or post-exposure bake, PEB). In some embodiments, the photoresist layer 15 is heated at a temperature ranging from about 20°C to about 400°C for about 20 seconds to about 1500 seconds. In other embodiments, the photoresist layer 15 is heated at a temperature ranging from about 50°C to about 250°C for about 50 seconds to about 1000 seconds. In some embodiments, the post-exposure bake facilitates the crosslinking of the radiation-exposed photoresist. In some embodiments, the post-exposure bake facilitates the generation, dispersion, and reaction of chemical reactants formed during photochemical radiation exposure, including acids or bases generated by the action of photochemical radiation. PEB facilitates the generation or enhancement of chemical reactions that create a chemical difference between the exposed region 50 and the unexposed region 52 within the photoresist layer.

[0019] In some embodiments, during PEB operation S130, a mixture 125 of oxygen (O2) and water (H2O) is applied to the resist layer 15, as shown in Figure 4. In some embodiments, water is applied as steam, gas (vapor), or mist. During PEB, oxygen promotes crosslinking in the photochemical radiation exposed regions 50 of the photoresist layer, while water inhibits the crosslinking reaction in the photochemical radiation unexposed regions 52 of the photoresist layer. As shown in Figure 4, in some embodiments, the PEB operation takes place in a baking chamber 110. The resist-coated substrate is supported on a substrate support stage 115 in the baking chamber 110. In some embodiments, the substrate support stage 115 includes a heater for heating the resist-coated substrate during PEB operation. Water and oxygen may be introduced into the chamber 110 via inlets 120a and 120b, respectively.

[0020] Baking chamber 110 may be a vacuum chamber. In some embodiments, PEB operation S125 is performed under reduced pressure. In some embodiments, a vacuum is applied to baking chamber 110 in operation S135 before and / or during PEB operation S125. Baking chamber 110 may be evacuated using a vacuum pump via exhaust device 130.

[0021] In some embodiments, during PEB operation S125, an additional gas may be applied in operation S140. In some embodiments, the additional gas includes at least one of SO2, CO2, NH3, and acetic acid. The additional gas may assist the crosslinking reaction in the photochemical radiation exposure region 50 of the photoresist layer.

[0022] Subsequently, in operation S145, the selectively exposed photoresist layer is developed by applying a developer to it. As shown in Figure 5A, developer 57 is supplied from dispenser 62 to photoresist layer 15. In some embodiments, developer 105 is a dry developer, as shown in Figure 5B. In some embodiments, unexposed areas 52 of the photoresist layer are removed by developer 57, 105, thereby forming a pattern of openings 55 in the photoresist layer 15, thereby exposing portions of the substrate 10, as shown in Figure 6.

[0023] In some embodiments, the photoresist developer 57 comprises a solvent and an acid or base. In some embodiments, the concentration of the solvent is from about 60% by weight to about 99% by weight, based on the total weight of the photoresist developer 57. The concentration of the acid or base is from about 0.001% by weight to about 20% by weight, based on the total weight of the photoresist developer 57. In some embodiments, the concentration of the acid or base in the developer 57 is from about 0.01% by weight to about 15% by weight, based on the total weight of the photoresist developer 57.

[0024] In some embodiments, a developer 57 is applied to the photoresist layer 15 using a spin coating process. During the spin coating process, the developer 57 is applied from above the photoresist layer 15 while the photoresist-coated substrate is rotated, as shown in Figure 5A. In some embodiments, the developer 57 is supplied at a rate between about 5 ml / min and about 800 ml / min, while the photoresist-coated substrate 10 rotates at a speed between about 100 rpm and about 2000 rpm. In some embodiments, the developer 57 is at a temperature between about 10°C and about 80°C during the development operation. In some embodiments, the development operation lasts between about 30 seconds and about 10 minutes.

[0025] In some embodiments, developer 57 is an organic solvent. The organic solvent can be any suitable solvent. In some embodiments, the solvent is selected from one or more of the following: propylene glycol methyl ether acetate (PGME), propylene glycol monomethyl ether (PGME), 1-ethoxy-2-propanol (PGEE), γ-butyrolactone (GBL), cyclohexanone (CHN), ethyl lactate (EL), methanol, ethanol, propanol, n-butanol, 4-methyl-2-pentanol, acetone, methyl ethyl ketone, dimethylformamide (DMF), isopropanol (IPA), tetrahydrofuran (THF), methyl isobutyl carbinol (MIBC), n-butyl acetate (nBA), 2-heptanone (MAK), and dioxane.

[0026] While spin coating is a suitable method for developing the photoresist layer 15 after exposure, it is intended to be illustrative and not to limit the embodiments. Instead, any suitable developing operation, including immersion processes, melt pool processes, and spraying methods, may be used. All such developing operations are included within the scope of the embodiments.

[0027] In some embodiments, a dry developer 105 is applied to a selectively exposed photoresist layer 15, as shown in Figure 5B. In some embodiments, the dry developer 105 is a plasma or chemical vapor, and the dry development operation S145 is a plasma etching or chemical etching operation. Dry development uses differences related to composition, degree of crosslinking, and film density to selectively remove desired portions of the photoresist. In some embodiments, the dry development process uses a gentle plasma (high voltage, low power) or a thermal process in a heated vacuum chamber while dry development chemicals (such as Cl2, CHCl3, CH2Cl2, CH4, CF4, N2, BF3, BCl3, CCl4, HCl, O2, NF3, NH3, N2H2, HBr, and NO2, or other Lewis acids in a vapor state) are flowing. In some embodiments, the developer 105 removes unexposed material, leaving a pattern of the exposed film, which is transferred to the underlying layer by a plasma-based etching process.

[0028] In some embodiments, dry development includes a plasma process, including transformer-coupled plasma (TCP), inductively coupled plasma (ICP), or capacitively coupled plasma (CCP). In some embodiments, the plasma process is performed for about 1 to about 3000 seconds at a pressure ranging from about 5 mTorr to about 20 mTorr, a power level ranging from about 250 W to about 1000 W, a temperature ranging from about 0°C to about 300°C, and a flow rate ranging from about 100 to about 1000 sccm.

[0029] In some embodiments, the dry development reaction is as follows: MOxCy + HX → MxCy + H2O; where MOxCy is a photoresist, HX is a developer gas, and MxCy is a developing product, which is a gas under low pressure.

[0030] In some embodiments, in operation S150, the pattern of the opening 55 in the photoresist layer 15 is extended into the substrate 10 or the target layer 60 (see Figure 18) to create a pattern of opening 55' in the substrate 10 or the target layer 60, thereby transferring the pattern in the photoresist layer 15 into the substrate 10 or the target layer 60, as shown in Figures 7 and 18. The pattern is extended into the substrate or target layer by etching using one or more suitable etchants. In some embodiments, the patterned photoresist layer pattern 15 is at least partially removed during the etching operation. In some embodiments, after etching the substrate 10 or the target layer, the patterned photoresist layer 15 is removed by using a suitable photoresist stripping solvent or by a photoresist ashing operation.

[0031] In some embodiments, the substrate 10 includes at least a single-crystal semiconductor layer on its surface portion. The substrate 10 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. In some embodiments, the substrate 10 is made of crystalline Si.

[0032] The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers can be used to gradually change the lattice constant from that of the substrate to the lattice constant of the subsequently formed source / drain regions. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, a silicon-germanium (SiGe) buffer layer is epitaxially grown on the silicon substrate 10. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percentages in the bottom buffer layer to 70 atomic percentages in the top buffer layer.

[0033] In some embodiments, the substrate 10 includes one or more layers of at least one metal, metal alloy, and metal nitride / sulfide / oxide / silicide having the formula MXa, wherein M is a metal, X is N, S, Se, O, or Si, and α is about 0.4 to about 2.5. In some embodiments, the substrate 10 includes titanium, aluminum, cobalt, ruthenium, titanium nitride, tungsten nitride, tantalum nitride, and combinations thereof.

[0034] In some embodiments, the substrate 10 includes a dielectric of at least a silicon or metal oxide or nitride having the formula MXb, wherein M is a metal or Si, X is N or O, and b ranges from about 0.4 to about 2.5. In some embodiments, the substrate 10 includes silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, lanthanum oxide, and combinations thereof.

[0035] The photoresist layer 15 is a photosensitive layer patterned by exposure to photochemical radiation. Generally, the chemical properties of the photoresist regions irradiated by incident radiation change depending on the type of photoresist used. The photoresist layer 15 can be a positive or negative photoresist. A positive photoresist refers to a photoresist material in which, during development, the portions of the photoresist layer exposed to photochemical radiation (such as ultraviolet light) are removed, while the unexposed (or less exposed) areas of the photoresist remain on the substrate after the development operation. Conversely, a negative photoresist refers to a photoresist material in which, during development, the portions of the photoresist exposed to photochemical radiation remain on the substrate after the development operation, while the unexposed (or less exposed) areas of the photoresist are removed during the development operation.

[0036] In some embodiments, the photoresist layer 15 is made of a photoresist composition comprising a first compound or first precursor and a second compound or second precursor combined in a vapor state. The first precursor or first compound is an organometallic compound having the formula: MaRbXc (a, b, and c are natural numbers), as shown in Figures 8A and 8B, wherein M is selected from one or more of the group consisting of: Sn, Bi, Sb, In, Te, and their oxides; and R is a substituted or unsubstituted alkyl, alkenyl, or carboxylic acid group. In some embodiments, X is a ligand, ion, or other substituent that reacts with the second compound or second precursor; and 1 ≦ a ≦ 2, b ≧ 1, c ≧ 1, and b + c ≦ 4. In some embodiments, b + c = 4. In some embodiments, the alkyl, alkenyl, or carboxylic acid group is substituted with one or more fluorine groups. In some embodiments, the organometallic precursor system is a dimer, as shown in Figure 8A, wherein each monomer unit is linked by an amino group. In some embodiments, b=c=2. In other embodiments, the organometallic precursor system is a dimer, as shown in Figure 8B, wherein each monomer unit is linked by an oxygen group. In some embodiments, b=1 and c=3. Each monomer has the following formula: MaRbXc, as defined above.

[0037] In some embodiments, R in the formula MaRbXc comprises an alkyl group substituted with different electron-donating groups (EDG) and / or electron-withdrawing groups (EGG) to tune the bond dissociation energy to provide a bond that can be cleaved by a low EUV dose. In some embodiments, R is a substituted or unsubstituted C1-C20 alkyl group, including all isomers of C1-C20 alkyl groups. EDG includes oxonium (-O-), amino (-NH2, -NHR, -NR2, where R = C1-C4 alkyl and phenyl), hydroxyl and alkoxy (-OH, -OR, where R = C1-C4 alkyl and phenyl), acetamino (-NHCOR, where R = C1-C4 alkyl and phenyl), alkylthio and mercapto (-SH, -SR, where R = C1-C4 alkyl and phenyl), phenyl, and carboxylate (-(C=O)O-). EWG includes halogens (-I, -Cl, -Br, -F), ammonium groups (-NR3+, where R = C1-C4 group and phenyl), nitro groups (-NO2), sulfonic acids and sulfonyl groups (-SO3H, -SO2R, where R = C1-C4 group and phenyl), cyano groups (-CN), methyl and acetoyl groups (-CHO, -COR, where R = C1-C4 group and phenyl), carboxyl and alkoxycarbonyl groups (-CO2H, -CO2R, where R = C1-C4 group and phenyl), and aminocarbonyl groups (-CONH2, -CONHR, -CONR, where R = C1-C4 group and phenyl), wherein the C1-C4 group includes all isomers of the C1-C4 group.

[0038] In some embodiments of the first precursor or compound having the formula MaRbXc, R comprises all structural isomers of C1-C4 alkyl groups substituted with phenyl, amino (-NH2, -NHR, -NR2, wherein R = C1-C3 alkyl), hydroxyl, and alkoxy (-OH, -OR, wherein R = C1-C3 alkyl and phenyl). In some embodiments of the first precursor or compound having the formula MaRbXc, R comprises C1-C4 alkyl groups substituted with one or two phenyl, amino (-NH2, -NHR, -NR2, wherein R = C1, C2, or C3 alkyl) and alkoxy (-OR, wherein R = C1, C2, or C3 alkyl) groups at the α-C position.

[0039] In some embodiments, the X group is readily replaced by a second compound or a second precursor to generate an M-OH group, such as a group selected from amines, including dialkylamines and monoalkylamines; alkoxy groups; carboxyl groups, halogens, and sulfonates. In some embodiments, the sulfonate group is substituted with one or more amino groups. In some embodiments, the halogen group is selected from one or more of the group consisting of F, Cl, Br, and I. In some embodiments, the sulfonate group includes substituted or unsubstituted C1-C3 groups.

[0040] In some embodiments, R in formula MaRbXc includes C7-C11 aralkyl groups, such as benzyl, ethylbenzyl, propylbenzyl, isopropylbenzyl, butylbenzyl, secondary butylbenzyl, or tertiary butylbenzyl; C3-C10 cycloalkyl groups, such as cyclobutyl, methylcyclobutyl, ethylcyclobutyl, cyclopentyl, methylcyclopentyl, ethylcyclopentyl, cyclohexyl, methylcyclohexyl, ethylcyclohexyl, cycloheptyl, or cyclooctyl; C2-C10 alkyl groups. Oxide groups, such as dimethyl ether, methyl dimethyl ether, ethyl methyl ether, diethyl ether, dipropyl ether, propyl ethyl ether, propyl methyl ether, diisopropyl ether, isopropyl ethyl ether, or isopropyl methyl ether; or C2-C10 alkylamino groups, such as methyl dimethylamino, dimethylamino, diethylamino, ethyl dimethylamino, dipropylamino, diisopropylamino, isopropyl methylamino, or isopropyl ethylamino. In some embodiments, R includes cyclopentyl, benzyl, methyl ether, ethyl ether, secondary amino, or tertiary amino.

[0041] In some embodiments, the X-group in formula MaRbXc is a C2-C10 alkylamine group, such as dimethylamino, diethylamino, dipropylamino, diisopropylamino, methylethylamino, methylpropylamino, ethylpropylamino, or halogen, such as F, Cl, Br, or I. In some embodiments, the X-group is dimethylamino or diethylamino, and c = 3. In some embodiments, the M-group is Sn and the a-group is 1. In some embodiments, 1 ≦ a ≦ 2, b ≧ 1, c ≧ 1, and b + c ≦ 4. In some embodiments, the b-group is 1, 2, or 3. In some embodiments, the c-group is 1, 2, or 3. In some embodiments, b + c = 4, and in other embodiments, b = 1 and c = 3.

[0042] In some embodiments, the first compound or first precursor includes one or more unsaturated bonds that can coordinate with functional groups (such as hydroxyl groups) on the substrate surface or intermediate lower layer to improve the adhesion of the photoresist layer to the substrate or lower layer.

[0043] In some embodiments, the second precursor or second compound is selected from one or more of the group consisting of water, amines, boranes, and phosphine. In some embodiments, the amine has the formula NpHnXm, where 0 ≦ n ≦ 3, 0 ≦ m ≦ 3, n + m = 3 when p is 1, and n + m = 4 when p is 2, and each X is independently selected from a halogen of the group consisting of F, Cl, Br, and I. In some embodiments, the borane has the formula BpHnXm, where 0 ≦ n ≦ 3, 0 ≦ m ≦ 3, n + m = 3 when p is 1, and n + m = 4 when p is 2, and each X is independently selected from a halogen of the group consisting of F, Cl, Br, and I. In some embodiments, phosphine has the formula PpHnXm, where 0 ≦ n ≦ 3, 0 ≦ m ≦ 3, n + m = 3 when p is 1, or n + m = 4 when p is 2, and each X is independently selected from the group consisting of halogens F, Cl, Br, and I.

[0044] In some embodiments, the second precursor or compound is ammonia or hydrazine. The reaction product of ammonia or hydrazine with the organometallic precursor or compound can form hydrogen bonds. These hydrogen bonds increase the boiling point of the reaction product and prevent the volatilization of the metal photoresist material, thereby preventing metal contamination. Hydrogen bonds also help prevent the humidity effect that degrades the quality of the photoresist layer.

[0045] In some embodiments, the first organometallic compound or first organometallic precursor comprises a metal core M+, to which a ligand L is attached, as shown in Figure 8C. In some embodiments, the metal core M+ is a metal oxide. In some embodiments, the ligand L comprises a C3-C12 aliphatic or aromatic group. The aliphatic or aromatic group may be unbranched or branched with cyclic or acyclic saturated dangling groups containing 1-9 carbons, including alkyl, alkenyl, and phenyl groups. The branched group may be further substituted with oxygen or halogen. In some embodiments, the C3-C12 aliphatic or aromatic group comprises a heterocyclic group. In some embodiments, the C3-C12 aliphatic or aromatic group is attached to the metal by ether or ester bonding. In some embodiments, the C3-C12 aliphatic or aromatic group comprises nitrite and sulfonate substituents.

[0046] In some embodiments, the organometallic precursor or organometallic compound includes dihexyltris(dimethylamino)tin, trihexyltris(dimethylamino)tin, isohexyltris(dimethylamino)tin, n-hexyltris(dimethylamino)tin, dipentyltris(dimethylamino)tin, tripentyltris(dimethylamino)tin, isopentyltris(dimethylamino)tin, n-pentyltris(dimethylamino)tin, dibutyltris(dimethylamino)tin, tributyltris(dimethylamino)tin, isobutyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, dibutyltris(dimethylamino)tin, and isopropyltris(dimethylamino)tin. n-Propyltris(diethylamino)tin, and similar alkyltris(tributoxy)tin compounds, including dihexyltris(tributoxy)tin, trihexyltris(tributoxy)tin, isohexyltris(tributoxy)tin, n-hexyltris(tributoxy)tin, dipentyltris(tributoxy), tripentyltris(tributoxy)tin, isopentyltris(tributoxy)tin, n-pentyltris(tributoxy)tin, tributyltris(tributoxy)tin, isobutyltris(butoxy)tin, n-butyltris(butoxy)tin, dibutyltris(butoxy)tin, isopropyltris(butoxy)tin, or n-propyltris(butoxy)tin. In some embodiments, the organometallic precursor or organometallic compound is fluorinated. In some embodiments, the organometallic precursor or compound has a boiling point below about 200°C.

[0047] Figure 8D illustrates an example of an organometallic precursor according to an embodiment of the present disclosure. In Figure 8D, Bz represents a phenyl group.

[0048] In some embodiments, the organometallic compound includes tin (Sn), antimony (Sb), bismuth (Bi), indium (In), tellurium (Te), and / or its oxides as the metal component; however, this disclosure is not limited to these metals. In other embodiments, additional suitable metals include titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), cobalt (Co), molybdenum (Mo), tungsten (W), aluminum (Al), gallium (Ga), silicon (Si), germanium (Ge), phosphorus (P), arsenic (As), yttrium (Y), lanthanum (La), cerium (Ce), lutetium (Lu), or their oxides and combinations thereof. Additional metals may be used as substitutes for or supplements to Sn, Sb, Bi, In, and / or Te.

[0049] The specific metal used can significantly affect radiation absorption. Therefore, the metal composition can be selected based on the desired radiation and absorption cross-section. Tin, antimony, bismuth, tellurium, and indium provide strong absorption of extreme ultraviolet light at 13.5 nm. Hafnium provides good absorption of electron beams and extreme ultraviolet radiation. Metal compositions including titanium, vanadium, molybdenum, or tungsten exhibit strong absorption at longer wavelengths to provide, for example, sensitivity to ultraviolet light at a wavelength of 248 nm.

[0050] In some embodiments, the photoresist is a chemically amplified photoresist. In some embodiments, the chemically amplified photoresist according to this disclosure comprises a polymer in a solvent along with one or more photoactive compounds (PACs). In some embodiments, the polymer comprises a hydrocarbon structure (such as an alicyclic hydrocarbon structure) containing one or more groups that will decompose (e.g., acidic unstable groups) or otherwise react (as further described below) when mixed with an acid, a base, or a free radical generated by the PAC. In some embodiments, the hydrocarbon structure comprises repeating units that form the backbone of the polymer resin. This repeating unit may include acrylates, methacrylates, crotonates, vinyl esters, maleic acid diesters, trans-butenedioic acid diesters, itconic acid diesters, (meth)acrylonitrile, (meth)acrylamide, styrene, vinyl ethers, combinations thereof, or the like.

[0051] In some embodiments, the decomposed group (also referred to as an acid labile group (ALG)) is attached to the hydrocarbon structure such that it will react with the acid / base / free radicals generated by the PAC during exposure. In some embodiments, the decomposed group is a carboxylic acid group, a fluorinated alcohol group, a phenolic alcohol group, a sulfonyl group, a sulfonamide group, a sulfonimide group, a (alkylsulfonyl)(alkylcarbonyl)methylene group, a (alkylsulfonyl)(alkylcarbonyl)imethylene group, a bis(alkylcarbonyl)methylene group, a bis(alkylcarbonyl)imethylene group, a bis(alkylsulfonyl)methylene group, a bis(alkylsulfonyl)imethylene group, a tri(alkylcarbonyl)methylene group, a tri(alkylsulfonyl)methylene group, a combination of these, or the like. Specific groups used for fluorinated alcohol groups include fluorinated hydroxyalkyl groups, such as hexafluoroisopropanol groups in some embodiments. Specific groups used for carboxylic acid groups include acrylate groups, methacrylate groups, or the like. In some embodiments, the polymer in the photoresist composition is based on a polymer of polyhydroxystyrene, polyacrylate, or polymethyl methacrylate.

[0052] In some embodiments, PAC includes photoacid generators, photobase generators, free radical generators, or the like. In some embodiments where PAC is a photoacid generator, PAC includes triazine halides, onium salts, diazonium salts, aromatic diazonium salts, phosphonium salts, strontium salts, monazine salts, acetylene sulfonates, oxime sulfonates, diazonium sulfonates, diazonium sulfonates, o-nitrobenzyl sulfonates, sulfonated esters, halogenated sulfonoxydimethimide, α-cyanooxyamine sulfonates, ketone diazonium sulfonate, sulfonyl diazonium esters, 1,2-bis(arylsulfonyl)hydrazine, nitrobenzyl esters, and s-triazine derivatives, combinations thereof, or the like.

[0053] As those skilled in the art will recognize, the compounds listed herein are intended only as illustrative examples of PACs and are not intended to limit the embodiments to those specifically described. Rather, any suitable PAC may be used, and all such PACs are fully intended to be included within the scope of these embodiments.

[0054] In some embodiments, the photoresist composition deposition operation S110 is performed by spin coating. In some embodiments, the photoresist composition deposition operation S110 is performed by vapor deposition.

[0055] In some embodiments, vapor deposition operations include atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, ALD includes plasma-enhanced atomic layer deposition (PE-ALD), and CVD includes plasma-enhanced chemical vapor deposition (PE-CVD), metal-organic chemical vapor deposition (MO-CVD), atmospheric pressure chemical vapor deposition (AP-CVD), and low pressure chemical vapor deposition (LP-CVD). Depositing a photoresist layer includes combining a first compound or first precursor and a second compound or second precursor in a vapor state to form a photoresist composition. In some embodiments, the first compound or first precursor and the second compound or second precursor of the photoresist composition are introduced into the deposition chamber (CVD chamber) approximately simultaneously. In some embodiments, the first compound or first precursor and the second compound or second precursor are introduced into the deposition chamber (ALD chamber) in an alternating manner, that is, first the first compound or precursor, then the second compound or precursor, and then the introduction of one compound or precursor followed by the second compound or precursor is repeated alternately.

[0056] In some embodiments, the deposition chamber temperature ranges from about 30°C to about 400°C during deposition operations, and in other embodiments between about 50°C and about 250°C. In some embodiments, the pressure in the deposition chamber ranges from about 5 mTorr to about 100 Torr during deposition operations, and in other embodiments between about 100 mTorr and about 10 Torr. In some embodiments, the plasma power is less than about 1000 W. In some embodiments, the plasma power ranges from about 100 W to about 900 W. In some embodiments, the flow rates of the first compound or precursor and the second compound or precursor range from about 100 sccm to about 1000 sccm. In some embodiments, the flow ratio of the organometallic compound or precursor to the second compound or precursor ranges from about 1:1 to about 1:10, and in other embodiments from about 1:3 to 1:6. Operating parameters outside the above ranges result in unsatisfactory photoresist layers in some embodiments. In some embodiments, photoresist layer formation occurs in a single chamber (one-pot formation).

[0057] In CVD processes according to some embodiments of the present disclosure, two or more gas streams of an organometallic precursor and a second precursor are introduced into the deposition chamber of a CVD apparatus through separate inlet paths, where they mix and react in the gas phase to form reaction products. In some embodiments, a separate injection inlet or a dual-chamber spray head is used to introduce the streams. The deposition apparatus is configured such that the streams of the organometallic precursor and the second precursor are mixed in the chamber, allowing the organometallic precursor and the second precursor to react to form reaction products. Without limiting the mechanisms, functions, or utility of the present disclosure, it is believed that the products from the gas-phase reaction become heavier in molecular weight and are then condensed or otherwise deposited onto a substrate.

[0058] In some embodiments, the ALD process is used to deposit a photoresist layer. During ALD, a layer is grown on the substrate by exposing the surface of the substrate to alternating gaseous compounds (or precursors). Compared to CVD, the precursors are introduced as a series of sequential, non-overlapping pulses. In each of these pulses, the precursor molecules react with the surface in a self-limiting manner, such that the reaction terminates once all reaction sites on the surface have been consumed. Therefore, the maximum amount of material deposited on the surface after a single exposure to all the precursors (the so-called ALD cycle) is determined by the nature of the precursor-surface interaction.

[0059] In one embodiment of the ALD method, an organometallic precursor is pulsed in the first half of the reaction to deliver a metal-containing precursor to the substrate surface. In some embodiments, the organometallic precursor reacts with a suitable underlying species (e.g., OH or NH functional groups on the substrate surface) to form a new self-saturating surface. In some embodiments, excess unused reactants and reaction byproducts are removed by evacuation and / or by circulating an inert purge gas. Then, in some embodiments, a second precursor (such as water or ammonia (NH3)) is pulsed into the deposition chamber. The water or NH3 reacts with the organometallic precursor on the substrate to obtain the reaction product photoresist on the substrate surface. The second precursor also forms self-saturating bonds with the underlying reactants to provide another self-limiting and saturated second half of the reaction. In some embodiments, a second purge is performed to remove unused reactants and reaction byproducts. The pulses of the first and second precursors are alternated with the intermediate purge operation until the desired thickness of the photoresist layer 15 is achieved.

[0060] In some embodiments, the photoresist layer 15 is formed to a thickness of about 5 nm to about 50 nm, and in other embodiments to a thickness of about 10 nm to about 30 nm. Those skilled in the art will recognize that additional ranges of thickness within the aforementioned defined range are contemplated and within the scope of this disclosure. Based on the optical properties of the photoresist layer, the thickness can be evaluated using non-contact methods of X-ray reflectance and / or ellipsometrics. The photoresist layer thickness is relatively uniform for ease of handling. In some embodiments, the variation in coating thickness is no greater than ±25% of the average coating thickness, and in other embodiments, the variation is no greater than ±10%. In some embodiments, such as highly uniform coatings on larger substrates, the uniformity of the photoresist layer can be evaluated using a 1 cm edge exclusion method; that is, the uniformity of the layer is not evaluated for coating portions within 1 cm of the edge. Those skilled in the art will recognize that additional ranges within the aforementioned defined range are contemplated and within the scope of this disclosure.

[0061] In some embodiments, the first and second compounds or precursors are delivered into the deposition chamber together with the carrier gas. The carrier gas, purge gas, deposition gas, or other process gas may contain nitrogen, hydrogen, argon, neon, helium, or combinations thereof.

[0062] A resist layer deposition apparatus 200 according to some embodiments of the present disclosure is illustrated in Figure 9. In some embodiments, the deposition apparatus 200 is an ALD or CVD apparatus. The deposition apparatus 200 includes a vacuum chamber 205. A substrate support stage 210 in the vacuum chamber 205 supports a substrate 10, such as a silicon wafer. In some embodiments, the substrate support stage 210 includes a heater. In some embodiments, a first precursor or compound gas supplier 220 and a carrier gas / purification gas supplier 225 are connected to an inlet 230 in the chamber via a gas line 235, and a second precursor or compound gas supplier 240 and a carrier gas / purification gas supplier 225 are connected to another inlet 230' in the chamber via another gas line 235'. The chamber is evacuated, and excess reactants and reaction byproducts are removed by a vacuum pump 245 via an outlet 250 and an exhaust line 255. In some embodiments, the flow rate or pulse of the precursor gas and carrier gas / purification gas, the evacuation of excess reactants and reaction byproducts, the pressure within the vacuum chamber 205, and the temperature of the vacuum chamber 205 or the substrate support stage 210 are controlled by a controller 260, which controls each of these parameters.

[0063] In some embodiments, ALD or CVD deposition parameters are varied during the deposition operation to form a photoresist layer with a density gradient. In some embodiments, the density gradient photoresist layer reduces defects such as scum and bridging; and improves line width roughness (LWR) and line edge roughness (LER).

[0064] The semiconductor manufacturing apparatus 180 according to an embodiment of the present disclosure includes a baking chamber 110 and a semiconductor substrate support stage 115 in a heating chamber, as shown in Figure 10. In some embodiments, a post-exposure baking operation S125 or other baking operations, including a pre-exposure baking operation S115, are performed in the baking chamber 110. In some embodiments, a plurality of inlet ports 120a, 120b, 120c and at least one exhaust port 130 are included. The inlet ports 120a, 120b, 120c are connected to photoresist layer processing sources 140, 145, 150, 155 via connecting lines 160a, 160b, 160c, respectively. The photoresist layer processing sources 140 and 145 include an oxygen source and a water source, respectively. In some embodiments, additional photoresist layer processing sources 150 and 155 include at least one of an SO2 source, a CO2 source, NH3, and an acetic acid source. In some embodiments, the additional photoresist processing material is a gas. In some embodiments, the additional processing material is an acid or an alkali. Additional acidic and alkaline treatments can break the bonds of alkyl substituents in the photoresist composition and thereby promote cross-linking reactions in the photochemical radiation exposure region 50 of the photoresist layer. The photoresist treatment material can be in the form of a gas, vapor, or liquid, such as a fine mist. In some embodiments, water and oxygen are combined outside the baking chamber and then introduced as a mixture into the baking chamber. In some embodiments, at least one of the additional photoresist layer treatment sources 150, 155 contains a carrier gas or a purge gas or other process gas. The carrier gas, purge gas, or other process gas includes nitrogen, hydrogen, argon, neon, helium, or combinations thereof. The size, shape, or number of inlet or outlet ports depends on the chamber design and the amount and type of photoresist treatment material used in the specific operation.

[0065] In some embodiments, the substrate support 115 includes a heating element to heat the resist-coated substrate 10 during PEB operation. In some embodiments, the semiconductor substrate support 115 is a heat-generating plate. In some embodiments, a vacuum pump 135 is connected via a connection line 165 to an exhaust port 130 to provide a depressurized environment.

[0066] The device also includes a controller 175, which is programmed to: control the flow of photoresist layer treatment material through inlet ports 120a, 120b, and 120c into the baking chamber 110; control a vacuum pump to control the exhaust flow from the heating chamber through exhaust port 130 and control the pressure in the baking chamber 110; control the heater of the substrate support stage 115 to regulate the temperature of PEB operation; and control the concentrations of oxygen, water, and any additional photoresist layer treatment material. In some embodiments, the device includes at least one of an oxygen sensor 170a, a water sensor 170b, a temperature sensor 170c, and a pressure sensor 170d. In some embodiments, the device further includes at least one sensor 170e to sense any additional gases or photoresist treatment material.

[0067] The positions of the inlet ports 120a, 120b, 120c, exhaust port 130, sensors 170a, 170b, 170c, 170d, 170e, substrate support 115, and other components shown in Figure 10 are for illustrative purposes only, and the various components can be arranged in any feasible or suitable location or arrangement.

[0068] In some embodiments, during PEB operation S125, one or more parameters are controlled, wherein these parameters are selected from: the flow of photoresist layer treatment material entering the baking chamber, the exhaust gas flow from the baking chamber, the temperature of the baking chamber, and the concentration of the photoresist layer treatment material.

[0069] In some embodiments, the photoresist layer 15 is heated at a temperature of about 20°C to about 400°C for about 20 seconds to about 1500 seconds. In other embodiments, the photoresist layer 15 is heated at a temperature ranging from about 50°C to about 250°C for about 50 seconds to about 1000 seconds. At temperatures and heating times below the disclosed range, the contrast of the photoresist pattern may not be adequately improved. At temperatures and heating times above the disclosed range, the semiconductor device structure beneath the photoresist layer may be damaged.

[0070] In some embodiments, during PEB operation S125, the flow rate of the processed material flowing into the baking chamber ranges from about 5 L / min to about 40 L / min. In other embodiments, the flow rate of the processed material entering the heating chamber ranges from about 10 L / min to about 30 L / min.

[0071] In some embodiments, during PEB operation S125, the flow rate of the exhaust gas from the baking chamber ranges from about 10 L / min to about 50 L / min. In other embodiments, the flow rate of the exhaust gas from the baking chamber ranges from about 20 L / min to about 40 L / min. Inlet and exhaust gas flow rates below the disclosed ranges may result in inadequate treatment of the photoresist. Flow rates above the disclosed ranges may result in turbulence and may cause metallic contaminants to flow out of the photoresist layer.

[0072] In some embodiments, the concentrations of O2 and H2O vary during the baking of the photoresist layer. In some embodiments, the oxygen concentration is greater than the water concentration during PEB operation S125. In some embodiments, the molar ratio of oxygen to the total amount of oxygen and water in the baking chamber is maintained in the range greater than about 0.2 to less than about 1 during PEB operation S125. In some embodiments, the oxygen to water molar ratio is adjusted during PEB operation S125. In some embodiments, the molar ratio is changed in a smooth gradient manner; in other embodiments, the oxygen to water concentration ratio is changed in a gradual manner during PEB operation S125. In some embodiments, the water concentration in the baking chamber is maintained in the range of about 20 ppm to about 2000 ppm during PEB operation S125. In other embodiments, the water concentration ranges from about 40 ppm to about 1000 ppm. At oxygen and water concentrations outside the disclosed ranges, the contrast of the photoresist pattern may not be adequately improved.

[0073] In some embodiments, the PEB operation is performed in multiple steps. For example, in one embodiment, a first baking step includes a high oxygen / water ratio to advance the crosslinking reaction in the photochemical radiation-exposed region. Then, in a second baking step, the oxygen / water ratio is reduced and the concentration of the inert carrier gas is increased to increase the hardness of the resist.

[0074] In some embodiments, the pressure inside the baking chamber during PEB operation S125 ranges from 1 Torr to 700 Torr. In other embodiments, the pressure inside the baking chamber ranges from about 10 Torr to about 600 Torr. At baking chamber pressures outside the disclosed range, the contrast of the photoresist pattern may not be adequately improved.

[0075] In some embodiments, during the dry development operation S145, the development operation S145 is performed in the same baking chamber 110 and the PEB operation S125. In some embodiments, at least one of the photoresist layer processing sources 150, 155 includes developer gas.

[0076] Figure 11A illustrates the reactions experienced by the photoresist composition components according to an embodiment of the present disclosure due to exposure to photochemical radiation and heating. Figure 11A also illustrates the exemplary chemical structures of the photoresist layer (PR) at various stages of the photoresist patterning method according to an embodiment of the present disclosure. As shown in Figure 11A, the photoresist composition includes an organometallic compound (e.g., SnX2R2) and a second compound (e.g., ammonia (NH3)). When the organometallic compound and ammonia combine, the organometallic compound reacts with some ammonia in the gas phase to form a reaction product having amine groups of a metal (Sn) attached to the organometallic compound. The amine groups in the deposited photoresist layer have hydrogen bonds, which can significantly increase the boiling point of the deposited photoresist layer and prevent degassing of the metal-containing photoresist material, thereby preventing metal contamination of the deposition chamber and semiconductor device processing equipment in the metal-containing photoresist. Furthermore, the hydrogen bonds of the amine groups can control the effect of humidity on the quality of the photoresist layer.

[0077] When subsequently exposed to extreme ultraviolet (EUV) radiation using a mask, the organometallic compound absorbs the UV radiation, and one or more organo-R groups cleave from the organometallic compound to form an amine-metallic compound in the radiation-exposed area. Then, in some embodiments, the amine-metallic compound is cross-linked via amine groups during post-exposure baking (PEB), as shown in Figure 11A. In some embodiments, partial cross-linking of the amine-metallic compound occurs as a result of exposure to UV radiation. The selectively exposed photoresist is then developed, and during development, the cross-linked radiation-exposed pattern remains above the substrate, while the unexposed radiation areas are removed.

[0078] Figure 11B illustrates the reactions experienced by the photoresist composition components according to an embodiment of the present disclosure due to exposure to photochemical radiation and heating. Figure 11B also illustrates the exemplary chemical structures of the photoresist layer (PR) at various stages of the photoresist patterning method according to an embodiment of the present disclosure. As shown in Figure 11B, the photoresist composition includes an organometallic compound (e.g., SnX3R) and a second compound (e.g., water (H2O)). When the organometallic compound and water (vapor) are combined in a CVD process, the organometallic compound reacts with some water in the gas phase by substituting X with -OH to form a reaction product having hydroxyl groups (-OH) attached to the metal (Sn) of the organometallic compound. Furthermore, the reaction product undergoes a CVD process to form a film over a substrate, wherein in some embodiments the hydroxyl metal compound is cross-linked via hydroxyl groups.

[0079] The cross-linked structure in the deposited photoresist layer can significantly increase the boiling point of the deposited photoresist layer and prevent the degassing of the metal-containing photoresist material, thereby preventing metal contamination of the deposition chamber and semiconductor device processing equipment in the metal-containing photoresist.

[0080] When subsequently exposed to extreme ultraviolet (EUV) radiation using a mask, the organometallic compound absorbs the UV radiation, and one or more organic R groups cleave from the organometallic compound to form cross-linked metal oxide compounds in the radiation-exposed areas. In some embodiments, hydrogen is left behind when the organic R groups cleave. Then, in some embodiments, the cross-linked metal oxide compounds are further cross-linked via hydrogen and oxygen during post-exposure baking (PEB), as shown in Figure 11B. In some embodiments, partial cross-linking occurs due to exposure to UV radiation. The selectively exposed photoresist is then developed, and during development, the cross-linked radiation-exposed pattern remains above the substrate, while the unexposed radiation areas are removed.

[0081] Figures 12A and 12B illustrate a controller for controlling post-exposure baking operation S125 and other operations (such as pre-exposure baking operation S115 and developing operation S145). In some embodiments, computer system 1200 is used as a controller for controlling the baking operation. In some embodiments, the same computer system 1200 is used as a controller 260 for controlling photoresist deposition operation S110 and a controller 175 for controlling PEB operation S125. All or part of the processes, methods, and / or operations of the above embodiments can be implemented using computer hardware and computer programs executed thereon. In Figure 12A, computer system 1200 includes a computer 1201, a keyboard 1202, a mouse 1203, and a monitor 1204. This computer includes an optical disc read-only memory (e.g., CD-ROM or DVD-ROM) drive 1205 and a disk drive 1206.

[0082] Figure 12B illustrates the internal configuration of computer system 1200. In Figure 12B, in addition to optical disc drive 1205 and magnetic disk drive 1206, computer 1201 also includes one or more processors, such as a microprocessor unit (MPU) 1211, a ROM 1212 storing programs such as boot programs, random access memory (RAM) 1213 connected to the MPU 1211 and temporarily storing application program commands and providing temporary storage areas, a hard disk 1214 storing application programs, system programs, and data, and a bus 1215 connecting the MPU 1211, ROM 1212, and the like. Note that computer 1201 may include a network card (not shown) for providing a connection to a LAN.

[0083] The program for enabling computer system 1200 to perform the functions of the apparatus for baking the coated substrate in any of the foregoing embodiments may be stored on optical disc 1221 or magnetic disk 1222, which is inserted into optical disc drive 1205 or magnetic disk drive 1206 and transferred to hard disk 1214. Alternatively, the program may be transferred to computer 1201 via a network (not shown) and stored on hard disk 1214. During execution, the program is loaded into RAM 1213. The program may be loaded from optical disc 1221 or magnetic disk 1222, or directly from the network. The program need not include, for example, an operating system (OS) or third-party programs to enable computer 1201 to perform the baking operations in the foregoing embodiments. The program may only include a command portion to invoke appropriate functions (modules) in a controlled mode and obtain the desired results.

[0084] In some embodiments, a target layer 60 to be patterned is disposed above a substrate before the resist layer 15 is formed, as shown in Figure 13. In some embodiments, the target layer 60 is a semiconductor layer; a conductive layer, such as a metallization layer; or a dielectric layer, such as a passivation layer disposed above a metallization layer. In some embodiments where the target layer 60 is a metallization layer, the target layer 60 is formed from a conductive material using metallization processes and metal deposition techniques (including electroplating, chemical vapor deposition, atomic layer deposition, and physical vapor deposition (sputtering)). Similarly, in some embodiments where the target layer 60 is a dielectric layer, the target layer 60 is formed using dielectric layer formation techniques (including thermal oxidation, chemical vapor deposition, atomic layer deposition, and physical vapor deposition). In some embodiments, the target layer 60 is a bottom antireflective coating (BAC) layer made of an organic polymer or a silicon-containing material.

[0085] The photoresist layer 15 is then selectively or patternedly exposed to photochemical radiation 45 / 97 to form exposed regions 50 and unexposed regions 52 in the photoresist layer, as shown in Figures 14A and 14B, and as described herein with respect to Figures 3A and 3B.

[0086] Then, as shown in Figure 15, the photoresist layer 15, which has been selectively exposed or patterned, undergoes a post-exposure baking operation, as described herein with respect to Figure 4.

[0087] Following PEB operation S125, the photoresist layer 15 is developed (as shown in Figures 16A and 16B) to form a pattern of photoresist openings 55 (as shown in Figure 17). Unexposed photoresist areas 52 are developed by dispensing developer 57 from dispenser 62 (as shown in Figure 16A) or by a dry development operation (as shown in Figure 16B) to form photoresist patterns 55 (as shown in Figure 17). The development operation is similar to the operation explained herein with reference to Figures 5A, 5B, and 6.

[0088] Then, as shown in Figure 17, the pattern 55 in the photoresist layer 15 is transferred onto the target layer 60 using a suitable etching operation, and the photoresist layer is removed (as explained with reference to Figure 7) to form the pattern 55 in the target layer 60.

[0089] In some embodiments, a lower resist layer 20 is formed over the substrate 10 or target layer 60 prior to the formation of the resist layer 15, as shown in Figures 19A and 19B. In some embodiments, the lower resist layer 20 improves the adhesion of the resist layer 15 to the substrate or target layer. In some embodiments, the lower resist layer 20 serves as a bottom antireflective coating. The BARC absorbs photochemical radiation passing through the photoresist layer, thereby preventing photochemical radiation from being reflected from the substrate or target layer and exposing unintended portions of the photoresist layer. Therefore, the BARC improves the linewidth roughness and line edge roughness of the photoresist pattern. In some embodiments, the BARC is made of: an organic polymer; an inorganic polymer, such as polysiloxane; or a silicon-containing layer, such as silicon oxide. The structures shown in Figures 19A and 19B then undergo the operations disclosed herein with reference to Figure 1 to form a semiconductor device.

[0090] Other embodiments include additional operations before, during, or after the operations described above. In one embodiment, the method includes forming field-effect transistor structures, including fin field-effect transistors (FinFETs) and gate-all-around field-effect transistors (GAAFETs). In some embodiments, a plurality of active fins are formed on a semiconductor substrate. Such embodiments further include etching the substrate through an opening in a patterned hard mask to form trenches in the substrate; filling the trenches with a dielectric material; performing a chemical mechanical polishing (CMP) process to form shallow trench isolation (STI) features; and epitaxially growing or recessing the STI features to form fin-shaped active regions. In another embodiment, the method includes additional operations such as forming a plurality of gate electrodes on a semiconductor substrate. The method may further include forming gate spacers, doped source / drain regions, contacts for gate / source / drain features, etc. In another embodiment, the target pattern will be formed as metal wiring in a multilayer interconnect structure. For example, metal interconnects can be formed in an inter-layer dielectric (ILD) layer of a substrate, which has been etched to form a plurality of trenches. The trenches can be filled with a conductive material, such as a metal; and a process such as chemical mechanical planarization (CMP) can be used to polish the conductive material to expose the patterned ILD layer, thereby forming the metal interconnects within the ILD layer. The above are non-limiting examples of devices / structures that can be manufactured and / or improved using the methods described herein.

[0091] As described above, a semiconductor wafer can be an intermediate structure manufactured during the processing of an IC or a portion thereof, which may include logic circuits, memory structures, passive components (such as resistors, capacitors, and inductors), and active components (such as diodes, field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, three-dimensional (3D) FETs, other memory cells), and combinations thereof.

[0092] The embodiments disclosed herein offer advantages over the prior art, although it should be understood that other embodiments may offer different advantages, but not all advantages need to be discussed herein, and not all embodiments require a particular advantage. Oxygen added to the PEB operation promotes photoresist crosslinking in the photochemically exposed regions, while water added to the PEB operation inhibits crosslinking reactions in the non-exposed regions. In some embodiments, additional photoresist treatment material added to the PEB operation promotes crosslinking reactions in the photochemically exposed regions. The embodiments disclosed herein provide improved contrast between exposed and non-exposed regions of the photoresist layer during semiconductor device fabrication. The embodiments disclosed herein provide improved local critical size uniformity. The embodiments disclosed herein provide improved pattern density-induced loading effects. The embodiments disclosed herein provide improved integrity of the photoresist pattern and reduced linewidth roughness and line edge roughness, as well as reduced dross. The embodiments disclosed herein allow for reduced exposure dose.

[0093] In one embodiment of this disclosure, a method of manufacturing a semiconductor device includes depositing a photoresist composition over a target layer on a substrate to form a photoresist layer. This photoresist layer is selectively exposed to photochemical radiation. After selective exposure, a vacuum is applied to the photoresist layer. O2 and H2O are introduced into the selectively exposed photoresist layer. The selectively exposed photoresist layer is baked. After baking, the photoresist layer is developed. The target layer is etched using this photoresist layer as an etch mask. In one embodiment, the photoresist composition is deposited by spin coating. In one embodiment, the photochemical radiation is extreme ultraviolet radiation. In one embodiment, during baking of the selectively exposed photoresist layer, the concentration of at least one of the O2 and H2O introduced into the selectively exposed photoresist layer is varied. In one embodiment, the photoresist layer is baked in a baking chamber, and during baking, the pressure inside the baking chamber ranges from 1 Torr to 700 Torr. In one embodiment, the pressure in the baking chamber is changed during the baking of the photoresist layer. In one embodiment, additional gas is introduced into the baking chamber during the baking of the photoresist layer. In one embodiment, the additional gas system is selected from at least one of sulfur dioxide, carbon dioxide, ammonia, and acetic acid. In one embodiment, the photoresist layer is baked while O2 and H2O are introduced into the selectively exposed photoresist layer. In one embodiment, the photoresist composition includes a metal.

[0094] Another embodiment disclosed herein is a method of manufacturing a semiconductor device, comprising depositing a metal resist layer over a substrate and patterning the resist layer under photochemical radiation. A vacuum is applied to the patterned resist layer. A gaseous mixture of oxygen and water is applied to the patterned resist layer, and the patterned resist layer is heated. After heating the patterned resist layer, the resist layer is developed using a dry developer to form a patterned resist layer. The portion of the substrate exposed by the patterned resist layer is removed. In one embodiment, during heating the patterned resist layer, the concentration of at least one of the oxygen and water applied to the patterned resist layer is varied. In one embodiment, the application of the vacuum, the application of the gas mixture, and the heating of the patterned resist layer are performed in a single chamber. In one embodiment, during heating the patterned resist layer, the pressure in the chamber is varied. In one embodiment, during the heating of the patterned photoresist layer, additional gas is introduced into the chamber. In one embodiment, this additional gas system is selected from at least one of sulfur dioxide, carbon dioxide, ammonia, and acetic acid.

[0095] Another embodiment disclosed herein is a method of manufacturing a semiconductor device, comprising combining a first resist precursor and a second resist precursor to form a resist layer over a substrate, thereby forming a resist-coated substrate. The resist layer is selectively exposed to photochemical radiation to form a latent image in the resist layer. After selective exposure of the resist layer, the resist-coated substrate is transferred to a chamber. After transferring the resist-coated substrate to the chamber, the pressure within the chamber is reduced. The resist-coated substrate is baked in the chamber. A mixture of O2 and H2O is applied to the resist-coated substrate in the chamber, and after applying the mixture of O2 and H2O to the resist-coated substrate, a developer is applied to the resist-coated substrate to form a patterned resist layer. In one embodiment, applying the developer to the resist-coated substrate includes applying a dry developer to the resist-coated substrate. In one embodiment, the developer is applied to the resist-coated substrate within the chamber. In another embodiment, the method includes using the patterned resist layer as an etching mask to etch the substrate.

[0096] Another embodiment of this disclosure is a semiconductor device manufacturing apparatus, comprising: a chamber, a vacuum pump connected to the chamber, a semiconductor substrate support in the chamber, at least one gas flow inlet in the chamber, at least one gas flow exhaust device in the chamber, a heater, and a controller. The controller is programmed to: control the vacuum pump, control the flow of a first gas entering the chamber through the at least one gas flow inlet, control the flow of a second gas entering the chamber through the at least one gas flow inlet, control the exhaust gas flow from the chamber through the gas flow exhaust device, control the temperature within the chamber, and control the pressure within the chamber. In one embodiment, the semiconductor substrate support includes a heating element. In one embodiment, the controller is programmed to control the flow of the first and second gases entering the chamber such that the concentration of the first gas in the chamber is greater than the concentration of the second gas in the chamber. In one embodiment, the controller is further programmed to control the flow of a third gas entering the chamber through the at least one gas flow inlet, wherein the third gas is different from the first and second gases. In one embodiment, the semiconductor device manufacturing apparatus includes a pressure sensor disposed in the chamber, wherein the pressure sensor communicates with the controller. In one embodiment, the semiconductor device manufacturing apparatus includes a temperature sensor disposed in the chamber, wherein the temperature sensor communicates with the controller. In one embodiment, the semiconductor device manufacturing apparatus includes an oxygen sensor disposed in the chamber, wherein the oxygen sensor communicates with the controller. In one embodiment, the semiconductor device manufacturing apparatus includes a water sensor, wherein the water sensor communicates with the controller.

[0097] Another embodiment of this disclosure is a semiconductor device manufacturing apparatus, comprising: a vacuum chamber, a vacuum pump connected to the vacuum chamber, a semiconductor substrate support in the vacuum chamber, a gas flow inlet in the vacuum chamber, a gas flow exhaust device in the vacuum chamber, a heater, and a controller. The controller is programmed to: control the vacuum pump, control the oxygen flow entering the vacuum chamber, control the water vapor flow entering the vacuum chamber, control the exhaust gas flow from the vacuum chamber through the gas flow exhaust device, control the temperature within the vacuum chamber, control the pressure within the vacuum chamber, and maintain an oxygen concentration higher than the water vapor concentration within the vacuum chamber. In one embodiment, the controller is further programmed to control the inflow of additional gas into the vacuum chamber. In one embodiment, the controller is programmed to maintain the molar ratio of oxygen to the total amount of oxygen and water in the chamber within a range greater than 0.2 and less than 1. In one embodiment, the controller is programmed to maintain the water concentration in the chamber within a range of 20 ppm to 2000 ppm. In one embodiment, the controller is programmed to maintain the temperature in the chamber within a range of 20°C to 400°C. In one embodiment, the controller is programmed to maintain the pressure within the chamber within a range of 1 Torr to 700 Torr. In another embodiment, the controller is programmed to change at least one of the pressure within the chamber, the temperature within the chamber, and the gas concentration within the chamber.

[0098] Another embodiment of this disclosure is a semiconductor device manufacturing apparatus, comprising: a chamber, a vacuum pump connected to the chamber, a substrate support disposed in the chamber, an airflow inlet in the wall of the chamber, an airflow exhaust device connected to the vacuum pump in the wall of the chamber, and a controller. The controller is programmed to: control the concentrations of oxygen and water vapor in the chamber such that the molar concentration of oxygen in the chamber is greater than the molar concentration of water, control the temperature in the chamber, and control the pressure in the chamber. In one embodiment, the controller is further programmed to change the pressure in the chamber while processing the substrate in the chamber. In one embodiment, the controller is programmed to change the temperature in the chamber while processing the substrate in the chamber. In one embodiment, the controller is programmed to change the concentrations of oxygen and water vapor in the chamber while processing the substrate in the chamber. In one embodiment, the semiconductor device manufacturing apparatus includes at least one of a pressure sensor, an oxygen sensor, a water sensor, and a temperature sensor.

[0099] The foregoing has outlined the features of several embodiments or examples to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0100] 10:Substrate 15: Resist layer 20: Lower layer of resist 30: Light Mask 35: Opaque Pattern 40: Photomask substrate 45: Exposure radiation 50: Exposure area 52: Unexposed area 55: Opening 55': Opening 55": Pattern 57: Developer 60: Target layer 62: Distributor 65: Reflector 70: Low thermal expansion glass substrate 75: Multi-layered reflection 80: Covering layer 85: Absorption Layer 90: Rear conductive layer 95: Extreme ultraviolet radiation 97: Part 100: Method 105: Developer 110: Baking Room 115: Substrate support platform 120a: Ingress Port 120b: Ingress Port 120c: Entry Port 125: Mixture 130: Exhaust device 135: Vacuum pump 140: Source of photoresist layer treatment 145: Source of photoresist layer treatment 150: Photoresist layer treatment source 155: Source of photoresist layer treatment 160a: Connecting cable 160b: Connecting cable 160c: Connecting cable 165: Connecting cable 170a: Oxygen sensor 170b: Water sensor 170c: Temperature sensor 170d: Pressure sensor 170e: Sensor 175: Controller 180: Semiconductor manufacturing equipment 200: Resist layer deposition equipment 205: Vacuum Chamber 210: Substrate support stage 220: First precursor or compound gas supplier 225: Carrier gas / purified gas supply unit 230: Entrance 230': Entry 235: Gas pipeline 235': Gas pipeline 240: Second precursor or compound gas supplier 245: Vacuum pump 250: Exports 255: Exhaust pipe 260: Controller 1200: Computer System 1201: Computer 1202: Keyboard 1203: Mouse 1204: Monitor 1205: CD-ROM Read-Only Memory Drive 1206: Disk Drive 1211: Microprocessor Unit 1212: Read-only memory 1213: Random Access Memory 1214: Hard Drive 1215: Busbar 1221: CD 1222: Disk S105: Operation S110: Operation S115: First Baking Operation S120: Operation S125: Operation S130: Operation S135: Operation S140: Operation S145: Operation S150: Operation

[0101] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of manufacturing a semiconductor device, comprising: depositing a photoresist composition over a target layer on a substrate to form a photoresist layer; selectively exposing the photoresist layer to photochemical radiation; applying a vacuum to the photoresist layer after selective exposure; introducing O2 and H2O into the selectively exposed photoresist layer; baking the selectively exposed photoresist layer; developing the photoresist layer after baking; and using the photoresist layer as an etch mask to etch the target layer.

2. The method as described in claim 1, wherein the photoresist composition is deposited by a spin coating operation.

3. The method as described in claim 1, wherein the photochemical radiation is extreme ultraviolet radiation.

4. The method as claimed in claim 1, wherein during the baking of the selectively exposed photoresist layer, the concentration of at least one of the O2 and H2O introduced into the selectively exposed photoresist layer is changed.

5. A method of manufacturing a semiconductor device, comprising: depositing a resist layer over a substrate; patterning and exposing the resist layer to photochemical radiation; applying a vacuum to the patterned resist layer; applying a gaseous mixture of oxygen and water to the patterned resist layer; heating the patterned resist layer; after heating the patterned resist layer, developing the resist layer using a dry developer to form a patterned resist layer; and removing a portion of the substrate exposed by the patterned resist layer.

6. The method as claimed in claim 5, wherein during the heating of the patterned resist layer, the concentration of at least one of the oxygen and the water applied to the patterned resist layer is changed.

7. The method as claimed in claim 5, wherein the application of the vacuum, the application of the gaseous mixture, and the heating of the patterned photoresist layer are performed in a single chamber.

8. A semiconductor device manufacturing apparatus comprising: a chamber; a vacuum pump connected to the chamber; a semiconductor substrate support disposed in the chamber; at least one gas flow inlet disposed in the chamber; at least one gas flow exhaust device disposed in the chamber; a heater; and a controller programmed to: control the vacuum pump; control a flow of a first gas entering the chamber via the at least one gas flow inlet; control a flow of a second gas entering the chamber via the at least one gas flow inlet; control an exhaust gas flow from the chamber via the gas flow exhaust device; control a temperature within the chamber; and control a pressure within the chamber.

9. The semiconductor device manufacturing apparatus as claimed in claim 8, wherein the semiconductor substrate support includes a heating element.

10. The semiconductor device manufacturing apparatus of claim 8, wherein the controller is programmed to control the airflow of the first gas and the second gas into the chamber such that a concentration of the first gas in the chamber is greater than a concentration of the second gas in the chamber.

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