Electronic devide, memory system and operation thereof

Abstract

In some aspects, a memory system includes a memory system coupled to host memory, comprising: a storage device including a first storage unit and a second storage unit; a memory controller coupled to the host and the storage device, the memory controller being configured to write first data to the first storage unit and / or write second data to the second storage unit, wherein the first data includes user data and the second data includes exchange data from the host memory.

Description

[Technical Field]

[0001] This disclosure relates to memory systems and the operation of memory systems. [Previous Technology]

[0002] The demand for storage capacity in host memory (e.g., dynamic random access memory, DRAM) is constantly increasing, but the cost of host memory remains high. Using a portion of external memory (e.g., solid-state drive, SSD) to compensate for the shortage of host memory is a viable solution. It is worthwhile to design external memory to accommodate additional functions. [Summary of the Invention]

[0003] In one aspect, a memory system coupled to host memory of a host includes:

[0004] A storage device, the storage device comprising a first storage unit and a second storage unit; and

[0005] A memory controller coupled to a host and a storage device, the memory controller being configured to write first data to a first storage unit and / or write second data to a second storage unit, wherein the first data includes user data and the second data includes exchange data from host memory.

[0006] In some implementations, the memory controller includes:

[0007] A cache memory, the cache memory being configured to receive first data and / or second data; and

[0008] A processor configured to, in response to a write command, write first data to a first storage unit according to a first address signal, and / or write second data to a second storage unit according to a second address signal.

[0009] In some implementations, the processor is further configured to convert the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0010] In some implementations, the processor is further configured to: count the number of loops in the second storage unit, and when the number of loops is greater than or equal to the lifetime threshold, the operation of writing the second data into the second storage unit is prohibited.

[0011] In some implementations, the processor is further configured to write the second data into the first storage unit.

[0012] In some implementations, the storage unit in the second storage unit is a single-level cell (SLC).

[0013] In some implementations, the storage cell in the first storage cell is a multi-level cell (MLC), a three-level cell (TLC), or a quad-level cell (QLC).

[0014] In another aspect, a method for operating a memory system coupled to a host memory, the method comprising: receiving first data and / or second data, wherein the first data includes user data and the second data includes exchange data from the host memory, and writing the first data to a first storage unit of a storage device and / or writing the second data to a second storage unit of a storage device.

[0015] In some implementations, the method further includes: receiving a write command, a first address signal and / or a second address signal, and responding to the write command by writing first data to a first storage unit based on the first address signal, and / or writing second data to a second storage unit based on the second address signal.

[0016] In some implementations, the method further includes: converting the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0017] In some implementations, the method further includes: counting the number of loops of the second storage unit, and prohibiting the operation of writing the second data into the second storage unit when the number of loops is greater than or equal to the lifetime threshold.

[0018] In some implementations, the method also includes: writing the second data into the first storage unit.

[0019] In another aspect, a memory system coupled to host memory of a host includes: a storage device including a first storage unit and a second storage unit, and a memory controller coupled to the host and the storage device, the memory controller being configured to read first data from the first storage unit and / or read second data from the second storage unit, wherein the first data includes user data and the second data includes exchange data from the host memory.

[0020] In some implementations, the memory controller includes a processor configured to read first data from a first memory cell according to a first address signal and / or read second data from a second memory cell according to a second address signal in response to a read command.

[0021] In some implementations, the processor is further configured to convert the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0022] In some implementations, the processor is further configured to: count the number of loops of the second storage unit, and when the number of loops is greater than or equal to the lifetime threshold, the operation of reading the second data from the second storage unit is prohibited.

[0023] In some implementations, the storage cell in the second storage cell is a single-level cell (SLC).

[0024] In some implementations, the storage cell in the first storage cell is a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC).

[0025] In another aspect, a method for operating a memory system coupled to a host memory, the method comprising: receiving a read command, and a first address signal and / or a second address signal, and reading first data from a first storage unit of a storage device and / or reading second data from a second storage unit of a storage device, wherein the first data includes user data and the second data includes exchange data from the host memory.

[0026] In some implementations, the method further includes: converting the logical address of the first address signal and / or the second address signal into a physical address based on a logical-to-physical address mapping table.

[0027] In some implementations, the method further includes: counting the number of loops of the second storage unit, and prohibiting the operation of reading second data from the second storage unit when the number of loops is greater than or equal to the lifetime threshold.

Implementation Method

[0029] Although specific configurations and arrangements have been described, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may also be adopted in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically depicted in the drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0030] Generally, terms can be understood at least in part according to their usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can also be understood to express either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood not necessarily to express an exclusive set of elements, but can allow for the presence of additional elements that are not necessarily explicitly described.

[0031] FIG1 shows a block diagram of an exemplary system 100 having storage devices according to some aspects of the present disclosure. System 100 may be a mobile phone, desktop computer, notebook computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage devices therein. As shown in FIG1, system 100 may include a host 108 having host memory 110 and host processor 112, and a memory system 102 having one or more storage devices 104 and memory controller 106.

[0032] Host 108 may be a processor (e.g., a central processing unit, CPU) or a system-on-chip (SoC) (e.g., an application processor, AP) of an electronic device. Host 108 may be coupled to memory controller 106 and configured to send data to or receive data from storage device 104 via memory controller 106. For example, host 108 may reflect program data in a programming operation or receive read data in a read operation. Host processor 112 may be a control unit (CU) or an arithmetic logic unit (ALU). Host memory 110 may be a storage unit including temporary registers or cache memory. Host 108 is configured to receive instructions and commands from and send instructions and commands to memory controller 106 of storage device 102, and to perform or implement various functions and operations provided in this disclosure, which will be described below.

[0033] Storage device 104 can be any storage device disclosed herein, such as a NAND flash memory device including a page buffer having multiple sections (e.g., four sections). Note that for illustrative purposes, NAND flash memory is merely one example of a storage device. Storage device 104 can include any suitable solid-state non-volatile memory, such as NOR flash memory, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer torque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM), etc. In some implementations, storage device 104 includes a three-dimensional (3D) NAND flash memory device.

[0034] The memory controller 106 may be implemented by the following: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in the following detailed description.

[0035] According to some implementations, the memory controller 106 is coupled to the storage device 104 and the host 108, and is configured to control the storage device 104. The memory controller 106 can manage the data stored in the storage device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low duty cycle environments such as secure digital (SD) cards, compact flash memory (CF) cards, universal serial bus (USB) flash memory drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 106 is designed to operate SSDs in high duty cycle environments or as an embedded multi-media card (eMMC) for data storage devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the storage device 104 by providing instructions such as read instructions to the storage device 104, for example, read, erase, and programming operations. For example, the memory controller 106 can be configured to provide read instructions to peripheral circuitry of the storage device 104 to control read operations. The memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to handle error correction codes (ECCs) regarding data read from or written to the storage device 104. The memory controller 106 can also perform any other suitable function, such as formatting the storage device 104.

[0036] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device through at least one of various interface protocols, such as the USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0037] The storage controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In an example shown in FIG2A, the memory controller 106 and a single storage device 104 can be integrated into a memory card 202. The memory card 202 may include PC cards (personal computer memory card international association, PCMCIA), CF cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC, secure digital high capacity), UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card to a host (e.g., host 108 in FIG1). In another example shown in Figure 2B, the memory controller 106 and multiple storage devices 104 may be integrated into the SSD 206. The SSD 206 may also include an SSD connector 208 that couples the SSD 206 to a host (e.g., host 108 in Figure 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0038] The memory control 106 is configured to receive commands from and send commands to the host 108, and to perform or implement a number of functions and operations provided in this disclosure, which will be described below.

[0039] FIG3 shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1. ​​Note that, for illustrative purposes, the NAND flash memory disclosed herein is merely one example of a memory device. Memory device 300 may include any suitable solid-state, non-volatile memory, such as NOR flash memory, FeRAM, PCM, MRAM, STT-RAM, or RRAM, etc. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can store a continuous analog value (e.g., voltage or charge) depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0040] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to represent a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of the three possible nominal storage values ​​to the cell to represent one of the three possible programming levels from the erase state. The fourth nominal stored value can be used to erase the state.

[0041] As shown in Figure 3, each NAND memory string 308 may include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and programming operations. In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some implementations, the drain of the DSG transistor 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the DSG transistor 312) or a deselection voltage (e.g., 0 V) ​​to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313, and / or by applying a selection voltage (e.g., higher than the threshold voltage of the SSG transistor 310) or a deselection voltage (e.g., 0 V) ​​to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0042] As shown in Figure 3, the NAND storage string 308 can be organized into multiple blocks 304, each block of which can have a common source line 314, for example, coupled to the ACS. In some implementations, each block 304 is the basic data unit used for erase operations (i.e., all memory cells 306 on the same block 304 are erased simultaneously). To erase memory cells 306 in a selected block 304, the source line 314 can be biased using an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)), which is coupled to the selected block 304 and unselected blocks 304 in the same plane as the selected block 304. Memory cells 306 of adjacent NAND storage strings 308 can be coupled via word lines (WL) 318, which selects which row of memory cells 306 is affected by read and programming operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, which is a basic data unit for programming and read operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled through word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding page 320. Peripheral circuitry 302 can be coupled to memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry used to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0043] FIG4 shows a block diagram of an exemplary memory system 102 including a memory controller 106 and a storage device 104 according to some aspects of the present disclosure. As shown in FIG4, the memory controller 106 may include a controller processor 408, such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor 408 is configured to control the module to execute commands or instructions to perform the functions disclosed in the present disclosure. The controller processor 408 may also be configured to control the operation of each peripheral circuit by generating and sending various control signals (e.g., read commands for read operations). The controller processor 408 may also send clock signals to other peripheral circuits 302 at a desired frequency, period, and duty cycle to coordinate the operation of each peripheral circuit 302, for example, for synchronization. The memory controller 106 may also include a volatile controller memory 411 and a non-volatile controller memory 413. Volatile controller memory 411 may include temporary registers or cache memory, allowing for faster access and processing speeds to read, write, or erase data stored therein, while potentially not retaining stored information after power is removed. In some implementations, volatile controller memory 411 includes dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile controller memory 413 may retain stored information even after power is removed. In some implementations, non-volatile controller memory 413 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. Storage device 104 may include a memory cell array, such as memory cell array 301 in FIG3. In some implementations, the non-volatile controller memory 413 may not be located within the memory controller 106. For example, the non-volatile controller memory 413 may be located external to the memory controller 106 but coupled to it. In some implementations, the controller memory (e.g., 411 or 413) is configured to store an L2P (logical-to-physical) address mapping table corresponding to files.

[0044] Figure 5 shows a block diagram of an exemplary host 108 according to some aspects of the present disclosure, the host 108 including host memory 110 and host processor 112. Host memory 110 may be volatile memory, such as random access memory (RAM), for example, DRAM, SRAM. Host memory 110 may also be non-volatile memory, such as NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. Host memory 110 includes main RAM 502 and ZRAM (zero capacitance random access memory) 504. In some implementations, main RAM 502 and ZRAM 504 may be different logical regions of host memory 110. In other words, the memory cells of main RAM 502 and ZRAM 504 can be distinguished by the logical address of the memory cells. In some implementations, main RAM 502 and ZRAM 504 may be separate memories. For example, main RAM 502 can belong to the first host memory 110, and ZRAM 504 can belong to the second host memory 110, which is independent of the first host memory 110. Furthermore, the first host memory 110 and the second host memory 110 can be the same or different types of memory. In some implementations, the host processor 112 can be a control unit (CU) or an arithmetic logic unit (ALU).

[0045] In some implementations, data from main RAM 502 can be transferred to ZRAM 504, and the transferred data can be software. Furthermore, the data transfer operation can be triggered at any time, either when main RAM 502 is full or as required by the host processor 112. In some implementations, the data transfer operation can be controlled by the host processor 112. In some implementations, the data transferred to ZRAM 504 can be compressed data. The data compression operation can be performed at any time, for example, before data is sent from main RAM 502, or during the transfer process (after data is sent from main RAM 502 and before data is received by ZRAM 504), or after data is received by ZRAM 504. The compression operation can be controlled by the host processor 112. In some implementations, the operation may involve the host processor 112 controlling the main RAM 502 to transfer data from the main RAM 502 to the ZRAM 504 when the main RAM 502 is full, and the transferred data is compressed before being received by the ZRAM 504. In some implementations, the data transferred from the main RAM 502 may be data with a lower access frequency compared to the data retained in the main RAM 502. In this case, inactive data can be compressed, and the storage capacity of the host memory 110 can be preserved. For example, in a smartphone implementation, assuming five applications are running and their programs are stored in the main RAM 502, if two of the five applications are inactive, their programs can be compressed and stored in the ZRAM 504. This frees up a portion of the main RAM 502's storage capacity, allowing more programs to be stored in the host memory 110, meaning more applications can run simultaneously. In this scenario, the two inactive applications still run in the background, and when these two inactive applications are invoked, their programs can be decompressed.

[0046] Data in host memory 110 can also be transferred to storage device 104, and data can be transferred from ZRAM 504 or main RAM 502. Furthermore, data transfer operations can be triggered at any time when main RAM 502 is full or when the main processor 112 depends on it. In some implementations, the data transfer operation can be controlled by the host processor 112. In some implementations, ZRAM 504 transfers swap data to a memory system (e.g., SSD, UFS, eMMC), and the swap data can be compressed software. The memory system can store the swap data, and the memory system can also send the swap data back to host memory 110 (e.g., ZRAM 504), making the memory system a supplement to host memory 110. In some implementations, after ZRAM 504 transfers swap data to the memory system, the swap data in ZRAM 504 can be deleted to free up storage capacity in ZRAM 504. In some implementations, when the storage capacity of ZRAM 504 is limited, data exchanged with inactive software or applications can be transferred from ZRAM 504 to the memory system; conversely, when inactive software or applications are invoked, the corresponding data exchanged can be transferred from the memory system to ZRAM 504. This allows more software or applications to run simultaneously.

[0047] The host processor 112 can send commands to the memory system to instruct the memory system to input or output exchange data. Furthermore, the memory system may include a memory controller 106 and a storage device 104, which may be a NAND flash memory. The commands and exchange data can be sent to the memory controller 106, and the memory controller 106 can write the exchange data to the storage device 104 according to the commands. In some implementations, the host processor 112 can also send address signals to the memory controller, wherein the address signals include logical addresses, and the controller can translate the logical addresses to physical addresses based on an L2P address mapping table. The L2P address mapping table can be stored in the DRAM, NAND flash memory, or host memory 110 of the memory system. The physical address points to a storage cell of the storage device 104, enabling the memory controller 106 to write exchange data to the target storage cell and read exchange data from the target storage cell. In some implementations, when the storage capacity of ZRAM 504 is limited, data exchanged with inactive software or applications can be transferred from ZRAM 504 to storage device 104; when inactive software or applications are invoked, the corresponding data exchanged can be transferred from storage device 104 to ZRAM 504. In this case, more software or applications can run at the same time.

[0048] Figure 6 shows a block diagram of an exemplary storage device 104 including a storage cell array 301 according to some aspects of the present disclosure. The storage cell array 301 can be divided into multiple logical units according to the logical addresses of the storage cells, such as a large LUN (logic unit number) 606, a switched LUN 608, a BOOT A 602, and a BOOT B 604. In some implementations, the host 108 can access the large LUN 606, the switched LUN 608, the BOOT A 602, or the BOOT B 604 by sending commands and storage cell address signals. Furthermore, the address signals include the logical addresses of the storage cells, and the storage controller 106 translates the logical addresses into physical addresses according to an L2P mapping table.

[0049] In some implementations, large LUN 606, BOOT A 602, and BOOT B 604 can store user data, and exchange LUN 608 can store exchange data. User data can be data received by host 108 or data generated within host 108. For example, in a smartphone with UFS (Ultra-Flash Storage), user data can be data input by the computer user or data generated during operation of host 108. In some implementations, BOOT A 602 and BOOT B 604 can also store system data, where system data can be operating system programs. For example, in a smartphone with UFS (Ultra-Flash Storage), the system data stored in BOOT A 602 or BOOT B 604 on an SSD can be Windows system programs. The memory controller 106 can write user data to the storage units corresponding to the large LUN 606, BOOT A 602, and BOOT B 604, and can also read user data from the storage units corresponding to these storage units. The memory controller 106 can write swap data to the storage unit corresponding to the swap LUN 608, and can also read swap data from the storage unit corresponding to the swap LUN 608. In other words, the storage units for storing swap data are separate from the storage units for storing user data. Because swap data is accessed more frequently than user data, the storage unit corresponding to the swap LUN 608 is worn out earlier than the storage units corresponding to the large LUN 606, BOOT A 602, or BOOT B 604. Because the swapped LUN 608 is separate from the large LUN 606, BOOT A 602, or BOOT B 604, the large LUN 606, BOOT A 602, and BOOT B 604 are not affected by frequent access to the swapped LUN 608. If the memory corresponding to the swapped LUN 608 is exhausted, the memory corresponding to the large LUN 606, BOOT A 602, and BOOT B 604 remains programmable and readable.

[0050] FIG7 shows a block diagram of an exemplary memory system including a memory controller 106 and a storage device 104 according to some aspects of the present disclosure. In some implementations, the storage device 104 may include a first storage unit 704 and a second storage unit 706. The first storage unit 704 is configured to store first data, wherein the first data is user data. The second storage unit 706 is configured to store second data, wherein the second data is exchange data from the host memory 110. Furthermore, the memory controller 106 is coupled between the host 108 and the storage device 104, and the memory controller 106 is configured to write the first data to the first storage unit 704 and / or write the second data to the second storage unit 706. In some implementations, the first storage unit 704 may be a storage unit corresponding to a large LUN 606, BOOT A 602, and BOOT B 604, and the second storage unit 706 may be a storage unit corresponding to a swap LUN 608. Because exchanged data is accessed more frequently than user data, the second storage unit 706 is exhausted earlier than the first storage unit 704. Since the second storage unit 706 is separate from the first storage unit 704, the first storage unit 704 is unaffected by the frequent access to the second storage unit 706. Even if the second storage unit 706 is exhausted, it remains programmable and readable.

[0051] In some implementations, the second storage unit 706 can be a single-level cell (SLC). Since each storage unit stores one bit of data, SLC can have better performance than multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), for example, less programming time, less read time, and more programming / erase loops. Because the swapped LUN 608 is accessed more frequently than the large LUN 606, BOOT A 602, and BOOT B 604, the second storage unit 706 requires better performance than the first storage unit 704. And SLC can meet the performance requirements of the second storage unit 706.

[0052] In some implementations, the first storage unit 704 can be an MLC, TLC, or QLC. Since each storage unit stores 2 / 3 / 4 bits of data, MLC, TLC, and QLC can have a larger storage capacity than SLC. Because the large LUN 606, BOOT A 602, and BOOT B 604 are accessed less frequently than the swapped LUN 608 and require a larger storage capacity, the first storage unit 704 requires a lower cost than the second storage unit 704. Furthermore, MLC, TLC, and QLC can meet the low-cost requirement of the first storage unit 704.

[0053] In some implementations, the memory controller 106 includes a cache memory 702 and a controller processor 408. The cache memory 702 may be SRAM, DRAM, NAND flash memory, NOR flash memory, or any other type of storage device or electrical device. The controller processor 408 may be a control unit (CU) or an arithmetic logic unit (ALU). For write operations, based on a write command, the cache memory 702 is configured to receive first data and / or second data, and the controller processor 408 is configured to write the first data to a first storage cell 704 according to a first address signal, and / or write the second data to a second storage cell 706 according to a second address signal. In some implementations, the first address signal may include a first logical address pointing to large LUN 606, BOOT A 602, and BOOT B 604. The controller processor 408 may translate the first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to the first storage cell 704. Therefore, the memory controller 106 writes user data to the first storage unit 704 according to the first address signal. In some implementations, the second address signal may include a second logical address pointing to the swap LUN 608. The controller processor 408 may translate the second logical address into a second physical address based on an L2P address mapping table, and the second physical address corresponds to the second storage unit 706. Therefore, the memory controller 106 writes swap data to the second storage unit 706 according to the second address signal. For read operations, based on a read command, the cache memory 702 is configured to receive first data and / or second data, and the controller processor 408 is configured to read the first data from the first storage unit 704 according to the second address signal, and / or read the second data from the second storage unit 706 according to the second address signal. In some implementations, the second address signal may include a first logical address pointing to the large LUN 606, BOOT A 602, and BOOT B 604. The controller processor 408 can translate a first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to the first memory cell 704. Therefore, the memory controller 106 reads user data from the first memory cell 704 according to a second address signal. In some implementations, the second address signal may include a second logical address pointing to a switching LUN 608. The controller processor 408 can translate the second logical address into a second physical address based on an L2P address mapping table, and the second physical address corresponds to the second memory cell 706. Therefore, the memory controller 106 reads switched data from the second memory cell 706 according to the second address signal.

[0054] In some implementations, for write operations, the memory processor can count the number of loops in the second storage unit 706 and compare the number of loops with a lifetime threshold. When the number of writes reaches the lifetime threshold, the processor can prevent the writing of second data to the second storage unit 706. The number of loops can be program / erase counts. The swap LUN 608 is accessed more frequently than the large LUN 606, BOOT A 602, and BOOT B 604, which may cause the second storage unit 706 to be exhausted earlier than the first storage unit 704. Counting the number of loops in the SLC can monitor the remaining lifetime of the second storage unit 706. When the second storage unit 706 is exhausted, it will be disabled in the event of lost swap data. In some implementations, after the second storage unit 706 is disabled, the host 108 will not send swap data to the memory system. In other implementations, after the second storage unit 706 is disabled, the host 108 will still transmit swap data to the memory system, and the memory controller 106 will write the swap data to the first storage unit 704 according to commands provided by the host 108. In some implementations, for read operations, the memory processor can count the number of loops in the second storage unit 706 and compare the number of loops with a lifetime threshold. When the number of reads reaches the lifetime threshold, the processor can prevent reading second data from the second storage unit 706. The number of loops can be program / erase counts. Swapped LUN 608 is accessed more frequently than large LUN 606, BOOT A 602, and BOOT B 604, which may cause the second storage unit 706 to be exhausted earlier than the first storage unit 704. Counting the number of loops in the SLC can monitor the remaining lifetime of the second storage unit 706. When the second storage unit 706 is exhausted, it will be disabled in the event of swap data loss. In some implementations, after the second storage unit 706 is disabled, the host 108 will not transfer exchange data to the memory system. In other implementations, after the second storage unit 706 is disabled, the host 108 will still transfer exchange data to the memory system, and the memory controller 106 will read exchange data from the first storage unit 704 according to commands provided by the host 108.

[0055] Figure 8 shows a flowchart of an exemplary method for operating a memory system according to some aspects of this disclosure. The memory system can be any suitable memory system disclosed herein, such as memory system 102 in Figures 4 and 7. Method 800 can be implemented partially or completely by memory system 102 as shown in Figures 4 and 7. It is understood that the operations shown in the method may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously or in a different order than that shown in Figure 8.

[0056] Referring to FIG8, method 800 begins at operation 802, wherein a memory system (e.g., memory system 102 in FIG4 and FIG7) receives first data and / or second data from a host (e.g., host 108 in FIG1 and FIG5). In some implementations, the first data is user data and the second data is exchange data from host memory.

[0057] In some implementations, the memory system may include a memory controller and a storage device, which may be a NAND flash memory. The storage device may include a first storage cell and a second storage cell.

[0058] In operation 804, as shown in FIG8, first data is written to the first storage cell of the storage device and / or second data is written to the second storage cell of the storage device.

[0059] In some implementations, the memory controller is coupled between the host and the storage device, and the memory controller is configured to write first data to a first storage unit and / or write second data to a second storage unit. In some implementations, the first storage unit may be a storage unit corresponding to a large LUN, BOOT A, and BOOT B, and the second storage unit may be a storage unit corresponding to a swapped LUN.

[0060] In some implementations, commands and exchange data can be sent to a memory controller, which can write the exchange data to a storage device according to a write command. In some implementations, the host processor can also send address signals to the memory controller, where the address signals may include logical addresses, and the controller can translate the logical addresses into physical addresses based on an L2P address mapping table. The L2P address mapping table can be stored in the DRAM, NAND flash memory, or host memory of the memory system. The physical address points to a storage cell in the storage device, enabling the memory controller to write the exchange data to the target storage cell and read the exchange data from the target storage cell. In some implementations, when the ZRAM storage capacity is limited, exchange data corresponding to inactive software or applications can be transferred from the ZRAM to the storage device; when inactive software or applications are invoked, the corresponding exchange data can be transferred from the storage device to the ZRAM. In this case, more software or applications can run simultaneously.

[0061] In some implementations, the memory controller includes a cache memory and a controller processor. The cache memory may be SRAM, DRAM, NAND flash memory, NOR flash memory, or any other type of storage device or electrical device. The controller processor may be a control unit (CU) or an arithmetic logic unit (ALU). The cache memory is configured to receive first data and / or second data, and the controller processor is configured to write the first data to a first storage cell according to a first address signal, and / or write the second data to a second storage cell according to an address signal. In some implementations, the address signal may include a first logical address pointing to a large LUN, BOOT A, and BOOT B. The controller processor may translate the first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to the first storage cell. Therefore, the memory controller writes user data to the first storage cell according to the address signal. In some implementations, the address signal may include a second logical address pointing to a swapped LUN. The controller processor can translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell. Therefore, the memory controller writes the exchanged data into the second memory cell according to the address signal.

[0062] In some implementations, the memory processor can count the number of loops in the second storage unit and compare the number of loops with a lifetime threshold. When the number of writes reaches the lifetime threshold, the processor can prevent the writing of second data to the second storage unit. The number of loops can be program / erase counts. Swapped LUNs are accessed more frequently than large LUNs, BOOT A, and BOOT B, which may cause the second storage unit to be exhausted earlier than the first storage unit. Counting the number of loops in the SLC can monitor the remaining lifetime of the second storage unit. When the second storage unit is exhausted, it will be disabled in the event of lost swap data. In some implementations, after the second storage unit is disabled, the host will not send swap data to the memory system. In other implementations, after the second storage unit is disabled, the host will still send swap data to the memory system, and the memory controller will write the swap data to the first storage unit according to commands provided by the host.

[0063] Figure 9 shows a flowchart of an exemplary method for operating a memory system according to some aspects of this disclosure. The memory system can be any suitable memory system disclosed herein, such as memory system 102 in Figures 4 and 7. Method 900 can be implemented partially or completely by memory system 102 as shown in Figures 4 and 7. It is understood that the operations shown in the method may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously or in a different order than that shown in Figure 9.

[0064] Referring to FIG9, method 900 begins at operation 902, wherein the memory system (e.g., memory system 102 in FIG4 and FIG7) receives a read command, a first address signal and / or a second address signal from the host (e.g., host 108 in FIG1 and FIG5).

[0065] In some implementations, the memory system may include a memory controller and a storage device, wherein the storage device may be a NAND flash memory. The storage device may include a first storage cell and a second storage cell.

[0066] In operation 904, as shown in FIG9, first data is read from a first storage cell of the storage device and / or second data is read from a second storage cell of the storage device, wherein the first data is user data and the second data is exchange data from the host memory.

[0067] In some implementations, a memory controller is coupled between the host and the storage device, and the memory controller is configured to read first data from a first storage unit and / or read second data from a second storage unit. In some implementations, the first storage unit may be a storage unit corresponding to a large LUN, BOOT A, and BOOT B, and the second storage unit may be a storage unit corresponding to a swapped LUN.

[0068] In some implementations, commands and exchange data can be sent to a memory controller, which can read the exchange data from a storage device according to a read command. In some implementations, the host processor can also send address signals to the memory controller, where the address signals may include logical addresses, and the controller can translate the logical addresses into physical addresses based on an L2P address mapping table. The L2P address mapping table can be stored in the DRAM, NAND flash memory, or host memory of the memory system. The physical address points to a storage cell of the storage device, enabling the memory controller to read the exchange data from the target storage cell. In some implementations, when the ZRAM storage capacity is limited, exchange data corresponding to inactive software or applications can be transferred from the ZRAM to the storage device; when inactive software or applications are invoked, the corresponding exchange data can be transferred from the storage device to the ZRAM. In this case, more software or applications can run simultaneously.

[0069] In some implementations, the memory controller includes a cache memory and a controller processor. The cache memory may be SRAM, DRAM, NAND flash memory, NOR flash memory, or any other type of storage device or electrical device. The controller processor may be a control unit (CU) or an arithmetic logic unit (ALU). The cache memory is configured to receive first data and / or second data, and the controller processor is configured to read the first data from a first storage cell based on a first address signal, and / or read the second data from a second storage cell based on an address signal. In some implementations, the address signal may include a first logical address pointing to a large LUN, BOOT A, and BOOT B. The controller processor may translate the first logical address into a first physical address based on an L2P address mapping table, and the first physical address corresponds to a first storage cell. Therefore, the memory controller reads user data from the first storage cell based on the address signal. In some implementations, the address signal may include a second logical address pointing to a swapped LUN. The controller processor can translate the second logical address into a second physical address based on the L2P address mapping table, and the second physical address corresponds to the second memory cell. Therefore, the memory controller reads and exchanges data from the second memory cell according to the address signal.

[0070] In some implementations, the memory processor can count the number of loops in the second storage unit and compare the number of loops with a lifetime threshold. When the number of reads reaches the lifetime threshold, the processor can prevent the reading of second data from the second storage unit. The number of loops can be program / erase counts. Swapped LUNs are accessed more frequently than large LUNs, BOOT A, and BOOT B, which may cause the second storage unit to be exhausted earlier than the first storage unit. Counting the number of loops in the SLC can monitor the remaining lifetime of the second storage unit. When the second storage unit is exhausted, it will be disabled in the event of lost swap data. In some implementations, after the second storage unit is disabled, the host will not send swap data to the memory system. In other implementations, after the second storage unit is disabled, the host will still send swap data to the memory system, and the memory controller will read swap data from the first storage unit according to the commands provided by the host.

[0071] The foregoing description of the specific implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementation.

[0072] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents. [Simplified Explanation of the Diagram]

[0028] The drawings incorporated herein by reference and forming part of the specification illustrate aspects of the present disclosure and, together with the specification, further serve to explain the present disclosure and enable those skilled in the art to make and use the present disclosure. Figure 1 shows a block diagram of an exemplary system having a host and memory system according to some aspects of the present disclosure. Figure 2A shows a diagram of an exemplary memory card having a storage device according to some aspects of the present disclosure. Figure 2B shows a diagram of an exemplary solid-state drive (SSD) having a storage device according to some aspects of the present disclosure. Figure 3 shows a schematic diagram of an exemplary storage device including peripheral circuitry according to some aspects of the present disclosure. Figure 4 shows a block diagram of an exemplary memory system including a memory controller and a storage device according to some aspects of the present disclosure. Figure 5 shows a block diagram of an exemplary host including host memory and a host processor according to some aspects of the present disclosure. Figure 6 shows a block diagram of an exemplary storage device including a memory cell array according to some aspects of the present disclosure. Figure 7 shows a block diagram of an exemplary memory system including a memory controller and a storage device according to some aspects of the present disclosure. Figure 8 shows a flowchart of an exemplary method for operating a memory system according to some aspects of the present disclosure. Figure 9 illustrates a flowchart of an exemplary method for operating a memory system according to some aspects of this disclosure. Aspects of this disclosure will be described with reference to the figures.

Claims

1. A memory system coupled to a host computer, comprising: A storage device, the storage device comprising a first storage unit and a second storage unit; The system also includes a memory controller coupled to the host and the storage device, the memory controller being configured to: write the first data to the first storage unit in response to a first write command instructing the writing of the first data, wherein the first data includes user data; write the second data to the second storage unit in response to a second write command instructing the writing of the second data, wherein the second data includes exchange data from the host; read the second data from the second storage unit and send it to the host in response to a first read command instructing the reading of the second data; and disable the second storage unit in response to a loop count of the second storage unit being greater than or equal to a threshold.

2. The memory system as described in claim 1, wherein, The storage cell array of the storage device is divided into multiple logical cells, the first storage cell corresponds to a first logical cell, and the second storage cell corresponds to a second logical cell; the memory controller is configured to: receive a first write command, a first address signal, and the first data, wherein the first address signal includes a first logical address pointing to the first logical cell; in response to the first write command, write the first data to the first storage cell according to the first address signal; receive a second write command, a second address signal, and the second data, wherein the second address signal includes a second logical address pointing to the second logical cell; and in response to the second write command, write the second data to the second storage cell according to the second address signal.

3. The memory system as described in claim 1, wherein, The exchanged data includes compressed data, which includes inactive software or application programs.

4. The memory system as described in claim 1, wherein, The number of loops includes the number of programmable / erase cycles; the threshold includes a lifetime threshold, which indicates that the second memory cell is exhausted when the number of loops is greater than or equal to the lifetime threshold.

5. The memory system as described in claim 1, wherein, The memory controller is further configured to: write the second data to the first storage unit in response to a third write command instructing the writing of the second data after the second storage unit is disabled.

6. The memory system as described in claim 5, wherein, The memory controller is further configured to: read the second data from the first storage unit in response to a second read command instructing the reading of the second data after the second storage unit is disabled.

7. The memory system as described in claim 1, wherein, The memory controller is configured to: prohibit reading the second data from the second storage unit in response to the second storage unit having a loop count greater than or equal to the threshold.

8. The memory system as described in claim 1, wherein, The memory controller is also configured to: in response to the second storage unit being disabled, cease receiving the second data sent by the host to the memory system.

9. The memory system as described in claim 1, wherein, The first storage unit is configured to write data with N bits, where N is greater than or equal to 2; the second storage unit is configured to write data with M bits, where M is greater than or equal to 1, and N is greater than M.

10. The memory system as described in claim 9, wherein, The storage cells in the second storage unit are single-level cells (SLC).

11. The memory system as described in claim 10, wherein, The storage cells in the first storage unit are multi-level cells (MLC), three-level cells (TLC), or four-level cells (QLC).

12. A method of operating a memory system, the memory system being coupled to a host computer and including a storage device, the storage device including a first storage unit and a second storage unit, the method comprising: In response to a first write command instructing the writing of first data, the first data is written to the first storage unit, wherein the first data includes user data; in response to a second write command instructing the writing of second data, the second data is written to the second storage unit, wherein the second data includes exchange data from the host; in response to a first read command instructing the reading of the second data, the second data is read from the second storage unit and sent to the host; and in response to the second storage unit having a loop count greater than or equal to a threshold, the second storage unit is disabled.

13. The method as described in claim 12, wherein, The storage unit array of the storage device is divided into multiple logical units, the first storage unit corresponds to the first logical unit, and the second storage unit corresponds to the second logical unit. In response to a first write command instructing the writing of the first data, writing the first data into the first storage unit includes: receiving the first write command, a first address signal, and the first data, wherein the first address signal includes a first logical address pointing to the first logical unit; and in response to the first write command, writing the first data into the first storage unit according to the first address signal; In response to a second write command instructing the writing of the second data, writing the second data into the second storage unit includes: receiving the second write command, a second address signal, and the second data, wherein the second address signal includes a second logical address pointing to the second logical unit; and in response to the second write command, writing the second data into the second storage unit according to the second address signal.

14. The method as described in claim 12, wherein, The exchanged data includes compressed data, which includes inactive software or application programs.

15. The method as described in claim 12, wherein, The number of loops includes the number of programmable / erase cycles; the threshold includes a lifetime threshold, which indicates that the second memory cell is exhausted when the number of loops is greater than or equal to the lifetime threshold.

16. The method as described in claim 12, further comprising: After the second storage unit is disabled, in response to a third write command instructing the writing of the second data, the second data is written to the first storage unit.

17. The method as described in claim 16, further comprising: When the second storage unit is disabled, the second data is read from the first storage unit in response to a second read command instructing the reading of the second data.

18. The method as described in claim 12, further comprising: In response to the second storage unit having a loop count greater than or equal to the threshold, reading the second data from the second storage unit is prohibited.

19. The method as described in claim 12, further comprising: In response to the second storage unit being disabled, the second data sent by the host to the memory system is no longer received.

20. The method as described in claim 12, wherein, The storage cells in the second storage unit are single-level cells (SLC); and the storage cells in the first storage unit are multi-level cells (MLC), three-level cells (TLC), or four-level cells (QLC).

21. An electronic device comprising: A host computer and a memory system, including a storage device and a memory controller, the storage device including a first storage cell and a second storage cell; the memory controller coupled to the host computer and the storage device; the memory controller configured to: write the first data to the first storage cell in response to the first write command from the host computer indicating the writing of the first data, wherein the first data includes user data; write the second data to the second storage cell in response to the second write command from the host computer indicating the writing of the second data, wherein the second data includes exchange data from the host computer; read the second data from the second storage cell and send it to the host computer in response to the first read command from the host computer indicating the reading of the second data; and disable the second storage cell in response to a loop count of the second storage cell being greater than or equal to a threshold.

22. The electronic device as claimed in claim 21, wherein, The storage cell array of the storage device is divided into multiple logical cells, the first storage cell corresponding to a first logical cell, and the second storage cell corresponding to a second logical cell; the memory controller is configured to: receive a first write command, a first address signal, and first data from the host, the first address signal including a first logical address pointing to the first logical cell; in response to the first write command from the host, write the first data to the first storage cell according to the first address signal; receive a second write command, a second address signal, and second data from the host, the second address signal including a second logical address pointing to the second logical cell; and in response to the second write command from the host, write the second data to the second storage cell according to the second address signal.

23. The electronic device as claimed in claim 21, wherein, The host includes host memory, which includes main RAM (Random Access Memory) and ZRAM (Zero Capacitance Random Access Memory), wherein the ZRAM is configured to store the exchange data, which includes compressed data, including programs of inactive software or applications.

24. The electronic device as claimed in claim 23, wherein, The host also includes a host processor configured to: in response to a shortage of storage capacity in the ZRAM, transfer exchange data corresponding to the inactive software or application from the ZRAM to the memory controller, and instruct the memory controller to write the exchange data corresponding to the inactive software or application into the second storage unit.

25. The electronic device as claimed in claim 24, wherein, The host processor is further configured to: invoke the inactive software or application; and send a second read command to the memory controller, instructing the memory controller to read the exchange data corresponding to the inactive software or application from the second storage unit, and to transfer the exchange data corresponding to the inactive software or application to the ZRAM.

26. The electronic device as claimed in claim 21, wherein, The host processor is also configured to: after the second storage unit is disabled, stop sending the second data to the memory controller.

27. The system as described in claim 21, wherein, The host processor is further configured to: after the second storage unit is disabled, send a third write command to the memory controller, instructing the memory controller to write the second data into the first storage unit.

28. The electronic device as claimed in claim 27, wherein, The host processor is further configured to: after the second storage unit is disabled, send a second read command to the memory controller, instructing the memory controller to read the second data from the first storage unit.

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