Semiconductor device

Abstract

The semiconductor device includes a substrate, an inner ultra-high voltage (UHV) element, an outer UHV element, a first isolation region, and a resistive element. The inner UHV element is disposed in a first region of the substrate, and the outer UHV element is disposed in a second region of the substrate, with the outer UHV element surrounding the inner UHV element. The first isolation region is disposed in the first region of the substrate, and the resistive element is disposed directly above the first isolation region. Furthermore, the inner and outer UHV elements are connected in series, and the resistive element is electrically coupled to both the outer and inner UHV elements.

Claims

1. A semiconductor device, comprising: One base; An inner ultra-high voltage element is disposed in a first region of the substrate, and the inner ultra-high voltage element includes: a first high-pressure well region disposed within the substrate; The substrate includes a first drain region located within the first high-pressure well region; an outer ultra-high-pressure element located in a second region of the substrate, surrounding the inner ultra-high-pressure element; a first isolation region located in the first region of the substrate; and a resistor element located directly above the first isolation region, wherein the inner ultra-high-pressure element and the outer ultra-high-pressure element are connected in series, and the resistor element is electrically coupled to both the outer ultra-high-pressure element and the inner ultra-high-pressure element.

2. The semiconductor device as claimed in claim 1, wherein the resistive element is disposed on the inner ultra-high voltage element.

3. The semiconductor device as claimed in claim 1, wherein the substrate has a first conductivity type, the first high-voltage well region has a second conductivity type, and the inner ultra-high voltage element further includes: a first well region having the first conductivity type and disposed within the first high-voltage well region; a first source region disposed within the first well region; and a first gate electrode disposed on the first well region.

4. The semiconductor device as claimed in claim 3, wherein the first isolation region includes a field oxide or shallow trench isolation region disposed in the first high-pressure well region, located between the first source region and the first drain region, and a portion of the first gate electrode extends laterally onto the first isolation region.

5. The semiconductor device as claimed in claim 3, wherein the distance between the first gate electrode and the first drain region is greater than the distance between the first gate electrode and the first source region.

6. The semiconductor device as claimed in claim 3, wherein the external ultra-high voltage element comprises: A second high-pressure well region, having the second conductivity type, is disposed within the substrate, surrounding the first high-pressure well region, and laterally separated from the first high-pressure well region; a second well region, having the second conductivity type, is disposed within the substrate and laterally separated from the second high-pressure well region; a second source region is disposed within the second well region; a second drain region is disposed within the second high-pressure well region; and a second gate electrode is disposed on the substrate, located between the second high-pressure well region and the second well region.

7. The semiconductor device as claimed in claim 6, wherein the bottom surface of the first high-pressure well region and the bottom surface of the second high-pressure well region are at the same horizontal level.

8. The semiconductor device as claimed in claim 6, wherein both the first high-pressure well region and the second high-pressure well region include a deep high-pressure well region and a high-pressure well region disposed on the deep high-pressure well region.

9. The semiconductor device as claimed in claim 6, wherein the bottom surface of the second high-pressure well region is lower than the bottom surface of the second well region.

10. The semiconductor device as claimed in claim 6, wherein the distance between the second gate electrode and the second drain region is greater than the distance between the second gate electrode and the second source region.

11. The semiconductor device as claimed in claim 6 further includes a second isolation region disposed between the first high-voltage well region and the second high-voltage well region, and the second isolation region includes a field oxide or shallow trench isolation region.

12. The semiconductor device as claimed in claim 6 further includes a third isolation region disposed in the second high-pressure well region, located between the second gate electrode and the second drain region, and the third isolation region includes a field oxide or shallow trench isolation region.

13. The semiconductor device as claimed in claim 6, wherein the first gate electrode, the second gate electrode, and the resistive element are all composed of polysilicon or metal.

14. The semiconductor device as claimed in claim 6 further includes a third well region having the first conductivity type, disposed in the substrate, wherein the bottom surface of the second well region is located in the third well region, and the bottom surfaces of the first high-pressure well region and the second high-pressure well region are both lower than the bottom surface of the third well region.

15. The semiconductor device as claimed in claim 14 further includes a base region having the first conductivity type, disposed in the third well region, and located outside the second well region.

16. The semiconductor device as claimed in claim 1, wherein a first terminal of the resistive element and a drain terminal of the inner ultra-high voltage element are electrically coupled to a high voltage, and a second terminal of the resistive element, a source terminal and a gate terminal of the inner ultra-high voltage element are electrically coupled to a low voltage.

17. The semiconductor device as claimed in claim 16, wherein the second terminal of the resistive element is electrically connected to a drain terminal of the external ultra-high voltage element.

18. The semiconductor device of claim 1, wherein, in a top view, the inner high-voltage element has a shape including a circle, an ellipse, a square, or a polygon, and the outer high-voltage element has a shape including a circular ring, an elliptical ring, a square ring, or a polygonal ring, the outer high-voltage element surrounds the inner high-voltage element, and the outer high-voltage element and the inner high-voltage element are spaced apart by a distance.

19. The semiconductor device as claimed in claim 1, wherein, in a top view, the inner ultra-high voltage element comprises a rectangle, and the outer ultra-high voltage element surrounds three sides of the rectangle.

20. The semiconductor device as claimed in claim 1, wherein the inner ultra-high voltage element comprises a metal-oxide-semiconductor transistor or a diode, and the outer ultra-high voltage element comprises a metal-oxide-semiconductor transistor.

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