Flash memory structure and method for fabricating the same

Abstract

A flash memory structure includes a semiconductor substrate, two gate stacks disposed on the semiconductor substrate, each gate stack including a floating gate and a control gate, the control gate being disposed on the floating gate, an erase gate being disposed between the two gate stacks, and two L-shaped elements disposed between the floating gate and the erase gate, each L-shaped element including a vertical portion and a horizontal portion, the vertical portion being attached to the floating gate, and the horizontal portion extending from the vertical portion toward the erase gate, the L-shaped element comprising a conductor or semiconductor material.

Claims

1. A flash memory structure, comprising: a semiconductor substrate; a first gate stack structure disposed on the semiconductor substrate, wherein the first gate stack structure includes a first floating gate and a first control gate, the first control gate being disposed on the first floating gate; and a second gate stack structure disposed on the semiconductor substrate, wherein the second gate stack structure includes a second floating gate and a second control gate, the second control gate being disposed on the second floating gate; An erase gate is disposed between the first gate stack structure and the second gate stack structure; a first L-shaped element is disposed between the first floating gate and the erase gate, wherein the first L-shaped element includes a first vertical portion and a first horizontal portion, the first vertical portion is attached to the sidewall of the first floating gate, and the first horizontal portion extends from the first vertical portion toward the erase gate, wherein the first L-shaped element and the first floating gate are not integrally formed; and a second L-shaped element is disposed between the second floating gate and the erase gate, wherein the second L-shaped element includes a second vertical portion and a second horizontal portion, the second vertical portion is attached to the sidewall of the second floating gate, and the second horizontal portion extends from the second vertical portion toward the erase gate, wherein the second L-shaped element and the second floating gate are not integrally formed; wherein the first L-shaped element and the second L-shaped element comprise conductors or semiconductors.

2. The flash memory structure as described in claim 1, wherein the conductors included in the first L-shaped element and the second L-shaped element comprise tungsten, cobalt, tantalum, titanium, aluminum, copper, titanium nitride or tantalum nitride, and the semiconductors comprise polycrystalline silicon, amorphous silicon or silicon-germanium.

3. The flash memory structure as described in claim 1, wherein the bottom of the first horizontal portion is flush with the bottom of the first floating gate, and the bottom of the second horizontal portion is flush with the bottom of the second floating gate.

4. The flash memory structure as described in claim 1, wherein the first gate stack structure further includes a first barrier dielectric layer disposed between the first floating gate and the first control gate, and the highest surface of the first vertical portion is lower than the bottom of the first barrier dielectric layer.

5. The flash memory structure as described in claim 1, wherein the second gate stack structure further includes a second barrier dielectric layer disposed between the second floating gate and the second control gate, and the highest surface of the second vertical portion is lower than the bottom of the second barrier dielectric layer.

6. The flash memory structure as described in claim 1, wherein the first L-shaped element and the second L-shaped element are mirror-symmetric with the erase gate as the central axis.

7. The flash memory structure as described in claim 1, wherein the erase gate is embedded in the semiconductor substrate.

8. The flash memory structure as described in claim 1, wherein during an erase operation, electrons flow from the first floating gate and the second floating gate through the first horizontal portion and the second horizontal portion to the erase gate, respectively.

9. A method for fabricating a flash memory structure, comprising: providing a semiconductor substrate, a first gate stack structure and a second gate stack structure disposed on the semiconductor substrate, two sacrificial layers respectively covering the first gate stack structure and the second gate stack structure, two first insulating layers respectively contacting the sidewalls of the sacrificial layers, and a first trench disposed between the first insulating layers and the first gate stack structure and the second gate stack structure, wherein the first gate structure includes a first floating gate and the second gate structure includes a second floating gate; forming a preparative material layer covering the sidewalls and bottom of the first trench, wherein the preparative material layer includes a conductor or a semiconductor; forming a photoresist covering and contacting the preparative material layer located at the bottom of the first trench; using the photoresist as a mask, removing a portion of the preparative material layer; and after removing a portion of the preparative material layer, completely removing the photoresist; After the photoresist is completely removed, a second insulating layer is formed to cover the sidewalls of the first trench and the remaining preparatory material layer, wherein the second insulating layer defines a second trench; and the bottom of the second trench and the preparatory material layer located below the bottom of the second trench are removed, so that the preparatory material layer is divided into a first L-shaped element and a second L-shaped element, wherein the first L-shaped element and the first floating gate are not integrally formed, and the second L-shaped element and the second floating gate are not integrally formed.

10. A method for manufacturing a flash memory structure as described in claim 9, wherein the first gate stack structure further includes a first control gate, a first barrier dielectric layer is disposed between the first floating gate and the first control gate, and the highest surface of the photoresist is lower than the bottom of the first barrier dielectric layer.

11. A method for fabricating a flash memory structure as described in claim 9, wherein two shallow trenches are isolated on both sides of the semiconductor substrate.

12. The method of manufacturing a flash memory structure as described in claim 11, further comprising: when forming the preparatory material layer, the preparatory material layer covers the shallow trench isolation.

13. The method of manufacturing a flash memory structure as described in claim 12, further comprising: when removing a portion of the preparatory material layer using the photoresist as a mask, simultaneously removing the preparatory material layer covering the highest upper surface of the shallow trench isolation.

14. A method for manufacturing a flash memory structure as described in claim 11, wherein when the photoresist is formed, the highest surface of the photoresist is lower than the highest upper surface of the shallow trench isolation.

15. A method for manufacturing a flash memory structure as described in claim 11, wherein the preparatory material layer is U-shaped after a portion of the preparatory material layer is removed and before the second insulating layer is formed.

16. A method for fabricating a flash memory structure as described in claim 11, wherein a dielectric layer is disposed between the gate stack structure and the semiconductor substrate.

17. The method of fabricating a flash memory structure as described in claim 16, after forming the first L-shaped element and the second L-shaped element, further includes: using the second insulating layer as a mask, etching the second insulating layer, the dielectric layer and the semiconductor substrate to form a third trench; and forming a wiped gate to fill the third trench.

18. A method for fabricating a flash memory structure as described in claim 11, wherein the preparative material layer comprises tungsten, cobalt, tantalum, titanium, aluminum, copper, titanium nitride, tantalum nitride, polycrystalline silicon, amorphous silicon, or silicon-germanium.

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