Memory device and operation method thereof

Abstract

A memory device and its operating method are disclosed. The memory device may be a high-capacity and high-performance 3D NAND flash memory. The memory device includes a memory block having multiple memory cells. The memory cells have multiple threshold voltage states, and the multiple threshold voltage states are distinguished by multiple reference voltages. The operating method includes performing a read operation on the memory block. The read operation includes sequentially providing one of the multiple reference voltages corresponding to one of the multiple state read periods to a target word line corresponding to a target memory cell during multiple state read periods. The duration of a first state read period is shorter than the duration of any of the other state read periods. The first state read period corresponds to a first reference voltage among the reference voltages.

Claims

1. A method of operating a memory device, wherein the memory device includes a memory block having a plurality of memory cells, the plurality of memory cells having a plurality of threshold voltage states, and the plurality of threshold voltage states being distinguished by a plurality of reference voltages, one of the plurality of reference voltages corresponding to one of the plurality of threshold voltage states, wherein the method of operating the device includes: A read operation is performed on the memory block, wherein the read operation includes: sequentially providing one of the plurality of reference voltages corresponding to one of the plurality of state read periods to the target word line corresponding to the target memory cell during a plurality of state read periods, wherein the duration of at least one first state read period is shorter than the duration of any of the plurality of state read periods other than the at least one first state read period, the at least one first state read period corresponds to at least one first reference voltage among the plurality of reference voltages, and the at least one first reference voltage corresponds to at least one of the plurality of threshold voltage states having the lowest threshold voltage other than the erase state.

2. The operation method as described in claim 1, wherein the duration of the at least one first state reading period is equal to or longer than the sensing time of the bit line corresponding to the target memory cell.

3. The operation method as described in request item 1, wherein the duration of the at least one first state reading period is 1 to 8 microseconds.

4. The method of operation as described in claim 1, wherein the plurality of memory cells are of a multilevel type, wherein the multilevel type means that one of the plurality of memory cells stores more than 1 bit of data.

5. The operation method as described in claim 1, wherein the plurality of memory cells are divided into a plurality of pages, the plurality of pages corresponding to a plurality of character lines, wherein, The read operation on the memory block includes: performing the read operation on a target page, wherein the target page is one of the plurality of pages, the target page includes the target memory cell and corresponds to the target character line.

6. A memory device, comprising: A memory array includes a memory block, wherein the memory block includes a plurality of memory cells, the plurality of memory cells having a plurality of threshold voltage states, and the plurality of threshold voltage states being distinguished by a plurality of reference voltages, one of the plurality of reference voltages corresponding to one of the plurality of threshold voltage states; and a memory controller coupled to the memory array, wherein the memory controller is configured to perform an operation method comprising: performing a read operation on the memory block, wherein the read operation comprises: sequentially providing one of a plurality of reference voltages corresponding to one of the plurality of state read periods to a target word line corresponding to a target memory cell during a plurality of state read periods, wherein the duration of at least one first state read period is shorter than the duration of any of the plurality of state read periods other than the at least one first state read period, the at least one first state read period corresponding to at least one first reference voltage among the plurality of reference voltages, the at least one first reference voltage corresponding to at least one of the plurality of threshold voltage states having the lowest threshold voltage other than the erase state.

7. The memory device as claimed in claim 6, wherein the duration of the at least one first state readout period is equal to or longer than the sensing time of the bit line corresponding to the target memory cell.

8. The memory device as claimed in claim 6, wherein the duration of the at least one first state read period is 1 to 8 microseconds.

9. The memory device as claimed in claim 6, wherein the plurality of memory cells are of a multilevel type, wherein the multilevel type means that one of the plurality of memory cells stores more than 1 bit of data.

10. The memory device as claimed in claim 6, wherein the plurality of memory cells are divided into a plurality of pages, the plurality of pages corresponding to a plurality of character lines, wherein, The memory controller performs the read operation on the target page, wherein the target page is one of the plurality of pages, and the target page includes the target memory cell and corresponds to the target character line.

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