Magnetoresistive random access memory

Abstract

This disclosure proposes a magnetic memory comprising a magnetic tunnel junction and a transistor structure. The magnetic tunnel junction includes a magnetically fixed layer, a tunnel barrier layer, a magnetically free layer, and at least one magnetically enhanced layer. The tunnel barrier layer is stacked with the magnetically fixed layer. The magnetically free layer is stacked with the tunnel barrier layer. The at least one magnetically enhanced layer is disposed corresponding to at least one of the magnetically free layer or the magnetically fixed layer. The transistor structure is electrically connected to the magnetic tunnel junction.

Description

Technical Field

[0001] This invention relates to a magnetic memory, and more particularly to a magnetic memory whose magnetic tunneling junction has a magnetic enhancement layer or a horizontally stacked structure. Prior Technology

[0002] Magnetic memory has gained increasing attention due to its advantages such as fast read / write speeds, excellent durability, non-volatility, and low power consumption. However, improving the magnetic field strength and directionality in the magnetic free layer and magnetic fixed layer of the magnetic tunnel junction, thereby producing high-performance magnetic thin films, remains a goal that needs further effort in this field. Furthermore, magnetic memory cells are susceptible to external signals and magnetic fields, which can interfere with the stored data. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a magnetic memory comprising a magnetic tunnel junction and a transistor structure. The magnetic tunnel junction includes a magnetically fixed layer, a tunnel barrier layer, a magnetically free layer, and at least one magnetically enhanced layer. The tunnel barrier layer is stacked with the magnetically fixed layer. The magnetically free layer is stacked with the tunnel barrier layer. The at least one magnetically enhanced layer is disposed corresponding to at least one of the magnetically free layer or the magnetically fixed layer. The transistor structure is electrically connected in series with the magnetic tunnel junction.

[0004] The present invention also provides a magnetic memory comprising a magnetic tunnel junction and a transistor structure. The magnetic tunnel junction includes a magnetically fixed layer, a tunnel barrier layer, and a magnetically free layer. The tunnel barrier layer and the magnetically fixed layer are arranged side-by-side. The magnetically free layer and the tunnel barrier layer are arranged side-by-side. The transistor structure is electrically connected in series with the magnetic tunnel junction. The bottom surfaces of the magnetically free layer, the tunnel barrier layer, and the magnetically fixed layer are all coplanar. Simple Explanation of the Diagram

[0005] The various embodiments disclosed herein can be best understood by reading the following description and accompanying drawings. It should be noted that, in accordance with standard manufacturing practices in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0006] Figure 1 is a schematic diagram of a magnetic memory according to an embodiment of the present invention.

[0007] Figure 2 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the first embodiment of the present invention.

[0008] Figure 3 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to a second embodiment of the present invention.

[0009] Figure 4 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to a third embodiment of the present invention.

[0010] Figure 5A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the fourth embodiment of the present invention.

[0011] Figure 5B is a cross-sectional view of Figure 5A along section A-A'.

[0012] Figure 6A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to a fifth embodiment of the present invention.

[0013] Figure 6B is a cross-sectional view of Figure 6A along section B-B'.

[0014] Figure 7A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the sixth embodiment of the present invention.

[0015] Figure 7B is a cross-sectional view of Figure 7A along section C-C'.

[0016] Figure 8 is a schematic diagram of a magnetic memory according to another embodiment of the present invention.

[0017] Figure 9 is a schematic diagram of a magnetic tunnel junction in a magnetic memory according to the seventh embodiment of the present invention.

[0018] Figure 10 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the eighth embodiment of the present invention.

[0019] Figure 11 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the ninth embodiment of the present invention.

[0020] Figure 12A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the tenth embodiment of the present invention.

[0021] Figure 12B is a cross-sectional view of Figure 12A along section D-D'.

[0022] Figure 13A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the eleventh embodiment of the present invention.

[0023] Figure 13B is a cross-sectional view of Figure 13A along section E-E'.

[0024] Figure 14A is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the twelfth embodiment of the present invention.

[0025] Figure 14B is a cross-sectional view of Figure 14A along section F-F'. Implementation

[0026] The following disclosure provides various embodiments or examples that can be used to implement different features of this disclosure. Specific examples of elements and configurations described below are for simplification purposes. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, in the following detailed description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, element symbols and / or reference numerals may be reused in multiple embodiments of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0027] Additionally, spatial relative terms (e.g., "beneath," "below," "lower," "above," "upper," and similar terms) are used herein to facilitate the description of the relative relationship between one element or feature depicted in the figures and one or more other elements or features. These spatial relative terms are intended to cover orientations of the device in use or operation other than those depicted in the figures. The device may be placed in other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0028] While the numerical ranges and parameters used to define the broader scope of this invention are approximate, the relevant values ​​in the specific embodiments have been presented as precisely as possible. However, any numerical value inevitably contains standard deviations due to individual testing methods. Here, "substantially," "approximately," or "about" generally refers to a value or range that is understandable to those skilled in the art to which this invention pertains. Alternatively, the terms "substantially," "approximately," or "about" mean that the actual value falls within the standard error understandable to those skilled in the art to which this invention pertains.

[0029] The magnetic memory described in this disclosure refers to Magnetoresistive Random Access Memory (MRAM). In MRAM, each memory cell contains a magnetic tunnel junction (MTJ), which includes a magnetic free layer, a magnetic fixed layer (or magnetic reference layer), and a tunnel barrier layer. The data storage mechanism of MRAM determines the data stored in the memory cell based on the magnetization polarity states of the magnetic free layer and the magnetic reference layer of the magnetic tunnel junction. Since the tunnel barrier layer is a relatively thin insulating structure, a tunnel magnetoresistance (TMR) phenomenon exists between the magnetic free layer, the tunnel barrier layer, and the magnetic fixed layer (or magnetic reference layer). This phenomenon describes how, when the insulating layer is sufficiently thin, electrons can tunnel from one ferromagnetic material to another, and the tunneling probability is related to the magnetization polarity states of the magnetic free layer and the magnetic fixed layer. Specifically, when the magnetization polarities in the magnetic free layer and the magnetic reference layer are in the same direction (or parallel), the magnetic tunnel junction can have a lower resistance; when the magnetization polarities in the magnetic free layer and the magnetic reference layer are opposite (or antiparallel), the magnetic tunnel junction can have a higher resistance. Therefore, by detecting the resistance state of the magnetic tunnel junction, it is possible to determine whether the data stored in the memory cell is "0" or "1".

[0030] Currently, advanced MRAMs include Spin Transfer Torque MRAM (STT-MRAM) and Spin-Orbit Torque MRAM (SOT-MRAM), which differ slightly in their mechanisms for switching magnetization polarity. Broadly speaking, STT-MRAM uses a spin-polarized current to switch the magnetic polarization state of the free layer. This is achieved by transferring spin angular momentum directly through the MTJ (Metal-Temperature Junction Layer) and reversing the magnetization polarity of the free layer. SOT-MRAM uses spin-orbit interaction to achieve faster switching. It generates a spin current by applying current to an adjacent heavy metal layer (without passing through the MTJ) to switch the magnetization polarity of the free layer. When writing "0" and "1", STT-MRAM requires an electron flow through the free layer, while SOT-MRAM only requires an electron to enter the free layer to write "1". Compared to STT-MRAM, SOT-MRAM only requires providing more conductive electrons with the same spin state and injecting them into the ferromagnetic layer. This generates a stronger magnetic moment, making it easier to reverse the magnetization direction of the free layer, thus enabling faster processing speeds and lower power consumption.

[0031] The magnetic memory structure proposed in this disclosure is applicable not only to the aforementioned STT-MRAM or SOT-MRAM, but also to other MRAMs, further improving the performance of various MRAMs. While reversing the magnetization direction is feasible, it has the following drawbacks: (a) The critical current density required to complete the reversal is as high as 10⁷ A / cm². This poses a significant challenge to the specifications of semiconductor wiring current-driven structures. (b) For STT-MRAM, since both read and write operations require current to pass through the insulating tunnel layer of the MTJ, tunneling events increase significantly, increasing the probability of MTJ breakdown. This may lead to device failure due to aging, making it impossible to distinguish between high-resistance and low-resistance states. (c) During operation, the two ferromagnetic layers inside the MTJ are simultaneously subjected to the transfer torque provided by the current, resulting in a very small difference in coercivity between the upper and lower ferromagnetic layers. During write operations, the magnetic free layer and the magnetic fixed layer may flip simultaneously, causing device errors. This probability is called the write error rate (WER). To maintain a WER ≤ 10⁻⁹ (meaning an error occurs only once per billion write jobs on average), a minimum latency is required during write jobs. However, modern computers perform floating-point operations at an average rate exceeding 10¹¹ times per second (10 gigaflops, 10 GFLOPS). Meeting the WER requirement would undoubtedly severely reduce the write speed of STT-MRAM.

[0032] Figure 1 is a schematic diagram of a magnetic memory according to an embodiment of the present invention. As shown in Figure 1, the magnetic memory 10 includes a magnetic tunnel junction 11, a bit line 12, a read word line 13, and a transistor structure 14. The magnetic tunnel junction 11 includes a magnetic fixation layer 111, a tunnel barrier layer 113, a magnetic free layer 115, and at least one magnetic enhancement layer 1111, 1112, 1151, 1152 (not shown in Figure 1, please refer to Figures 2 to 4). The at least one magnetic enhancement layer corresponds to at least one of the magnetic free layer 115 or the magnetic fixation layer 111. The bit line 12 is connected to one of the magnetic free layer 115 and the magnetic fixation layer 111. The transistor structure 14 is electrically connected in series with the magnetic tunnel junction 11. The read word line 13 can be electrically connected to the gate region 145 of the transistor structure 14 for controlling the switching state of the transistor structure 14. In this embodiment, the magnetically fixed layer 111, the tunnel barrier layer 113, and the magnetically free layer 115 are stacked along a vertical direction (Z direction). However, in other embodiments, the stacking order of these layers may be reversed. That is, in this embodiment, the bit line 12 is connected to the magnetically free layer 115, and the conductive structure 15 for writing and reading stored data is connected to the magnetically fixed layer 111. However, in other embodiments, the bit line 12 may be connected to the magnetically fixed layer 111, and the conductive structure 15 may be connected to the magnetically free layer 115.

[0033] The magnetically fixed layer 111 and the magnetically free layer 115 may contain ferromagnetic materials, such as iron (Fe), cobalt (Co), nickel (Ni), cobalt-iron-boron (CoFeB), alloys of the above materials, and multilayer stacked structures. The tunnel barrier layer 113 may contain magnesium oxide (MgO). Magnesium oxide has good tunnel magnetoresistance (TMR) characteristics. When the magnetization polarity directions on both sides of the tunnel barrier layer 113 are the same (parallel), the tunnel barrier layer 113 may have a first resistance; when the magnetization polarity directions on both sides of the tunnel barrier layer 113 are opposite (antiparallel), the tunnel barrier layer 113 may have a second resistance. Using magnesium oxide or other materials as the material of the tunnel barrier layer 113 can effectively improve the difference between the first resistance and the second resistance, resulting in higher signal contrast.

[0034] Bit line 12 may contain copper (Cu) or other conductive materials and may be connected to the upper electrode E1 of magnetic tunnel junction 11 (not shown in FIG. 1, please refer to FIG. 2 to FIG. 4). Conductive structure 15 may contain copper (Cu) or other conductive materials and may be connected to the lower electrode E2 of magnetic tunnel junction 11 (please refer to FIG. 2 to FIG. 4). As shown in FIG. 1, bit line 12 may extend along a first direction (X direction). Bit line 12 may be connected to magnetic tunnel junctions in other magnetic memory cells. When the memory cell is being written to and read from, different current signals may be applied to bit line 12. Specifically, when a write operation is performed, a spin-polarized current is applied to bit line 12, which may change the magnetic state of magnetic tunnel junction 11 or the magnetic polarization direction of magnetic free layer 115. When a read operation is performed, a small sensing current is applied to bit line 12 to measure the resistance state of magnetic tunnel junction 11, which determines whether the data stored in the magnetic tunnel junction 11 of the memory cell is "0" or "1".

[0035] In some embodiments, the magnetic memory 10 is based on a SOT-MRAM memory architecture, but in other embodiments, the magnetic memory 10 may also be based on STT-MRAM or other types of memory architectures. As shown in FIG1, the magnetic memory 10 may optionally include a write line 16, which can be used to write data to the magnetic tunnel junction 11.

[0036] In some embodiments, the transistor structure 14 may include a source region 141, a channel region 142, a drain region 143, a gate region 145, and a gate insulating layer 144.

[0037] Figure 2 is a partial schematic diagram of the magnetic tunnel junction in the magnetic memory according to the first embodiment of the present invention. As described above, at least one magnetic reinforcement layer 1111, 1112, 1151, 1152 is provided corresponding to at least one of the magnetic fixed layer 111 or the magnetic free layer 115. The magnetic reinforcement layer is provided corresponding to the magnetic fixed layer 111 or the magnetic free layer 115. In the first embodiment, it can be understood that the magnetic fixed layer 111 includes two magnetic reinforcement layers 1111, 1112 and a ferromagnetic material layer 1113, and the magnetic free layer 115 includes two magnetic reinforcement layers 1151, 1152 and a ferromagnetic material layer 1153. In other words, the magnetic fixed layer 111 has magnetic reinforcement layers on both the side near the tunnel barrier layer 113 and the side away from the tunnel barrier layer 113. Similarly, the magnetic free layer 115 has magnetic reinforcement layers on both the side near the tunnel barrier layer 113 and the side away from the tunnel barrier layer 113. Each of the magnetic reinforcement layers 1111, 1112, 1151, and 1152 comprises a plurality of magnetic columnar structures M1. These magnetic columnar structures M1 have a primary extension direction (e.g., the Z direction), and this primary extension direction is the same as the stacking direction of the magnetic tunnel junction 11. The magnetic columnar structures M1 may contain ferromagnetic materials, such as iron, cobalt, nickel, ruthenium (Ru), etc., and their length may be between approximately 0.5 and 1 nanometer. Each of the magnetic reinforcement layers 1111, 1112, 1151, and 1152 also comprises a dielectric material M2 disposed between the magnetic columnar structures M1. The dielectric material M2 may be, for example, an oxide or oxynitride of one or more of magnesium (Mg), silicon (Si), titanium (Ti), barium (Ba), calcium (Ca), lanthanum (La), aluminum (Al), manganese (Mn), vanadium (V), and hafnium (Hf).

[0038] In this embodiment, magnetic reinforcement layers 1111 and 1112 belong to the resolvable regions of the magnetically fixed layer 111, and magnetic reinforcement layers 1151 and 1152 belong to the resolvable regions of the magnetically free layer 115. For example, the cross-section of the magnetic tunnel junction 11 can be observed using various electron microscopes, revealing a three-layer structure in the magnetically fixed layer 111, including the magnetic reinforcement layer 1111, the ferromagnetic material layer 1113, and the magnetic reinforcement layer 1112. This layered structure can be distinguished by the obvious columnar structure M1 in the magnetic reinforcement layer, while the ferromagnetic material layer 1113 or 1153 and the tunnel barrier layer 113 do not have obvious columnar structure M1. Furthermore, the magnetic columnar structure M1 of the magnetic reinforcement layer and the ferromagnetic material layer 1113 or 1153 can be distinguished based on the different degrees of electron scattering and electron penetration of the different materials in the aforementioned electron microscope. Alternatively, the magnetic columnar structure M1 and the ferromagnetic material layer 1113 or 1153 may have different lattice arrangement orientations, which can also be observed through the aforementioned electron microscope to distinguish the regions where the two are located.

[0039] Besides using electron microscopy to observe the structure and distinguish the magnetic reinforcement layers in the magnetically fixed layer 111 and the magnetically free layer 115, chemical analysis can also be used to distinguish the magnetic reinforcement layers 1111, 1112, 1151, and 1152 in the magnetically fixed layer 111 and the magnetically free layer 115. For example, using energy-dispersive X-ray spectroscopy (EDX), high-energy X-rays emitted from different regions in the magnetically fixed layer 111 or the magnetically free layer 115 and their corresponding energy levels can be detected. This allows the composition of the measured region to be determined, thereby distinguishing the aforementioned layered structure.

[0040] By incorporating a magnetic reinforcement layer within the magnetically fixed layer or the magnetically free layer, the magnetic field strength and vertical orientation in both layers can be concentrated and enhanced, resulting in a high-performance vertically anisotropic magnetic thin film. For example, in conventional MRAM, a critical current density as high as 10⁷ A / cm² is required to flip the magnetic field direction of the MTJ. However, in this embodiment, because the magnetic reinforcement layer effectively enhances the magnetic field strength, the current density can be reduced to complete the flip, effectively extending the stability and lifespan of the MRAM. For STT-MRAM, both read and write operations require current to pass through the insulating tunnel layer of the MTJ. Effectively reducing the current required for read and write events will significantly reduce the probability of MTJ breakdown. Furthermore, the magnetic reinforcement layer in the magnetically fixed layer effectively stabilizes the magnetic polarization direction of the magnetically fixed layer, preventing it from changing during write operations. This avoids simultaneous flipping of the magnetically free layer and the magnetically fixed layer, shortening the waiting time for each write operation and meeting the demands of modern, higher-speed computing. Additionally, the number of magnetic reinforcement layers can be adjusted as needed; this disclosure provides only some embodiments for reference.

[0041] Figure 3 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the second embodiment of the present invention. In the second embodiment, the magnetically fixed layer 111 includes a magnetically reinforcing layer 1112 and a ferromagnetic material layer 1113, and the magnetically free layer 115 includes a magnetically reinforcing layer 1152 and a ferromagnetic material layer 1153. The remaining structure is basically the same as that in the first embodiment. Those skilled in the art will understand that, based on the first and second embodiments, the number, thickness, and position of the magnetically reinforcing layers in the magnetically fixed layer 111 or the magnetically free layer 115 can be adjusted according to requirements. For example, the magnetically fixed layer 111 may include one or more magnetically reinforcing layers, and the magnetically free layer may include one or more magnetically reinforcing layers.

[0042] Figure 4 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to a third embodiment of the present invention. In the third embodiment, the magnetic reinforcement layer and the magnetic fixation layer together form a first composite layer 111', and / or the magnetic reinforcement layer and the magnetic free layer together form a second composite layer 115'. The first composite layer 111' and the second composite layer 115' each include a magnetic columnar structure M1' and a dielectric material M2'. The dielectric material M2' is disposed in or fills the gaps between the magnetic columnar structures M1'. The magnetic columnar structures M1' and the dielectric material M2' can be the same as those in the previous embodiments, and will not be described again. Since the magnetic columnar structure of the magnetic reinforcement layer can include ferromagnetic materials in the magnetic fixation layer and the magnetic free layer, the magnetic reinforcement layer can be integrated with the magnetic fixation layer or the magnetic free layer to form a composite layer 111' or 115', respectively. In addition, the third embodiment can also be combined with the first or second embodiment. For example, the magnetic fixing layer 111 in Figure 3 can be a composite layer (as shown in the composite layer 111' in Figure 4), while the magnetic free layer 115 in Figure 3 can be a structure of a magnetic reinforcement layer with distinguishable regions (as shown in the magnetic reinforcement layers 1151, 1152 and the ferromagnetic material layer 1153 in Figure 2).

[0043] Please refer to Figures 2 to 4. In these embodiments, the magnetic reinforcement layer or composite layer process may be as follows: forming a dielectric material layer, such as an oxide or oxynitride of one or more of magnesium (Mg), silicon (Si), titanium (Ti), barium (Ba), calcium (Ca), lanthanum (La), aluminum (Al), manganese (Mn), vanadium (V), and hafnium (Hf); defining a plurality of porous regions in the dielectric material layer by appropriate patterning and etching processes (e.g., wet or dry etching); and forming a plurality of magnetic columnar structures extending along the stacking direction of the magnetic tunnel junction in the porous regions of the dielectric material layer by an electroplating process.

[0044] On the other hand, at least one of the upper surface, lower surface, or any side surface of the magnetic tunnel junction in some embodiments of this disclosure may be surrounded by one or more electromagnetic wave absorbing or barrier layers. Figure 5A is a partial schematic diagram of the magnetic tunnel junction in the magnetic memory according to the fourth embodiment of the present invention, and Figure 5B is a cross-sectional schematic diagram of Figure 5A along section A-A'. In the fourth embodiment, the side surfaces 115A, 115B, 115C, and 115D of the magnetic tunnel junction 11 (including the magnetic fixing layer 111, the tunnel barrier layer 113, and the magnetic free layer 115) are surrounded by electromagnetic wave absorbing or barrier layers. Specifically, the electromagnetic wave absorbing or barrier layers may include either a non-magnetic ferrite 21 or a conductive layer (including copper wires 12 and 15). The non-magnetic ferrite 21 may be designed to be grounded. For example, because the non-magnetic ferrite 21 has a very high resistance, direct contact with at least one side surface of the magnetic tunnel junction 11 will not affect writing and reading memory. Taking the electromagnetic wave absorption or barrier layer containing non-magnetic ferrite 21 as an example, it can absorb electromagnetic wave signals from the outside, preventing the magnetization direction inside the magnetic tunnel junction 11 from being disturbed by changes in the external magnetic field. Furthermore, in this embodiment, the upper surface of the magnetic tunnel junction 11 can be covered by the projection of the bit line 12 (e.g., a conductive layer structure such as a copper wire), and the lower surface of the magnetic tunnel junction 11 can be covered by the projection of the conductive structure 15 (e.g., a conductive layer structure such as a copper wire). Thus, even if the upper and lower surfaces of the magnetic tunnel junction 11 are not covered with non-magnetic ferrite, the bit line 12 and the conductive structure 15 can still produce an electromagnetic shielding effect, preventing the magnetization direction inside the magnetic tunnel junction 11 from being disturbed by changes in the external magnetic field. In some embodiments, the size of the aforementioned conductive layer structure such as the copper wire (e.g., the width of the copper wire in a top view) is larger than the size of the magnetic tunnel junction 11 (e.g., the diameter of the magnetic tunnel junction in a top view), thereby achieving a better shielding effect.

[0045] Figure 6A is a partial schematic diagram of the magnetic tunnel junction in the magnetic memory according to the fifth embodiment of the present invention, and Figure 6B is a cross-sectional schematic diagram of Figure 6A along section B-B'. In the fifth embodiment, the side surfaces 115A, 115B, 115C, and 115D of the magnetic tunnel junction 11 are surrounded by an electromagnetic wave absorbing or barrier layer and a non-magnetic insulating layer 22, and the electromagnetic wave absorbing or barrier layer may include either a magnetic ferrite 21' or a conductive layer (including copper wires 12 and 15). The magnetic ferrite 21' is separated from at least one of the sides of the magnetic tunnel junction 11 by the non-magnetic insulating layer 22. In the fourth and fifth embodiments, by surrounding the magnetic tunnel junction 11 with an electromagnetic wave absorbing or barrier layer, the magnetic field state of the magnetic tunnel junction is less susceptible to interference from external signals. The fifth embodiment differs from the fourth embodiment in that the magnetic ferrite 21' in the electromagnetic wave absorption or barrier layer does not directly contact at least one of the surfaces 115A, 115B, 115C, and 115D of the magnetic tunnel junction 11. By additionally providing a non-magnetic insulating layer 22 and separating the four interconnected sides of the magnetic ferrite 21' shown in Figure 6B with an insulating and non-magnetic material 200 (such as silicon dioxide), when the electromagnetic wave absorption or barrier layer is a magnetic ferrite, its horizontal magnetic field strength (approximately one-tenth of the magnetic field strength of the magnetic free layer 115) can be set before the magnetic memory process, causing it to magnetically couple with the magnetic free layer 115, etc., resulting in the vertical magnetic field of the magnetic free layer 115 deviating from the vertical line by about 5 degrees, which can reduce the magnitude of the current for changing the stored information when writing memory. This method can achieve the current purpose of designing field-free switching using the wedge structure of magnetic memory. This structure can also isolate the magnetic tunnel junction 11 from the outside world, which can be described as killing two birds with one stone. In some embodiments, the non-magnetic insulating layer 22 may contain, for example, oxides or oxynitrides.

[0046] Figure 7A is a partial schematic diagram of the magnetic tunnel junction 11 in the magnetic memory according to the sixth embodiment of the present invention, and Figure 7B is a cross-sectional schematic diagram of Figure 7A along section C-C'. In the sixth embodiment, the electromagnetic wave absorbing or barrier layer disposed outside the magnetic tunnel junction 11 includes a conductive layer (e.g., a coaxial cable). The peripheral structure 30 of this coaxial cable is disposed on at least one side of the magnetic tunnel junction 11 and extends along the stacking direction of the magnetic tunnel junction 11. Generally, a coaxial cable includes an inner conductor, an inner insulation layer, an outer conductor, and an outer insulation layer. In this embodiment, the peripheral structure of the coaxial cable may include a peripheral conductive structure and a peripheral insulation structure. For example, referring to Figure 7B, the peripheral structure of the coaxial cable refers to the structure that needs to be grounded, such as the outer conductor and the outer insulation layer, and the magnetic tunnel junction 11 located at the center replaces the traditional inner conductor structure. For example, the coaxial cable is a type of coaxial cable. The outer structure 30 of the coaxial cable may include a copper layer 31, a phosphor bronze alloy layer 32, a barrier layer 33, and an insulating layer 34. The copper layer 31 is adjacent to or surrounded by the phosphor bronze alloy layer 32. The phosphor bronze alloy layer 32 may contain cuprous phosphide (Cu3P) and, being adjacent to the copper layer 31, can serve as a seed layer, adhesive layer, and partial diffusion barrier, and can also prevent the copper layer 31 from oxidizing during the manufacturing process. The barrier layer 33 is groundable and may contain, for example, titanium nitride (TiN). As shown in Figure 7A, the copper layer 31 and / or the phosphor bronze alloy layer 32 can be grounded, thereby providing an electromagnetic shielding effect for the magnetic tunnel junction 11.

[0047] The aforementioned fourth to sixth embodiments describe examples of providing an electromagnetic wave absorption or barrier layer on the outside of the magnetic tunnel junction. Regarding the upper and lower surfaces of the magnetic tunnel junction, as previously described, the copper wires of the bit line 12 and the conductive structure 15 have a shielding effect. That is, the bit line 12 and the conductive structure 15 are located on the upper and lower surfaces of the magnetic tunnel junction 11, respectively, and are configured to shield the magnetic tunnel junction 11 and transmit signals to the magnetic tunnel junction 11 for write and read operations.

[0048] Figure 8 is a schematic diagram of a magnetic memory according to another embodiment of the present invention. As shown in Figure 8, the magnetic memory 50 includes a magnetic tunnel junction 51, a bit line 52, a read word line 53, and a transistor structure 54. The magnetic tunnel junction 51 includes a magnetically fixed layer 511, a tunnel barrier layer 513, and a magnetically free layer 515. The bit line 52 is connected to one of the magnetically free layer 515 and the magnetically fixed layer 511. The transistor structure 54 is electrically connected to the magnetic tunnel junction 51. In some embodiments, the read word line 53 may be connected or electrically connected to the gate region 545 of the transistor structure 54 for controlling the switching state of the transistor structure 54. In this embodiment, the bottom surface 515S of the magnetically free layer 515, the bottom surface 513S of the tunnel barrier layer 513, and the bottom surface 511S of the magnetically fixed layer 511 form a coplanarity S, for example, a coplanarity along the horizontal direction (X direction). In this embodiment, the magnetic fixation layer 511, the tunnel barrier layer 513, and the magnetic free layer 515 are arranged along a horizontal direction (X direction), but this disclosure does not limit the arrangement order of the magnetic fixation layer 511, the tunnel barrier layer 513, and the magnetic free layer 515. That is, in this embodiment, the bit line 52 can be connected to the magnetic free layer 515 via electrode E1, and the conductive structure 55 for writing and reading stored data can be connected to the magnetic fixation layer 511 via electrode E2; however, in other embodiments, the bit line 52 can be connected to the magnetic fixation layer 511, and the conductive structure 55 can be connected to the magnetic free layer 515. As shown in FIG8, the magnetic memory 50 may selectively include a write line 56, which can be used to write data into the magnetic tunnel junction 51.

[0049] Regarding the materials of the magnetic fixing layer 511, tunnel barrier layer 513, and magnetic free layer 515, please refer to the foregoing embodiments, and will not be repeated here. The difference between this embodiment and the foregoing embodiments is that the magnetic fixing layer 511, tunnel barrier layer 513, and magnetic free layer 515 are arranged horizontally. This allows for the completion of multiple repetitive structures with the same composition in a single semiconductor process, shortening the process time. Figure 9 is a schematic diagram of a magnetic tunnel junction in a magnetic memory according to the seventh embodiment of the present invention. In the seventh embodiment, the magnetic fixing layer 511 may include multiple ferromagnetic material layers and non-ferromagnetic material layers arranged side by side. For example, the first layer L1 contains platinum (e.g., 5 nm thick), the second layer L2 contains a stacked structure of cobalt and platinum (e.g., a side-by-side structure of 6 layers of cobalt with a thickness of 0.5 nm and platinum with a thickness of 0.3 nm), the third layer L3 contains cobalt (e.g., 0.5 nm thick), the fourth layer L4 contains ruthenium, the fifth layer L5 contains a stacked structure of cobalt and platinum (e.g., a side-by-side structure of 2 layers of cobalt with a thickness of 0.5 nm and platinum with a thickness of 0.3 nm), the sixth layer L6 contains cobalt (e.g., 0.5 nm thick), the seventh layer L7 contains tantalum (Ta), and the eighth layer L8 contains cobalt iron boron (e.g., 1.3 nm thick).

[0050] Through this multilayer arrangement of ferromagnetic / non-ferromagnetic / ferromagnetic layers, an artificial antiferromagnetic (SAF) material can be formed, which has a high magnetic coupling strength, can avoid changes in magnetic field direction caused by thermal disturbance, and improves the anti-interference capability of the magnetic tunnel junction 51. Furthermore, the multilayer arrangement structure of this embodiment can also be applied to the magnetic tunnel junction 11 of the aforementioned first to sixth embodiments. However, it should be noted that by forming multiple layers of artificial antiferromagnetic material in the horizontally arranged magnetic tunnel junction 51, compared to the vertical arrangement of the aforementioned embodiments, multiple repeating structures with the same composition can be formed simultaneously in a single semiconductor process, thereby shortening the process time and improving efficiency. For example, platinum can be present in the first layer L1, the second layer L2, and the fifth layer L5, and can be formed simultaneously; cobalt can be present in the second layer L2, the third layer L3, the fifth layer L5, and the sixth layer L6, and can be formed simultaneously. Thus, compared to the vertical stacking structure where each layer needs to be formed one by one using semiconductor processes, the horizontally arranged magnetic tunnel junctions 51 can effectively reduce semiconductor process steps and shorten process time.

[0051] Figure 10 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the eighth embodiment of the present invention. In the eighth embodiment, the magnetic tunnel junction 51 further includes at least one magnetic reinforcement layer 5111, 5151, which is disposed corresponding to at least one of the magnetic free layer 515 or the magnetic fixed layer 511. The magnetic reinforcement layers 5111, 5151 may include a magnetic columnar structure M1 and a dielectric material M2. Regarding how the magnetic columnar structure M1 is disposed corresponding to at least one of the magnetic free layer 515 and / or the magnetic fixed layer 511, and the composition of the dielectric material M2 surrounding the magnetic columnar structure M1, please refer to the foregoing embodiments, which will not be repeated here. The main difference between the eighth embodiment and the second embodiment is that the magnetic fixed layer 511, the tunnel barrier layer 513 and the magnetic free layer 515 in the magnetic tunnel junction 51 of this embodiment are disposed along the horizontal direction (e.g., the X direction), and the main extension direction of the magnetic columnar structure M1 is extending in the horizontal direction (e.g., the X direction).

[0052] Figure 11 is a partial schematic diagram of a magnetic tunnel junction in a magnetic memory according to the ninth embodiment of the present invention. In the ninth embodiment, the magnetic reinforcement layer and the magnetic fixation layer together form a first composite layer 511', and / or the magnetic reinforcement layer and the magnetic free layer together form a second composite layer 515'. The first composite layer 511' and the second composite layer 515' each include a magnetic columnar structure M1' and a dielectric material M2'. The dielectric material M2' is disposed in or fills the gaps between the magnetic columnar structures M1'. Regarding how the magnetic columnar structure M1' and the magnetic fixation layer 511' and / or the magnetic free layer 515' respectively form a first composite layer 511' and / or a second composite layer 515', and the composition surrounding the magnetic columnar structure M1', please refer to the foregoing embodiments, which will not be repeated here. Since the magnetic columnar structure of the magnetic reinforcement layer may include ferromagnetic materials in the magnetic fixation layer and the magnetic free layer, the magnetic reinforcement layer may be integrated with the magnetic fixation layer or the magnetic free layer to form a composite layer 511' or 515' respectively. In the eighth and ninth embodiments, the magnetic columnar structure has a main extension direction (e.g., the X direction), and this main extension direction is the same as the side-by-side arrangement direction of the magnetic tunnel junction 51.

[0053] Please refer to Figures 10 and 11. In these embodiments, in addition to the aforementioned horizontally arranged magnetic tunnel junctions 51, which can simultaneously form multiple repeating structures with the same composition in a single semiconductor process deposition method to shorten the process time and improve efficiency, the magnetic reinforcement layer or composite layer can be formed by electroplating before or after other deposition steps. For example, multiple porous regions are defined in the dielectric material M2 / M2' by appropriate patterning and etching processes (e.g., wet or dry etching); through the electroplating process, multiple magnetic columnar structures M1 / M1' extending along the stacking direction (X direction) of the magnetic tunnel junction are formed in the porous regions of the dielectric material M2 / M2'.

[0054] Figure 12A is a partial schematic diagram of the magnetic tunnel junction in the magnetic memory according to the tenth embodiment of the present invention. Figure 12B is a cross-sectional schematic diagram of Figure 12A along section D-D'. In the tenth embodiment, the magnetization directions of the magnetic free layer 515 and the magnetic fixed layer 511 are both horizontal. At least one of the following surfaces of the magnetic tunnel junction 51, which is perpendicular to the side-by-side arrangement direction (X direction) and electrically connected to the first electrode E1, the second surface 511L electrically connected to the second electrode E2, or parallel to the side-by-side arrangement direction (X direction): the third surface 515A, the fourth surface 515B, the fifth surface 515C, and the sixth surface 515D, is surrounded by one or more electromagnetic wave absorbing or barrier layers. Specifically, the electromagnetic wave absorbing or barrier layer may include either a non-magnetic ferrite 61 or a conductive layer (including copper wires 52, 55). For example, the non-magnetic ferrite 61 may be designed so that only the outer surface is grounded, and the interior is not grounded (not shown). For example, because the non-magnetic ferrite 61 has a very high resistance, direct contact with at least one side of the magnetic tunnel junction 51 will not affect memory writing and reading. Taking the electromagnetic wave absorption or barrier layer containing the non-magnetic ferrite 61 as an example, it can absorb electromagnetic wave signals from the outside, preventing interference from changes in the external magnetic field on the magnetization direction inside the magnetic tunnel junction 51. The aforementioned non-magnetic ferrite 61 can directly contact at least one of the third surface 515A, fourth surface 515B, fifth surface 515C, and sixth surface 515D of the magnetic tunnel junction 51. For example, the electromagnetic wave absorption or barrier layer can directly contact the third surface 515A, fourth surface 515B, fifth surface 515C, and sixth surface 515D of the magnetic tunnel junction 51. Furthermore, the first surface 515L of the magnetic tunnel junction 51 can be covered by the lateral projection of the bit line 52 (e.g., a conductive layer structure such as a copper wire), and the second surface 511L of the magnetic tunnel junction 51 can be covered by the lateral projection of the conductive structure 55 (e.g., a conductive layer structure such as a copper wire). Thus, even if the first surface 515L and the second surface 511L of the magnetic tunnel junction 51 are not covered by non-magnetic ferrite, the bit line 52 and the conductive structure 55 can still produce an electromagnetic shielding effect, preventing the magnetization direction inside the magnetic tunnel junction 51 from being disturbed by changes in the external magnetic field. In some embodiments, the size of the aforementioned conductive layer structure such as the copper wire (e.g., the width of the copper wire in the X-direction view) is larger than the size of the magnetic tunnel junction 51 (e.g., the diameter of the magnetic tunnel junction in the X-direction view), thereby achieving a better shielding effect.

[0055] Figure 13A is a partial schematic diagram of the magnetic tunnel junction in the magnetic memory according to the eleventh embodiment of the present invention, and Figure 13B is a cross-sectional schematic diagram of Figure 13A along section E-E'. In the eleventh embodiment, the magnetization directions of the magnetic free layer 515 and the magnetic fixed layer 511 are both horizontal. The third surface 515A, the fourth surface 515B, the fifth surface 515C, and the sixth surface 515D of the magnetic tunnel junction 51 are surrounded by an electromagnetic wave absorbing or barrier layer and a non-magnetic insulating layer 62, and the electromagnetic wave absorbing or barrier layer may include either a magnetic ferrite 61' or a conductive layer (including copper wires 52, 55). The magnetic ferrite 61' is separated from at least one of the third surface 515A, the fourth surface 515B, the fifth surface 515C, and the sixth surface 515D of the magnetic tunnel junction 51 by a non-magnetic insulating layer 62. In the tenth and eleventh embodiments, by surrounding the magnetic tunnel junction 51 with an electromagnetic wave absorbing or barrier layer, the magnetic field state of the magnetic tunnel junction can be made less susceptible to interference from external signals. The eleventh embodiment differs from the tenth embodiment in that the magnetic ferrite 61' in the electromagnetic wave absorbing or barrier layer does not directly contact at least one of the surfaces 515A, 515B, 515C, and 515D of the magnetic tunnel junction 51. By additionally providing a non-magnetic insulating layer 62, and separating the four sides of the magnetic ferrite 61' shown in Figure 13B from each other with an insulating and non-magnetic material 200 (such as silicon dioxide), when the electromagnetic wave absorbing or barrier layer is a magnetic ferrite, its vertical magnetic field strength (approximately one-tenth the magnetic field strength of the magnetic free layer 515) can be set before the magnetic memory process, causing magnetic coupling between it and the magnetic free layer 515, resulting in the horizontal magnetic field of the magnetic free layer 515 deviating from the horizontal line by approximately 5 degrees. This reduces the magnitude of the current required to change the stored information when writing to memory. This method achieves the current goal of designing field-free switching using a wedge structure of magnetic memory. Furthermore, this structure isolates the magnetic tunnel junction 51 from the outside world, achieving two goals at once. As shown in Figures 13A and 13B, the non-magnetic insulating layer 62 and the magnetic ferrite 61' are first deposited using a semiconductor process in the space of the fifth surface 515C, which will subsequently directly contact the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has not yet been formed at this stage). Next, the non-magnetic insulating layer 62 and the magnetic ferrite 61' are deposited using a semiconductor process in the space of the fourth surface 515B and the sixth surface 515D, which will subsequently directly contact the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has not yet been formed at this stage). Then, in the aforementioned manner, multiple layers of the same repeating structure are simultaneously formed into horizontally arranged magnetic tunnel junctions 51 using a single semiconductor process. Finally, the non-magnetic insulating layer 62 and the magnetic ferrite 61' are deposited using a semiconductor process on the third surface 515A of the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has already been formed at this stage).In some embodiments, the non-magnetic insulating layer 62 may comprise, for example, oxides or oxynitrides.

[0056] Figure 14A is a partial schematic diagram of the magnetic tunnel junction 51 in the magnetic memory according to the twelfth embodiment of the present invention, and Figure 14B is a cross-sectional schematic diagram of Figure 14A along section F-F'. In the twelfth embodiment, the magnetization directions of both the magnetic free layer 515 and the magnetic fixed layer 511 are horizontal. The electromagnetic wave absorbing or barrier layer disposed on the outside of the magnetic tunnel junction 51 includes a conductive layer (e.g., the peripheral structure 70 of a coaxial cable). The peripheral structure 70 of the coaxial cable is disposed on at least one of the third surface 515A, the fourth surface 515B, the fifth surface 515C, and the sixth surface 515D of the magnetic tunnel junction 51 and extends along the parallel arrangement direction (X direction) of the magnetic tunnel junction 51. Generally, a coaxial cable includes an inner conductor, an inner insulation layer, an outer conductor, and an outer insulation layer. In this embodiment, the peripheral structure of the aforementioned coaxial cable may include a peripheral conductive structure and a peripheral insulating structure. For example, referring to Figure 14B, the so-called peripheral structure of the coaxial cable refers to the structure of the outer conductor and outer insulation layer, with the magnetic tunnel junction 51 located at the center replacing the traditional inner conductor structure. For instance, the peripheral structure 70 of the coaxial cable may include a copper layer 71, a phosphor bronze alloy layer 72, a barrier layer 73, and an insulation layer 74. The copper layer 71 is adjacent to the phosphor bronze alloy layer 72, or surrounded on both sides by the phosphor bronze alloy layer 72. The phosphor bronze alloy layer 72 may contain cuprous phosphide (Cu3P), and its proximity to the copper layer 71 serves as a seed layer, adhesion layer, and partial diffusion barrier, while also preventing the copper layer 71 from oxidizing during the manufacturing process. The barrier layer 73 is optional, for example, it may contain titanium nitride (TiN). As shown in Figure 14A, the copper layer 71 and / or the phosphor bronze alloy layer 72 can be used for grounding, thereby providing electromagnetic shielding for the magnetic tunnel junction 51. In some embodiments, the peripheral structure 70 of the coaxial cable may first be formed by semiconductor process deposition or electroplating of inner and outer insulating layers 74, barrier layer 73, phosphor bronze alloy layer 72, and copper layer 71 in the space that will subsequently directly contact the fifth surface 515C of the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has not yet been formed at this time). Then, the peripheral structure 70 of the coaxial cable is formed by semiconductor process deposition in the space that will subsequently directly contact the fourth surface 515B and sixth surface 515D of the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has not yet been formed at this time). Then, the multilayer repeating structure with the same composition is deposited in a single semiconductor process deposition step in the manner described above, and horizontally arranged magnetic tunnel junctions 51 are formed simultaneously. Finally, the peripheral structure 70 of the coaxial cable is formed by semiconductor process deposition on the third surface 515A of the magnetic tunnel junction 51 (note that the magnetic tunnel junction 51 has been formed at this time).

[0057] The aforementioned tenth to twelfth embodiments describe examples of providing an electromagnetic wave absorption or barrier layer on the outside of the magnetic tunnel junction. Regarding the upper and lower surfaces of the magnetic tunnel junction, as previously described, the copper wires of the bit line 52 and the conductive structure 55 can provide a certain shielding effect. That is, the copper wires of the bit line 52 and the copper wires of the sensing conductive structure 55 are located on the first surface 515L and the second surface 511L of the magnetic tunnel junction 51, respectively, and are configured to shield the magnetic tunnel junction 51 and to transmit signals to the magnetic tunnel junction 51 for write and read operations.

[0058] The foregoing description briefly outlines the features of certain embodiments of the present invention, enabling those skilled in the art to more fully understand the various forms of this disclosure. Those skilled in the art will readily recognize that this disclosure serves as a basis for designing or modifying other operations and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0059] Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, apparatuses, methods, and steps described in the specification. As will readily apparent from the disclosure of this disclosure to those skilled in the art to which this invention pertains, the same functions or results as the corresponding embodiments described in this disclosure can be performed using existing or subsequently developed processes, machines, manufactures, compositions of matter, apparatuses, methods, or steps. Therefore, the appended claims also cover such processes, machines, manufactures, compositions of matter, apparatuses, methods, and steps.

[0060] 10,50: Magnetic memory 11,51: Magnetic tunnel junction 12,52: Bit line 13,53: Read character lines 14,54: Transistor Structure 15,55: Conductive structure 16,56: Write lines 21,21',61,61': Ferrite 22,62: Non-magnetic insulating layer 30, 70: External structure of coaxial cable 31,71: Copper layer 32,72: Phosphor bronze alloy layer 33,73: Barrier Layer 34,74: Insulation layer 111,511: Magnetic fixing layer 111', 511': First composite layer 113,513: Tunnel barrier layer 115,515: Magnetic Free Layer 115', 515': Second composite layer 115A, 115B, 115C, 115D: Side surfaces 141,541: Source region 142,542: Passage Area 143,543: Drainage region 144,544: Gate insulation layer 145,545: Gate region 200: Insulating and non-magnetic materials 511L: Second Surface 511S: Bottom surface of the magnetic fixing layer 513S: Bottom surface of tunnel barrier layer 515A, 515B, 515C, 515D: Surface 515L: First Surface 515S: Bottom surface of the magnetic free layer 1111,1112,5111,5112: Magnetic reinforcement layer 1113: Ferromagnetic material layer 1151, 1152, 5151, 5152: Magnetic reinforcement layer 1153: Ferromagnetic material layer E1, E2: Electrodes L1~L8: Layers M1, M1': Magnetic columnar structure M2, M2': Dielectric material

Claims

1. A magnetic memory, comprising: a magnetic tunnel junction, comprising: a magnetically fixed layer; a tunnel barrier layer stacked with the magnetically fixed layer; a magnetically free layer stacked with the tunnel barrier layer; and at least one magnetically enhanced layer disposed corresponding to at least one of the magnetically free layer or the magnetically fixed layer, wherein the at least one magnetically enhanced layer comprises a plurality of magnetic pillar structures having a main extension direction substantially the same as the stacking direction of the magnetic tunnel junction; and a transistor structure electrically connected to the magnetic tunnel junction.

2. The magnetic memory as claimed in claim 1, wherein the at least one magnetic enhancement layer defines a recognizable portion of at least one of the magnetic free layer or the magnetic fixed layer.

3. The magnetic memory as claimed in claim 1, wherein the at least one magnetic enhancement layer and the magnetic fixation layer together form a first composite layer, and / or together with the magnetic free layer form a second composite layer.

4. The magnetic memory as claimed in claim 1, wherein at least one of the upper surface, lower surface, or any side surface of the magnetic tunnel junction is surrounded by one or more electromagnetic wave absorbing or barrier layers.

5. The magnetic memory as claimed in claim 4, wherein the one or more electromagnetic wave absorbing or barrier layers comprise at least one of magnetic ferrite, non-magnetic ferrite, or conductive layer.

6. The magnetic memory as claimed in claim 5, wherein the non-magnetic ferrite directly contacts at least one of the sides of the magnetic tunnel junction, and the magnetic ferrite is separated from at least one of the sides of the magnetic tunnel junction by an insulating layer.

7. The magnetic memory as claimed in claim 5, wherein the conductive layer is a peripheral structure of a coaxial cable formed of a phosphor bronze alloy layer, the peripheral structure of the coaxial cable being disposed on at least one of the sides of the magnetic tunnel junction and extending along the stacking direction of the magnetic tunnel junction.

8. The magnetic memory as claimed in claim 7, wherein the peripheral structure of the coaxial cable further includes a copper layer adjacent to the phosphor bronze alloy layer.

9. The magnetic memory as claimed in claim 5, wherein the conductive layer further comprises copper wires located on the upper and lower surfaces of the magnetic tunnel junction and configured to shield the magnetic tunnel junction and transmit signals from the magnetic tunnel junction.

10. The magnetic memory as claimed in claim 1, wherein the plurality of magnetic columnar structures comprise iron, cobalt, nickel and / or ruthenium.

11. A magnetic memory, comprising: a magnetic tunnel junction, comprising: a magnetic fixation layer; a tunnel barrier layer disposed side-by-side with the magnetic fixation layer; and a magnetic free layer disposed side-by-side with the tunnel barrier layer; at least one magnetic enhancement layer disposed corresponding to at least one of the magnetic free layer or the magnetic fixation layer, wherein the at least one magnetic enhancement layer comprises a plurality of magnetic columnar structures; and a transistor structure electrically connected to the magnetic tunnel junction, wherein the bottom surfaces of the magnetic free layer, the tunnel barrier layer, and the magnetic fixation layer are coplanar.

12. The magnetic memory as claimed in claim 11, wherein the magnetic fixing layer comprises a ferromagnetic material layer and a non-ferromagnetic material layer arranged side by side.

13. The magnetic memory as claimed in claim 11, wherein the at least one magnetic enhancement layer and the magnetic fixation layer together form a first composite layer, and / or together with the magnetic free layer form a second composite layer.

14. The magnetic memory as claimed in claim 11, wherein the magnetic columnar structures have a primary extension direction that is substantially the same as the side-by-side orientation of the magnetic tunnel junction.

15. The magnetic memory as claimed in claim 11, wherein at least one of the first surface, the second surface, or the third surface, the fourth surface, the fifth surface, and the sixth surface, which are parallel to the side-by-side orientation, or perpendicular to the side-by-side orientation, is surrounded by one or more electromagnetic wave absorbing or barrier layers.

16. The magnetic memory as claimed in claim 15, wherein the one or more electromagnetic wave absorbing or barrier layers comprise at least one of magnetic ferrite, non-magnetic ferrite, or conductive layer.

17. The magnetic memory as claimed in claim 16, wherein the non-magnetic ferrite directly contacts at least one of the third, fourth, fifth, and sixth surfaces of the magnetic tunnel junction, and the magnetic ferrite is separated from at least one of the third, fourth, fifth, and sixth surfaces of the magnetic tunnel junction by an insulating layer.

18. The magnetic memory as claimed in claim 16, wherein the conductive layer is a peripheral structure of a coaxial cable formed of a phosphor bronze alloy layer, the peripheral structure of the coaxial cable being disposed on at least one of the third surface, the fourth surface, the fifth surface, and the sixth surface of the magnetic tunnel junction and extending along the side-by-side arrangement direction of the magnetic tunnel junction.

19. The magnetic memory as claimed in claim 18, wherein the peripheral structure of the coaxial cable further includes a copper layer adjacent to the phosphor bronze alloy layer.

20. The magnetic memory as claimed in claim 11, wherein the at least one magnetic enhancement layer comprises a plurality of dielectric materials, wherein each of the plurality of dielectric materials is disposed between two of the plurality of magnetic columnar structures.

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