Semiconductor device and method for making the same

Abstract

This application provides a semiconductor device and a method for manufacturing the same. The method includes: providing a package comprising: a substrate including a top surface and a bottom surface; an electronic component mounted on the top surface of the substrate; and a first sealant disposed on the top surface of the substrate and sealing the electronic component; forming a reference mark in the first sealant; and forming a first shielding layer on the first sealant using an aerosol spraying device, wherein the first shielding layer is located at a predetermined distance from the reference mark and above the electronic component.

Description

[Technical Field]

[0001] This application relates generally to semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing a semiconductor device. [Previous Technology]

[0002] The semiconductor industry continues to face complex integration challenges as consumers demand smaller, faster, and higher-performing electronics, and increasingly more functionality packaged into a single device. One solution is System-in-Package (SiP). SiP can include multiple semiconductor components, such as semiconductor dies, semiconductor packages, integrated passive devices, and discrete active or passive electronic components, all integrated into a single semiconductor package. Because high-speed digital and radio frequency (RF) semiconductor packages may be integrated into SiPs, electromagnetic interference (EMI) can easily occur. EMI can interrupt, impede, or otherwise degrade or limit the performance of circuitry in a SiP.

[0003] Therefore, there is a need to reduce EMI in SiP. [Summary of the Invention]

[0004] The purpose of this application is to provide a semiconductor device with reduced electromagnetic interference.

[0005] According to one aspect of the embodiments of this application, a method for manufacturing a semiconductor device is provided. The method may include: providing a package comprising: a substrate including a top surface and a bottom surface; an electronic component mounted on the top surface of the substrate; and a first sealant disposed on the top surface of the substrate and sealing the electronic component; forming a reference mark in the first sealant; and forming a first shielding layer on the first sealant, wherein the first shielding layer is located at a predetermined distance from the reference mark and above the electronic component.

[0006] According to another aspect of the embodiments of this application, a semiconductor device is provided. The semiconductor device may include: a substrate, the substrate including a top surface and a bottom surface; an electronic component mounted on the top surface of the substrate; a first sealant disposed on the top surface of the substrate and sealing the electronic component; a reference mark formed in the first sealant; and a first shielding layer formed on the first sealant, wherein the first shielding layer is located at a predetermined distance from the reference mark and above the electronic component.

[0007] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and not intended to limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Implementation Method

[0013] The following detailed description of exemplary embodiments of this application refers to the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret it in a limiting manner, and the scope of the embodiments of this application is limited only to the appended claims.

[0014] In this application, unless otherwise expressly stated, the singular as used includes the plural. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the term "comprising" and other forms such as "including" and "containing" are not limiting. Furthermore, unless otherwise expressly stated, terms such as "element" or "component" cover elements and components comprising one unit, as well as elements and components comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0015] As used herein, spatially relative terms, such as “below,” “under,” “above,” “over,” “upper,” “upper side,” “lower side,” “left side,” “right side,” “vertical,” “horizontal,” “side,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the accompanying figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0016] FIG1 is a cross-sectional view showing a system-in-package (SiP) device 100, in which a conformal EMI shielding layer 140 is formed to prevent electromagnetic noise radiated by high-frequency devices. As shown in FIG1, the device 100 includes a substrate 110 and a plurality of electronic components 122, 124 and 126 mounted thereon. The plurality of electronic components 122, 124 and 126 may include high-speed digital and RF electronics that may radiate electromagnetic noise to the outside. A sealant 130 is formed on the substrate 110 and seals the electronic components 122, 124 and 126. The EMI shielding layer 140 is formed on the sealant 130 and coupled to a reference node or potential (e.g., ground) to prevent electromagnetic waves generated in the device 100 from leaking to the outside and also to prevent external electromagnetic waves from entering the device 100.

[0017] However, since the EMI shielding layer 140 can form a closed-loop circuit with the ground point, an EMI loop current IEMI may be generated and may flow in the EMI shielding layer 140. The EMI loop current IEMI will further induce electromagnetic fields in its adjacent electronic components, which may cause undesirable interference to the adjacent electronic components.

[0018] To address the above-mentioned problems, one aspect of this application provides a method for manufacturing a semiconductor device. In this method, a shielding layer is selectively formed between a conformal shielding layer and an electronic component to further reduce EMI in the SiP device. The combination of the selective shielding layer and the external conformal shielding layer can significantly reduce EMI or other interference in the SiP. Furthermore, in this method, a reference mark is first formed on a sealant above the electronic component, and then the selective shielding layer is formed directly relative to the reference mark using an aerosol jetting apparatus. Since no photolithography or etching process is used, the method of this application is simple and cost-effective.

[0019] Referring to Figures 2A and 2B to 5A and 5B and Figures 6 to 9, perspective views and cross-sectional views illustrating the various steps of a method for manufacturing a semiconductor device are shown. The method will now be described in more detail with reference to the accompanying drawings.

[0020] Referring to Figures 2A and 2B, a package strip 200 is provided. Figure 2A shows a perspective view of the package strip 200, and Figure 2B is a cross-sectional view of the package strip 200 along section lines A1-A2 shown in Figure 2A.

[0021] Specifically, the encapsulation strip 200 includes a substrate 210 having a top surface 210a and a bottom surface 210b. The substrate 210 can provide support and connection for electronic components and devices. For example, the substrate 210 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, or a ceramic substrate. However, the substrate 210 is not limited to these examples. In other examples, the substrate 210 may include a laminated interposer, a strip interposer, a lead frame, or other suitable substrate. The substrate 210 may include any structure on or in which an integrated circuit system can be fabricated. For example, the substrate 210 may include one or more insulating or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed on or between the insulating layers. In the example shown in FIG. 2B, the substrate 210 may include a redistribution structure (RDS) 215 having one or more dielectric layers and one or more conductive layers located between and through the dielectric layers. The conductive layer can define pads, traces, and plugs through which electrical signals or voltages can be distributed horizontally and vertically on the RDS. The RDS 215 can include one or more of Al, Cu, Sn, Ni, Au, Ag, or any other suitable conductive material. It is understood that the RDS 215 can be implemented in various structures and types, but aspects of this application are not limited to the examples described above.

[0022] In the examples shown in Figures 2A and 2B, the package strip 200 may include a plurality of undivided packages 202. The packages 202 may be predefined and separated by a plurality of dividing channels 204. The dividing channels 204 may provide cutting regions to divide the package strip 200 into individual semiconductor packages. However, the scope of this application is not limited to the examples shown in Figures 2A and 2B. In some other embodiments, the package strip 200 may include different packages.

[0023] In each package 202 shown in FIG. 2B, multiple electronic components 222 and 224 may be mounted on the top surface 210a of the substrate 210. Electronic components 222 and 224 may include any of a variety of semiconductor dies, semiconductor packages, or discrete devices. For example, electronic components 222 and 224 may include digital signal processors (DSPs), microcontrollers, microprocessors, network processors, power management processors, audio processors, video processors, RF circuits, wireless baseband system-on-a-chip (SoC) processors, sensors, memory controllers, memory devices, application-specific integrated circuits, etc. Electronic components 222 and 224 may include one or more passive electronic components, such as resistors, capacitors, inductors, etc. Electronic components 222 and 224 may be mounted on the top surface 210a of the substrate using any suitable surface mount technology.

[0024] In this application, electronic component 222 may include devices or circuits susceptible to or generating electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, and inter-device interference. In some cases, electronic component 222 may include any element configured to provide several mobility functions and capabilities, including but not limited to positioning functions, wireless connectivity functions (e.g., wireless communication), and / or cellular connectivity functions (e.g., cellular communication). In some cases, electronic component 222 may be configured to provide radio frequency front-end (RFFE) functionality. For example, electronic component 222 may include, but is not limited to, power amplifiers, filters, switches, low-noise amplifiers (LNAs), tuners, multiplexers, etc. In FIG2B, electronic component 222 is shown as a semiconductor die. Semiconductor die 222 is formed and mounted in a flip-chip type such that conductive bumps of semiconductor die 222 are soldered to some RDS 215 in substrate 210. In other embodiments, electronic component 222 may include bonding pads and may be connected to RDS 215 by wire bonding. This application does not limit the connection relationship between electronic component 222 and RDS 215 to the above disclosure.

[0025] A first sealant 230 is formed on the top surface 210a of the substrate 210 and seals electronic components 222 and 224. The first sealant 230 may be made of a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with suitable fillers, but the scope of this application is not limited thereto. The first sealant 230 is non-conductive, provides structural support, and environmentally protects electronic components 222 and 224 from external components and contaminants.

[0026] Referring to Figures 3A and 3B, a reference mark 206 is formed in the first sealant 230. Figure 3A is a perspective view of the encapsulation strip after the reference mark 206 has been formed, and Figure 3B is a cross-sectional view of the encapsulation strip along section lines A1-A2 shown in Figure 3A.

[0027] In some embodiments, a saw blade 282 may be used to form the reference mark 206. In some embodiments, a laser cutting tool or an etching process may be used to form the reference mark 206. In some embodiments, after the reference mark 206 is formed, a cleaning process for removing residues may be further performed.

[0028] In the examples shown in Figures 3A and 3B, the reference mark 206 may include a plurality of grooves, each groove having a V-shaped cross-section and aligned vertically with a corresponding dividing channel 204. In some embodiments, the grooves may have a depth ranging from 5% to 80% of the thickness of the first sealant 230. It is understood that the shape and / or location of the reference marks shown in Figures 3A and 3B are for illustrative purposes only and not for limitation. In some other embodiments, the grooves may be formed in other peripheral areas of the encapsulation strip, or the grooves may have a U-shaped cross-section, a cap-shaped cross-section, a Y-shaped cross-section, a rectangular cross-section, a trapezoidal cross-section, or other polygonal cross-section, as long as they can be identified by an inspection tool such as an optical microscope, as will be described in detail below. The location of the reference mark 206 may be determined with reference to the dividing channel. In some other embodiments, more than one reference mark 206 may be formed on the surface of the first sealant 230.

[0029] Referring to Figures 4A and 4B, the visual inspection device 284 is used to inspect the package to determine the position of the reference mark 206 and the distance between the reference mark 206 and the electronic component 222. Figure 4A is a perspective view of the package strip, and Figure 4B is a cross-sectional view of the package strip along section lines A1-A2 shown in Figure 4A. The visual inspection device 284 may include an optical microscope, an electron microscope, or an X-ray microscope, but this application is not limited thereto.

[0030] In some embodiments, as shown in FIG4B, electronic component 222 may include a proximal end and a distal end relative to reference mark 206. Visual inspection device 284 may be used to determine a distance D1 between the proximal end of electronic component 222 and reference mark 206, and another distance D2 between the distal end of electronic component 222 and reference mark 206. These two distances D1 and D2 may be used to determine the location of a selective shielding layer formed over electronic component 222 in subsequent processes.

[0031] In some embodiments, the visual inspection device 284 may capture an image of the top surface of the first sealant 230, and then the visual inspection device 284 or an external controller may execute an image recognition algorithm to automatically detect and identify the electronic components 222, the reference mark 206, and / or the positional relationships between them.

[0032] Referring to Figures 5A and 5B, an aerosol spraying device 286 is used to form a first shielding layer 250 on the first sealant 230. Figure 5A is a perspective view of the encapsulation strip after the formation of the first shielding layer 250, and Figure 5B is a cross-sectional view of the encapsulation strip along the section lines A1-A2 shown in Figure 5A.

[0033] In some embodiments, the aerosol jetting device 286 can atomize conductive ink (e.g., silver-based conductive ink, etc.) using ultrasonic or pneumatic methods to generate droplets with diameters ranging from one to several micrometers. The droplets can be entrained in an airflow and delivered to the printhead. At the printhead, another airflow can be introduced to focus the droplets into a tightly collimated bundle of material. The combined airflow can then exit the printhead through a converging nozzle that compresses the aerosol stream into particles or droplets with small diameters. The droplet jet can then exit the printhead at high speed and impact the first sealant 230. Thus, at least a portion of the top surface aligned with the nozzle can be deposited with a shielding material. Furthermore, the first shielding layer 250 can be formed by moving the printhead and continuously distributing droplets. In some embodiments, the aerosol jetting device 286 may also include a controller (e.g., a microcontroller unit) for controlling its operation. For example, the controller can control the movement of the printhead and / or the timing of the droplet jet distribution based on the position of the reference mark 206 and the distance between the reference mark 206 and the electronic component 222. In some embodiments, the first shielding layer 250 can be post-processed (e.g., post-heating process) to achieve its final electrical and mechanical properties.

[0034] In some embodiments, the aerosol jetting apparatus may include multiple printheads. Therefore, multiple printheads can operate simultaneously over the encapsulation strip to form multiple first shielding layers over their respective semiconductor devices, thereby increasing the productivity of the aerosol jetting apparatus.

[0035] Referring again to FIG5B, the first shielding layer 250 is formed at a predetermined distance from the reference mark 206 and above the electronic component 222, which may be susceptible to or generate EMI, RFI, etc. It can be seen that the projection of the first shielding layer 250 onto the top surface of the substrate 210 overlaps with the electronic component 222 and preferably covers the entire electronic component 222. Therefore, the first shielding layer 250 can shield against EMI or other interference induced to (or generated by) the electronic component 222.

[0036] Furthermore, since the aerosol jetting device 286 can easily and accurately control the position and / or distribution time of the droplet jet based on the position of the reference mark 206, the first shielding layer 250 can be directly formed at the desired region and have the desired shape without any mask, any photolithography process, or any etching process. Therefore, compared with methods that use laser ablation, sputtering, and polishing processes to form a selective shielding layer, the method of this application is simple and cost-effective.

[0037] However, the scope of this application is not limited to the embodiments described above. In some other embodiments, the first shielding layer may be dispensed, sprayed, or printed onto the first sealant by jet printing, laser printing, pneumatic or any other metal deposition process, as long as the metal deposition process can directly form the first shielding layer with the desired shape at the desired area.

[0038] Subsequently, as shown in FIG. 6, a second sealant 260 is formed on the first sealant 230 and the first shielding layer 250. For example, solder paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable processes can be used to form the second sealant 260 on the first sealant 230 and the first shielding layer 250. The second sealant 260 may be made of a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with suitable fillers, but the scope of this application is not limited thereto. For example, the second sealant 260 may comprise an epoxy molding compound filled with one or more high-k dielectric materials. High-k fillers can improve the thermal conductivity of the second sealant 260.

[0039] Subsequently, as shown in FIG7, each package 202 is separated from the package strip along its respective dividing channel 204. For example, as shown in FIG7, a saw blade 288 can be used to divide the package strip into individual devices through the dividing channel 204. In some other examples, a laser cutting tool can also be used to divide the package strip.

[0040] Subsequently, as shown in FIG8, a second shielding layer 270 is formed to cover the semiconductor device. The second shielding layer 270 may be made of the same or different material as the first shielding layer 250, and may be formed by spraying, electroplating, sputtering or any other suitable metal deposition process.

[0041] The second shielding layer 270 may be a conformal shield, conforming to the shape and / or contour of the second sealant 260, the first sealant 230, and the substrate 210. That is, the second shielding layer 270 covers the top and side surfaces of the second sealant 260, the side surface of the first sealant 230, and the side surface of the substrate 210. Therefore, the combination of the first shielding layer 250 and the second shielding layer 270 can significantly reduce EMI or other interference in semiconductor devices.

[0042] In the example shown in FIG8, the second shielding layer 270 may not be connected to the first shielding layer 250 below it because the first shielding layer 250 is formed outside the split channel. However, the present application is not limited thereto. In another example shown in FIG9, the first shielding layer 250' may be formed at the split channel. Therefore, after the splitting process, a portion of the side surface of the first shielding layer 250' may be exposed from the second sealant 260, and the second shielding layer 270' may cover the exposed portion of the side surface of the first shielding layer 250', thereby making electrical contact with the first shielding layer 250'.

[0043] Although the process for manufacturing semiconductor devices has been described in conjunction with the accompanying drawings, those skilled in the art will understand that modifications and adjustments can be made to the process without departing from the scope of the invention.

[0044] According to another aspect of this application, a semiconductor device is provided. Referring to FIG10, a cross-sectional view of a semiconductor device 900 according to an embodiment of this application is shown.

[0045] As shown in FIG. 10, the semiconductor device 900 includes a substrate 910, an electronic component 922, a first sealant 930, a reference mark 906, and a first shielding layer 950. The substrate 910 may have a top surface 910a and a bottom surface 910b. The electronic component 922 is mounted on the top surface 910a of the substrate 910 and may be susceptible to or generate electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, and inter-device interference. The first sealant 930 is disposed on the surface 910a of the substrate 910 and seals the electronic component 922. The reference mark 906 is formed in the first sealant 930. The first shielding layer 950 is formed on the first sealant 930, and the first shielding layer 950 is located at a predetermined distance from the reference mark 906 and above the electronic component 922.

[0046] In some embodiments, the projection of the first shielding layer 950 onto the top surface 910a of the substrate 910 can cover the electronic component 922, so the first shielding layer 950 can shield against EMI or other interference induced to (or generated by) the electronic component 922.

[0047] In some embodiments, the reference mark 906 may include a groove formed in the first sealant 930 at the dividing channel 904 of the substrate 910. The dividing channel 904 may provide a cutting area to divide the substrate 910 into individual semiconductor devices 902.

[0048] In some embodiments, as shown in FIG10, a second sealant 960 is formed on the first sealant 930 and covers the reference mark 906 and the first shielding layer 950. In some embodiments, the second sealant 960 may comprise an epoxy molding compound filled with one or more high-k dielectric materials. The high-k filler can improve the thermal conductivity of the second sealant 960.

[0049] In some other embodiments, the semiconductor device 900 may have a structure and configuration similar to the package shown in FIG. 6, and be manufactured by the method embodiments described above. Therefore, further details of the semiconductor device 900 can be found in the method embodiments described above, and will not be repeated here.

[0050] This discussion includes numerous illustrative drawings that illustrate various parts of a semiconductor device and methods of manufacturing said semiconductor device. For clarity, these drawings do not show all aspects of each example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein. It will be understood that embodiments described in the context of one component or method are similarly effective for other components or methods. Similarly, embodiments described in the context of a component are similarly effective for a method, and vice versa. Features described in the context of an embodiment may be adapted accordingly to the same or similar features in other embodiments. Features described in the context of an embodiment may be adapted accordingly to other embodiments, even if not explicitly described in those other embodiments. Furthermore, additions and / or combinations and / or substitutions described for features in the context of an embodiment may be adapted accordingly to the same or similar features in other embodiments.

[0051] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the embodiments in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended list of exemplary claims. [Simplified Explanation of the Diagram]

[0008] The accompanying drawings referenced herein form part of the specification. Unless otherwise expressly stated in the detailed description, the features shown in the drawings illustrate only some embodiments of this application and not all embodiments of this application, and the reader of the specification should not imply the contrary.

[0009] Figure 1 is a cross-sectional view of a system-in-package (SiP) device.

[0010] Figures 2A and 2B to 5A and 5B and Figures 6 to 9 are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device according to embodiments of the present application.

[0011] FIG10 is a cross-sectional view of a semiconductor device according to an embodiment of the present application.

[0012] The same reference numerals will be used throughout the accompanying drawings to denote the same or similar parts.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A package is provided, the package comprising: a substrate including a top surface and a bottom surface; an electronic component mounted on the top surface of the substrate; and a first sealant disposed on the top surface of the substrate and sealing the electronic component; a reference mark formed in the first sealant; and a first shielding layer formed on the first sealant at a predetermined distance from the reference mark using an aerosol spraying device, wherein the first shielding layer is located above the electronic component.

2. The method according to request item 1, wherein, Forming the reference mark in the first sealant includes: forming a groove in the first sealant at the segmentation channel of the package.

3. The method according to request item 2, wherein, Forming the groove in the first sealant includes: forming the groove in the first sealant using a saw blade or laser cutting tool.

4. The method according to request item 1, wherein, Forming the first shielding layer on the first sealant using the aerosol spraying device includes: inspecting the package to determine the position of the reference mark and the distance between the reference mark and the electronic component; and controlling the aerosol spraying device to form the first shielding layer based on the position of the reference mark and the distance between the reference mark and the electronic component.

5. The method according to request item 1, wherein, The projection of the first shielding layer onto the top surface of the substrate covers the electronic components.

6. The method according to request item 1, wherein, The method further includes: forming a second sealant on the first sealant to cover the reference mark and the first shielding layer; separating the semiconductor device from the package along a dividing channel of the package; and forming a second shielding layer to cover the semiconductor device.

7. The method according to request item 6, wherein, The second shielding layer conforms to the shape of the semiconductor device.

8. The method according to claim 6, wherein, The second sealant comprises an epoxy molding compound filled with one or more high-k dielectric materials.

9. A semiconductor device, the semiconductor device comprising: A substrate, the substrate comprising a top surface and a bottom surface; An electronic component is mounted on the top surface of the substrate; A first sealant is disposed on the top surface of the substrate and seals the electronic components; A reference mark, said reference mark being formed in the first sealant; A first shielding layer is formed on the first sealant at a predetermined distance from the reference mark using an aerosol spraying device, wherein the first shielding layer is located above the electronic component.

10. The semiconductor device according to claim 9, wherein, The reference mark includes a groove formed in the first sealant at the segmented channel of the substrate.

11. The semiconductor device according to claim 9, wherein, The projection of the first shielding layer onto the top surface of the substrate covers the electronic components.

12. The semiconductor device according to claim 9, wherein, The semiconductor device further includes: a second sealant formed on the first sealant and covering the reference mark and the first shielding layer.

13. The semiconductor device according to claim 12, wherein, The second sealant comprises an epoxy molding compound filled with one or more high-k dielectric materials.

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