Dual-gate thin film transistor

Abstract

A dual-gate thin-film transistor is disclosed to address the problem of decreased drive current caused by parasitic resistance in the lightly doped region of conventional thin-film transistors. The transistor comprises a substrate, stacked with a lower gate, a lower gate insulating layer, a channel layer, an upper gate insulating layer, an upper gate, and an inner dielectric layer. The channel layer has a source and a drain at its two ends, respectively, and a lightly doped drain region is formed in the region of the channel layer near the drain. The upper gate region is divided into a lower first upper gate and an upper second upper gate, the second upper gate having an elongated section extending towards the drain. This achieves the effect of increasing drive current and reducing leakage current.

Claims

1. A dual-gate thin-film transistor, comprising: a substrate; a lower gate disposed on the substrate; a lower gate insulating layer stacked on the lower gate; a channel layer stacked on the lower gate insulating layer, the two ends of the channel layer being a source and a drain, respectively, and a lightly doped drain region being formed in the region of the channel layer near the drain; an upper gate insulating layer stacked on the channel layer; an upper gate stacked on the upper gate insulating layer, the upper gate region being divided into a lower first upper gate and an upper second upper gate, the second upper gate having an elongated section extending toward the drain; an inner dielectric layer stacked on the upper gate insulating layer and covering most of the upper gate; a source metal layer disposed on the inner dielectric layer and aligned with the source; and a drain metal layer disposed on the inner dielectric layer and aligned with the drain.

2. As in claim 1, a dual-gate thin-film transistor, wherein, The doping concentration range of this lightly doped drain region is 1 x 10¹⁷ cm⁻³ to 5 x 10¹⁸ cm⁻³.

3. As in claim 1, a dual-gate thin-film transistor, wherein, The length of the elongated section is 15% to 70% of the length of the first upper gate.

4. As in claim 1, a dual-gate thin-film transistor, wherein, The first upper gate and the second upper gate are flush at the end near the source.

5. As in claim 1, a dual-gate thin-film transistor, wherein, The thickness of the first upper gate is 45% to 100% of the thickness of the upper gate insulation layer.

6. As in claim 1, a dual-gate thin-film transistor, wherein, The materials of the lower gate, the upper gate, the source metal layer, and the drain metal layer are molybdenum, aluminum, titanium, titanium nitride, or heavily doped polycrystalline silicon.

7. As in claim 1, a dual-gate thin-film transistor, wherein, The materials of the lower gate insulation layer and the upper gate insulation layer are silicon oxide, silicon nitride, aluminum oxide or hafnium oxide.

8. As in claim 1, a dual-gate thin-film transistor, wherein, The material of the inner dielectric layer is silicon oxide, silicon nitride, aluminum oxide, titanium oxide, or hafnium oxide.

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