Decoder unit and receiver using the decoder unit

Abstract

In the decoder unit, when the switching circuit is in the ON state, the data signal to be decoded is allowed to pass through and used as a sampled data signal; when the switching circuit is in the OFF state, the data signal to be decoded is blocked from passing through. The decoder circuit receives an intermediate data signal, which has a ratio equal to the sum of the voltage value of the sampled data signal and the voltage value of the first reference voltage. Based on the first reference voltage and a selection signal, the decoder performs an analog-to-logarithmic conversion on the intermediate data signal to generate a first-part decoded signal comprising three bits, which, depending on the selection signal, determines whether it is a differentially linear intermediate data signal or a differentially nonlinear intermediate data signal. The decoder then compares the intermediate data signal with a second reference voltage to generate a second-part decoded signal comprising one bit.

Claims

1. A decoder unit, comprising: a switching circuit that receives a data signal to be decoded, the switching circuit operating between an on state and a off state; when the switching circuit is operating in the on state, the switching circuit allows the data signal to be decoded to pass through and serves as a sampled data signal; when the switching circuit is operating in the off state, the switching circuit blocks the data signal to be decoded from passing through; and a decoder circuit electrically connected to the switching circuit, for receiving the sampled data signal, a first reference voltage, a second reference voltage, and a selection signal; the decoder circuit, based on the first reference voltage, the second reference voltage, and the selection signal, decodes the sampled data signal into a four-bit decoded signal. The decoder circuit receives an intermediate data signal having a sum of voltage values ​​equal to the sum of the voltage values ​​of the sampled data signal and the voltage values ​​of the first reference voltage. The decoder circuit performs an analog-to-digital conversion on the intermediate data signal based on the first reference voltage and the selection signal, and generates a first partial decoded signal including three bits. The first partial decoded signal determines whether it is a differentially linear intermediate data signal or a differentially nonlinear intermediate data signal by depending on the selection signal. The decoder circuit compares the intermediate data signal with the second reference voltage and generates a second partial decoded signal including one bit.

2. The decoder unit as described in claim 1, wherein, The proportion of the voltage value of the first reference voltage is one-eighth of the voltage value of the first reference voltage.

3. The decoder unit as described in claim 1, wherein, When the selection signal is at a first logic value, the voltage value of the second reference voltage is equal to the voltage value of the first reference voltage, and the first part of the decoded signal is the intermediate data signal with differential linearity. When the selection signal is at a second logic value, the voltage value of the second reference voltage is equal to one-eighth of the voltage value of the first reference voltage, and the first part of the decoded signal is the intermediate data signal with differential nonlinearity.

4. The decoder unit as described in claim 1, wherein, When the selection signal is at a first logic value, the voltage value of the first reference voltage is equal to twice the voltage value of the first reference voltage when the selection signal is at a second logic value.

5. The decoder unit as described in claim 1, wherein, The data signal to be decoded is represented by a first input voltage and a second input voltage. The decoder circuit includes: a conversion circuit, which includes a first capacitor group, which includes a first common node and five first capacitors. Each first capacitor has a first terminal and a second terminal. The first common node is electrically connected to the first terminals of the first capacitors and is further electrically connected to the switching circuit. The first terminal of each first capacitor is used to receive the first input voltage. Each first capacitor outputs a first comparison voltage at the first common node. When the switching circuit is in the on state, the first comparison voltage is equal to the first input voltage. When the switching circuit is in the off state, the first comparison voltage changes with the voltage value of the second terminal of each first capacitor. A second capacitor group includes a second common node and four second capacitors, each of the second capacitors having a first terminal and a second terminal. The second common node is electrically connected to the first terminal of each of the second capacitors and is further electrically connected to the switching circuit. The second common node is used to receive the second input voltage. Each of the second capacitors outputs a second comparison voltage at the second common node. When the switching circuit is operated in the on state, the second comparison voltage is equal to the second input voltage. When the switching circuit is operated in the off state, the second comparison voltage changes with the voltage values ​​of the second terminals of the second capacitors. A comparator circuit electrically connected to the first common node and the second common node, for receiving the first comparison voltage and the second comparison voltage, and further receiving the second reference voltage, and comparing the first comparison voltage and the second comparison voltage to generate a first comparison output, the first comparison output including a three-bit first comparison signal and a three-bit second comparison signal, and comparing the difference between the first comparison voltage and the second comparison voltage with the second reference voltage to generate a second comparison output, the second comparison output including a one-bit third comparison signal and a one-bit fourth comparison signal; a register electrically connected to the comparator circuit, for receiving the first comparison output and the second comparison output, and generating the decoding signal based on the first comparison output and the second comparison output;The controller is electrically connected to the comparator circuit to receive the first comparator output. The controller is further electrically connected to the second terminals of the first capacitors from the first to the third, and to the second terminals of the second capacitors from the first to the third. The controller further receives the first reference voltage and the selection signal. The controller is configured to selectively provide either the first reference voltage or a ground voltage to the second terminals of the first capacitors from the first to the third, and to the second terminals of the second capacitors from the first to the third, based on the first comparator output and the selection signal. When the selection signal is at a first logic value and the two most significant bits of the first comparison signal are logic values ​​"00", the controller selectively transmits either the first reference voltage or the ground voltage to the second terminal of the first capacitor and the second terminal of the second capacitor in the first capacitor, and also selectively transmits either the first reference voltage or the ground voltage to the second terminal of the second capacitor and the second terminal of the first capacitor in the second capacitor. Conversely, when the controller selectively transmits either the first reference voltage or the ground voltage to the second terminals of both the first and second capacitors, it also selectively transmits either the first reference voltage or the ground voltage to the second terminals of both the first and second capacitors in the second capacitor. The second terminal of the fourth capacitor in the first capacitor is used to receive the ground voltage. The second terminal of the fourth capacitor in the second capacitor is used to receive the ground voltage. When the switching circuit operates in the on state, the second terminal of the fifth capacitor in the first capacitor is used to receive the ground voltage. When the switching circuit operates in the off state... The second terminal of the fifth of the first capacitors is used to receive the first reference voltage.

6. The decoder unit as described in claim 5, wherein, The capacitance ratio of the first capacitor to the fifth capacitor is 1:3:8:2:2, and the capacitance ratio of the second capacitor to the fourth capacitor is 1:3:8:2:

2.

7. The decoder unit as described in claim 5, wherein, The controller includes: a first switch group comprising three first switches, each first switch having a first terminal, a second terminal, and a third terminal, the first terminal being electrically connected to the second terminal of each of the first capacitors from the first to the third, the second terminal being used to receive the first reference voltage, and the third terminal being used to receive the ground voltage; and a second switch group comprising three second switches, each second switch having a first terminal, a second terminal, and a third terminal, the first terminal being electrically connected to the second terminal of each of the second capacitors from the first to the third, the second terminal being used to receive the first reference voltage, and the third terminal being used to receive the ground voltage. Each first switch and each second switch operates between a first state and a second state. When each first switch and each second switch is operating in the first state, the first terminal of each first switch and each second switch is electrically connected to each of the first capacitors. A switch and the second terminal of each of the second switches (switched to ON), when each of the first switches and each of the second switches is operated in the second state, the first terminal of each of the first switches and each of the second switches is electrically connected to the third terminal of each of the first switches and each of the second switches (switched to ON); and a control logic, the control logic being electrically connected to the comparison circuit, and the control logic being used to receive the two most significant bits of the first comparison signal and the two most significant bits of the second comparison signal, and the control logic being further electrically connected to the first switches and the second switches to receive the selection signal, the control logic controlling the first switches and the second switches to switch between the first state and the second state based on the two most significant bits of the first comparison signal, the two most significant bits of the second comparison signal and the two most significant bits of the selection signal.

8. The decoder unit as described in claim 5, wherein, The comparison circuit includes: three first comparators, each of which is electrically connected to the first common node and the second common node, for receiving the first comparison voltage and the second comparison voltage, and each of the first comparators operates between an enabled mode and a disabled mode. When each of the first comparators operates in the enabled mode, each of the first comparators performs a comparison based on the first comparison voltage and the second comparison voltage, and generates a first comparison signal and a second comparison signal corresponding to one bit. When each of the first comparators operates in the disabled mode, each of the first comparators does not perform a comparison operation. A second comparator electrically connected to the first common node and the second common node, for receiving the first comparison voltage, the second comparison voltage, and the second reference voltage, the second comparator operating between an enabled mode and a disabled mode; when operating in the enabled mode, the second comparator performs a comparison based on the difference between the first comparison voltage and the second comparison voltage and the second reference voltage, and generates the third comparison signal and the second comparison signal; when operating in the disabled mode, the second comparator does not perform the comparison operation; and a timing generator electrically connected to the first comparator and the second comparator, the timing generator receiving the two most significant bits of the first comparison signal and the two most significant bits of the second comparison signal generated by the first comparator, and receiving the third comparison signal and the fourth comparison signal generated by the second comparator; The timing generator further receives a clock signal, and the timing generator controls the first comparator and the second comparator to switch between the enabled mode and the disabled mode based on the two most significant bits of the first comparison signal, the two most significant bits of the second comparison signal, the third comparison signal, the fourth comparison signal, and the clock signal.

9. The decoder unit as described in claim 5, wherein, The switching circuit includes a first sampling switch and a second sampling switch. The first sampling switch has a first terminal for receiving the first input voltage and a second terminal electrically connected to the first common node. The second sampling switch has a first terminal for receiving the second input voltage and a second terminal electrically connected to the second common node. The first sampling switch and the second sampling switch are each used to receive a clock signal. The first sampling switch and the second sampling switch operate in a conducting state and a non-conducting state according to the clock signal. When the first sampling switch operates in the conducting state and the second sampling switch operates in the conducting state, the switching circuit operates in the conducting state. When the first sampling switch operates in the non-conducting state and the second sampling switch operates in the non-conducting state, the switching circuit operates in the non-conducting state.

10. The decoder unit as described in claim 5, wherein, The first capacitor bank also includes a switch having a first terminal electrically connected to the second terminal of the fifth of the first capacitors, a second terminal for receiving the first reference voltage, and a third terminal for receiving the ground voltage. The switch operates between a first state and a second state. When the switch operates in the first state, the first terminal and the second terminal of the switch are electrically connected, and the switch circuit operates in a non-conducting state. When the switch operates in the second state, the first terminal and the third terminal of the switch are electrically connected, and the switch circuit operates in a conducting state.

11. A receiver, comprising: a decoder unit, including: a switching circuit that receives a data signal to be decoded, the switching circuit operating between an on state and a non-conducting state, wherein when the switching circuit is operating in the on state, the switching circuit allows the data signal to be decoded to pass through and serves as a sampled data signal, and when the switching circuit is operating in the non-conducting state, the switching circuit blocks the data signal to be decoded from passing through; a decoder circuit electrically connected to the switching circuit, for receiving the sampled data signal, a first reference voltage, a second reference voltage, and a selection signal; the decoder circuit, based on the first reference voltage, the second reference voltage, and the selection signal, decodes the sampled data signal into a four-bit decoded signal, wherein... The decoder circuit receives an intermediate data signal having a sum of voltage values ​​equal to the ratio of the voltage value of the sampled data signal to the voltage value of the first reference voltage. Based on the first reference voltage and the selection signal, the decoder circuit performs an analog-to-digital conversion on the intermediate data signal and generates a first-part decoded signal comprising three bits. The first-part decoded signal is determined by the selection signal to be either a differentially linear intermediate data signal or a differentially nonlinear intermediate data signal. The decoder circuit also compares the intermediate data signal with the second reference voltage and generates a second-part decoded signal comprising one bit. A voltage regulator, electrically connected to the decoder circuit, generates the first reference voltage for the decoder circuit to receive. A digital-to-analog converter (DPC), electrically connected to the decoder circuit, is configured to generate the second reference voltage for reception by the decoder circuit. A processor, electrically connected to the voltage regulator and the DPC, is configured to receive a decoded output from the decoded signal, and to receive a selection signal. The processor is configured to convert the decoded output into a converted output and perform an adaptive calibration on the voltage regulator and the DPC to adjust the voltage values ​​of the first and second reference voltages. The converted output includes a first error portion and a second error portion. The processor generates the first error portion of the converted output based on the first and second decoded signals and the selection signal. The processor generates the second error portion of the converted output based on the second decoded signal. When the selection signal is at a first logic value, the processor performs the adaptive calibration on the voltage regulator and the DPC based on the first error portion of the converted output to adjust the voltage values ​​of the first and second reference voltages. When the selection signal is at a second logic value, the processor performs adaptive calibration on the voltage regulator based on the first error portion of the conversion output to adjust the voltage value of the first reference voltage; the processor performs adaptive calibration on the digital-to-analog converter based on the second error portion of the conversion output to adjust the voltage value of the second reference voltage.

12. The receiver as claimed in claim 11 further includes a phase interpolator electrically connected to the processor for receiving a clock input, performing a phase interpolation on the clock input, and generating a plurality of interpolated clock signals, one of the interpolated clock signals being a predetermined interpolated clock signal relating to the operation of the decoder unit. When the selection signal is at the first logic value, the processor performs the adaptive calibration on the phase interpolator based on the first error portion of the conversion output to adjust a phase offset of the predetermined interpolated clock signal relative to the clock input. When the selection signal is at the second logic value, the processor performs the adaptive calibration on the phase interpolator based on the second error portion of the conversion output to adjust a phase offset of the predetermined interpolated clock signal relative to the clock input.

13. The receiver as described in claim 11, wherein, When using 1+0.5 D pulse shaping, the selection signal is set to the first logic value. When using 1+D pulse shaping, the selection signal is set to the second logic value. When using 1+0.5 D pulse shaping, the data signal to be decoded comes from an input data signal, and the input data signal adopts a pulse amplitude modulation (PAM)-4 format and a pulse amplitude modulation (PAM)-10 format. Alternatively, when using 1+D pulse shaping, the data signal to be decoded comes from an input data signal, and the input data signal adopts a pulse amplitude modulation (PAM)-7 format.

14. A receiver, comprising: a decoder unit, including: A switching circuit is provided to receive a data signal to be decoded. The switching circuit operates between an on state and a off state. When the switching circuit is in the on state, it allows the data signal to be decoded to pass through and serves as a sampled data signal. When the switching circuit is in the off state, it blocks the data signal to be decoded from passing through. A decoder circuit is electrically connected to the switching circuit and is used to receive the sampled data signal, a first reference voltage, a second reference voltage, and a selection signal. The decoder circuit decodes the sampled data signal into a four-bit decoded signal based on the first reference voltage, the second reference voltage, and the selection signal. The decoder circuit also receives an intermediate data signal. The intermediate data signal has a voltage value equal to that of the sampled data signal, or the intermediate data signal, according to the selection signal, has a voltage value equal to the sum of the voltage values ​​of the sampled data signal and the voltage values ​​of the first reference voltage. The decoder circuit performs analog-to-digital conversion on the intermediate data signal based on the first reference voltage and the selection signal, and generates a first-part decoded signal including three bits. The first-part decoded signal is determined by the selection signal to be either a differentially linear intermediate data signal or a differentially nonlinear intermediate data signal. The decoder circuit compares the intermediate data signal with the second reference voltage and generates a second-part decoded signal including one bit. A voltage regulator is electrically connected to the decoder circuit and is used to generate the first reference voltage, which is received by the decoder circuit. A digital-to-analog converter is electrically connected to the decoder circuit and is used to generate the second reference voltage, which is received by the decoder circuit.A processor, electrically connected to the voltage regulator and the digital-to-analog converter, is configured to receive a decoded output and a selection signal from the decoded signal, decode the decoded output into a conversion output, and perform an adaptive calibration on the voltage regulator and the digital-to-analog converter to adjust the voltage values ​​of the first reference voltage and the second reference voltage. The conversion output includes a first error portion and a second error portion. The processor generates the first error portion of the conversion output based on the first portion of the decoded signal, and generates the second error portion of the conversion output based on the second portion of the decoded signal. When the selection signal is at a first logic value, the processor performs adaptive calibration on the voltage regulator and the digital-to-analog converter based on the first error portion of the conversion output to adjust the voltage values ​​of the first reference voltage and the second reference voltage. When the selection signal is at a second logic value, the processor performs adaptive calibration on the voltage regulator based on the first error portion of the conversion output to adjust the voltage value of the first reference voltage, and performs adaptive calibration on the digital-to-analog converter based on the second error portion of the conversion output to adjust the voltage value of the second reference voltage.

15. The receiver as claimed in claim 14 further includes a phase interpolator electrically connected to the processor for receiving a clock input, the phase interpolator performing a phase interpolation on the clock input to generate a plurality of interpolated clock signals, wherein... A predetermined interpolated clock signal relates to the operation of the decoder unit. When the selection signal is at the first logic value, the processor performs adaptive calibration on the phase interpolator based on the first error portion of the conversion output to adjust a phase offset of the predetermined interpolated clock signal relative to the clock input. When the selection signal is at the second logic value, the processor performs adaptive calibration on the phase interpolator based on the second error portion of the conversion output to adjust the phase offset of the predetermined interpolated clock signal relative to the clock input.

16. The receiver as described in claim 14, wherein, When using a 1+0.5 D pulse shaping, the selection signal is set to the first logic value, and when using a 1+D pulse shaping, the selection signal is set to the second logic value. When using a 1+0.5 D pulse shaping, the data signal to be decoded comes from an input data signal, which adopts a pulse amplitude modulation (PAM)-2 format and a pulse amplitude modulation (PAM)-4 format, or when using a 1+D pulse shaping, the input data signal adopts a pulse amplitude modulation (PAM)-3 format.

17. The receiver of request item 14, wherein, The proportion of the voltage value of the first reference voltage is one-eighth of the voltage value of the first reference voltage.

18. The receiver of request item 14, wherein, When the selection signal is at the first logic value, the voltage value of the second reference voltage is equal to the voltage value of the first reference voltage, and when the selection signal is at the second logic value, the voltage value of the second reference voltage is equal to one-eighth of the voltage value of the first reference voltage.

19. The receiver of request item 14, wherein, When the selection signal is at the first logic value, the voltage value of the intermediate data signal is equal to the voltage value of the sampled data signal, and the first part of the decoded signal is the differentially linear intermediate data signal. When the selection signal is at the second logic value, the voltage value of the intermediate data signal is equal to the sum of the ratio of the voltage value of the sampled data signal to the voltage value of the first reference voltage, and the first part of the decoded signal is the differentially nonlinear intermediate data signal.

20. The receiver of request item 14, wherein, The voltage value of the first reference voltage when the selection signal is at the first logic value is equal to twice the voltage value of the first reference voltage when the selection signal is at the second logic value.

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