Image signal processor

Abstract

An image signal processor includes a comparator circuit for processing image signals generated by a pixel array. The comparator circuit includes an image signal load transistor and a first driver transistor constructed by a first transistor configuration structure, other transistors constructed by a second transistor configuration structure, and a guard ring surrounding the first transistor configuration structure on a substrate. The second transistor configuration structure includes a gate electrode extension extending above a shallow trench isolation region.

Claims

1. An image signal processor (ISP) comprising a comparator circuit for processing a plurality of image signals generated by a pixel array, the comparator circuit comprising: an image signal load transistor constructed by a first transistor configuration structure, and a first driving transistor; a plurality of other transistors constructed by a second transistor configuration structure; and a guard ring located on a substrate and surrounding the first transistor configuration structure; wherein the first transistor configuration structure comprises: the substrate; a first gate dielectric layer located on the substrate; a first gate electrode located on the first gate dielectric layer; a first source / drain electrode located in the substrate and adjacent to the first gate dielectric layer; and a first gate contact located above the first gate electrode and electrically connected to the first gate electrode; wherein the second transistor configuration structure comprises: a second gate dielectric layer located on the substrate; and a second gate electrode located on the second gate dielectric layer; A second source / drain electrode is located within the substrate and adjacent to the second gate dielectric layer; a shallow trench isolation (STI) region surrounds the second source / drain electrode; a gate electrode extension extends above the shallow trench isolation region; and a second gate contact is located on the shallow trench isolation region and is directly electrically connected to the gate electrode extension.

2. The image signal processor as claimed in claim 1, wherein the comparator circuit further includes a second driving transistor, a first power load transistor, and a second power load transistor configured by the first transistor structure.

3. The image signal processor as claimed in claim 2, wherein the comparator circuit further includes a first select transistor, a reference signal transistor, and a second select transistor configured by the second transistor structure.

4. The image signal processor as described in claim 3, wherein the comparator circuit further includes a first input capacitor and a second input capacitor, each surrounded by a guard ring.

5. The image signal processor as described in claim 1 further includes a selection output circuit connected to the comparator circuit.

6. The image signal processor as claimed in claim 5, wherein the selection output circuit further includes a third driving transistor constructed from the first transistor configuration structure.

7. The image signal processor as described in claim 6, wherein the selected output circuit further includes a power supply load capacitor and a grounding capacitor, both of which are surrounded by the protection ring.

8. The image signal processor as claimed in claim 7 further includes an analog-to-digital converter (ADC) circuit, wherein the pixel array is electrically connected to the comparator circuit through the analog-to-digital converter circuit.

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