Display device

Abstract

The display device includes a power line and a driving transistor, multiple light-emitting elements each including a first electrode and a second electrode, a first planarization layer partially surrounding the side surfaces of the multiple light-emitting elements, a first connection electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor, a second connection electrode disposed on the first planarization layer, a passivation layer disposed on the first connection electrode and the second connection electrode, and a second planarization layer disposed on the passivation layer and configured to partially surround the side surfaces of the light-emitting elements, wherein the passivation layer exposes the end of the first connection electrode configured to surround a portion of the side surface of one of the light-emitting elements; wherein the second planarization layer covers the end of the first connection electrode.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device that minimizes or reduces short-circuit defects between connecting electrodes. Prior Technology

[0002] As display devices used in computer monitors, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require an independent light source.

[0003] The applications of display devices have diversified from computer monitors and televisions to personal mobile devices, and people are now researching display devices with a wide display area and reduced size and weight.

[0004] Furthermore, in recent years, display devices incorporating light-emitting diodes (LEDs) have garnered attention as next-generation display devices. Because LEDs are made of inorganic rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs can be quickly switched on and off, possess excellent luminous efficiency, high shock resistance, and high stability, and can display high-brightness images. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display device that minimizes or reduces the separation of reflective electrodes caused by moisture penetration.

[0006] Another objective of this disclosure is to provide a display device that reduces reflective electrode crystallization.

[0007] Another objective of this disclosure is to provide a display device in which the first connecting electrode and the first electrode of the light-emitting element can be autonomously aligned.

[0008] Another objective of this disclosure is to provide a display device in which the third connecting electrode and the second electrode of the light-emitting element can be autonomously aligned.

[0009] Another objective of this disclosure is to provide a display device that minimizes or reduces short-circuit defects between connecting electrodes.

[0010] Another objective of this disclosure is to provide a display device that reduces line resistance.

[0011] Another objective of this disclosure is to provide a display device that can detect defects in the light-emitting element regardless of whether the driving transistor is defective.

[0012] Another objective of this disclosure is to provide a display device that improves electrical connections by minimizing or reducing connection defects caused by residual film during the process.

[0013] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0014] A display device according to an example embodiment of the present invention includes: a substrate defining a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer and including the first electrode and the second electrode in the sub-pixels respectively; a first planarization layer disposed on the bonding layer and configured to partially surround a plurality of side surfaces of the light-emitting elements; a first connection electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connection electrode disposed on the first planarization layer, spaced apart from the first connection electrode and connected to the second reflective electrode; a passivation layer disposed on the first connection electrode and the second connection electrode; a second planarization layer disposed on the passivation layer and configured to partially surround the side surfaces of the light-emitting elements; and a third connection electrode disposed on the second planarization layer and configured to connect the second electrode and the power line. This passivation layer exposes the end of the first connection electrode, which is configured to surround a portion of the side surface of one of the light-emitting elements. A second planarization layer covers the end of the first connection electrode.

[0015] A display device according to another exemplary embodiment of the present invention includes: a substrate having a plurality of pixels, each comprising a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer and comprising a first electrode and a second electrode in the sub-pixels; a first planarization layer disposed on the bonding layer and configured to partially surround a plurality of side surfaces of the light-emitting elements; a first connection electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connection electrode disposed on the first planarization layer, spaced apart from the first connection electrode and connected to the second reflective electrode; a passivation layer disposed on the first connection electrode and the second connection electrode; a second planarization layer disposed on the passivation layer and having a height decreasing toward the light-emitting elements; and a third connection electrode disposed on the second planarization layer and configured to connect the second electrode and the power line. Therefore, short-circuit defects between connecting electrodes can be minimized or reduced.

[0016] Details of other exemplary embodiments are included in the detailed description and drawings.

[0017] According to an exemplary embodiment of this disclosure, a passivation layer is disposed on a connection electrode connected to a reflective electrode, which can minimize or reduce moisture penetration into the reflective electrode.

[0018] According to exemplary embodiments disclosed herein, reflective electrode separation due to moisture penetration can be minimized or reduced.

[0019] According to exemplary embodiments disclosed herein, the display device can reduce production energy consumption and improve display device lifespan by minimizing or reducing potential defects caused by line corrosion, thereby operating with low power consumption.

[0020] According to the exemplary embodiments disclosed herein, by performing an ashing process on the first planarization layer and the second planarization layer, the first connecting electrode and the third connecting electrode can be connected to the light-emitting elements through a self-aligning method without the need for an independent alignment process, thereby ensuring the transfer margin of the light-emitting elements.

[0021] According to an exemplary embodiment of the present disclosure, a passivation layer is disposed on the first connection electrode to separate the first connection electrode from the third connection electrode, thereby suppressing short-circuit defects between the first connection electrode and the third connection electrode.

[0022] According to an exemplary embodiment of the present invention, the second planarization layer flows back to the portion of the first connection electrode exposed through the passivation layer, thereby separating the first connection electrode and the third connection electrode, which can suppress short-circuit defects in the connection between the first connection electrode and the third connection electrode.

[0023] According to the exemplary embodiments disclosed herein, the illumination detection signal is applied to the light-emitting element without passing through the driving transistor, and the presence of defects in the light-emitting element can be detected regardless of whether the driving transistor has defects.

[0024] The effects of this disclosure are not limited to the examples above, and include various additional effects.

[0025] Other features and manners of this disclosure will be set forth in the following description, and some will be obvious from the description or may be learned by practicing the inventive concept provided herein. Other features and manners of the inventive concept may be realized and achieved by structures specifically pointed out in the written description, the claims and drawings or which may be derived therefrom.

[0026] It should be understood that the foregoing general description of this disclosure and the following detailed description are exemplary and intended to provide further explanation of the claimed disclosure. Simple Explanation of the Diagram

[0027] The accompanying drawings are included in this specification to provide a further understanding of the disclosure and form part of this specification. They illustrate various aspects of the disclosure and, together with the specification, serve to explain the various principles of the disclosure. In the drawings: Figure 1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure; Figure 2 is an enlarged top view of the pixels of a display device according to an exemplary embodiment of the present disclosure; Figure 3 is a cross-sectional schematic diagram along line III-III' in Figure 2; and Figures 4A to 4H are flowcharts of a method for manufacturing a display device according to an example embodiment of the present disclosure. Implementation

[0028] The advantages and features of this disclosure, and the methods for achieving such advantages and features, will become clear with reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various other forms. The following exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the content and scope of this disclosure.

[0029] The shapes, sizes, scales, angles, quantities, etc., illustrated in the figures for illustrating exemplary embodiments are merely examples, and this disclosure is not limited thereto. The same reference numerals throughout the document generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as "comprising," "having," and "consisting of" as used herein are generally intended to allow for the addition of other components, unless such terms are used in conjunction with more restrictive terms such as "only." Any reference to the singular may include the plural, and vice versa, unless explicitly stated otherwise.

[0030] Even if not explicitly stated, components should be interpreted as including a normal range of error.

[0031] When terms such as “above,” “over,” “below,” and “adjacent” are used to describe the positional relationship between two components, one or more components may be located between the two components unless such terms are used in conjunction with further restrictive terms such as “directly” or “immediately next.”

[0032] When an element or layer is described as being disposed "on" another element or layer, the other layer or element may be disposed directly on the other element or located between the two.

[0033] While terms such as "first" and "second" can be used to describe various components, these components are not limited by these terms. These terms are used to refer to a single component only, without relating to other components. Therefore, in the technical concepts disclosed herein, the first component mentioned below may be the second component, and vice versa.

[0034] Similar reference symbols are typically used throughout the text to denote similar elements.

[0035] For ease of description, the dimensions and thickness of each component shown in the figures are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0036] The features of the various embodiments disclosed herein may be partially or wholly coupled or combined with each other, and may be technically interlocked and operated in various ways, and these embodiments may be carried out independently or in combination with each other.

[0037] The display device according to an exemplary embodiment of the present disclosure will now be described in detail with reference to the drawings.

[0038] Figure 1 is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 1 only shows the display panel PN, gate driver GD, data driver DD, and timing controller TC among the various components of the display device 100.

[0039] Referring to FIG1, the display device 100 includes a display panel PN having a plurality of sub-pixels SP, a gate driver GD configured to provide various types of signals to the display panel PN, a timing controller TC configured to control the gate driver GD and the data driver DD, and the data driver DD.

[0040] The gate driver GD responds to multiple gate control signals provided by the timing controller TC, providing multiple scan signals to multiple scan lines SL. Figure 1 shows a single gate driver GD configured to be separated from one side of the display panel PN. However, the number and arrangement of gate drivers GD are not limited in this way.

[0041] The data driver DD responds to multiple data control signals provided by the timing controller TC, converting the image data input from the timing controller TC into a data voltage using a reference gamma voltage. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0042] The timing controller TC aligns externally input image data and provides the image data to the data driver DD. The timing controller TC can utilize externally input synchronization signals, namely dot clock signals, data enable signals, and horizontal / vertical synchronization signals, to generate gate control signals and data control signals. Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by providing the generated gate control signals and data control signals to them.

[0043] The display panel PN is configured to display an image to the user and includes multiple sub-pixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and each of the multiple sub-pixels SP is connected to both the scan lines SL and the data lines DL. Furthermore, although not shown in the diagram, the multiple sub-pixels SP can be connected to high-potential power lines, low-potential power lines, reference lines, etc., respectively.

[0044] The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA.

[0045] The display area AA is the area in the display device 100 where an image is displayed. The display area AA may include multiple sub-pixels SP that constitute multiple pixels PX, and circuitry configured to operate these sub-pixels SP. These sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP can constitute one pixel PX. Light-emitting elements, thin-film transistors for operating the light-emitting elements, etc., may be disposed in each of the multiple sub-pixels SP. The multiple light-emitting elements may be defined differently depending on the type of display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel, the light-emitting elements may be light-emitting diodes (LEDs) or micro LEDs.

[0046] The display area AA includes multiple signal lines for transmitting various signals to multiple sub-pixels SP. For example, these signal lines may include multiple data lines DL for providing data voltage to the multiple sub-pixels SP; and multiple scan lines SL for providing gate voltage to the multiple sub-pixels SP. These scan lines SL may extend in one direction within the display area AA and connect to the multiple sub-pixels SP. These data lines DL may extend in a direction different from this direction within the display area AA and connect to these sub-pixels SP. Furthermore, the display area AA may also include low-potential power lines, high-potential power lines, etc. However, this disclosure is not limited to these.

[0047] The non-display area NA can be defined as an area where no image is displayed, i.e., an area extending from the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driving integrated circuits such as gate driving integrated circuits and data driving integrated circuits. The non-display area NA may be located on the surface behind the display panel PN, i.e., on a surface where no sub-pixels SP are present. Alternatively, the non-display area NA may be omitted. However, this disclosure is not limited to the configuration shown in the figures.

[0048] Meanwhile, gate drivers (GD), data drivers (DD), and timing controllers (TC) can be connected to the display panel (PN) in various ways. For example, the gate driver (GD) can be mounted in the non-display area (NA) using a gate-in-panel (GIP) method, or between multiple sub-pixels (SP) using a gate-in-active area (GIA) method in the display area (AA). For example, the data driver (DD) and timing controller (TC) can be formed on separate flexible films and printed circuit boards, and electrically connected to the display panel (PN) by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area (NA) of the display panel (PN). When the gate driver (GD) is mounted using the GIP method and the data driver (DD) and timing controller (TC) transmit signals to the display panel (PN) through the pad electrodes in the non-display area (NA), ensuring that the area in the non-display area (NA) can accommodate the gate driver (GD) and pad electrodes can increase the bezel size.

[0049] Alternatively, by mounting the gate driver GD within the display area AA using the GIA method and connecting the signal lines on the front surface of the display panel PN to the side lines of the pad electrodes on the rear surface of the display panel PN to form a flexible film bonded to the printed circuit board on the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized or reduced. In other words, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN using the aforementioned method, a virtually bezel-less design can be achieved.

[0050] Figure 2 is an enlarged top view of a pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 3 is a cross-sectional schematic diagram along line III-III' in Figure 2. Figure 2 only shows the first reflective electrode RE1, the second reflective electrode RE2, the first connecting electrode CE1, the second connecting electrode CE2, and the light-emitting element LED among the plurality of components of the display device 100. Figure 3 is a cross-sectional schematic diagram showing a first sub-pixel including the first light-emitting element 120. The cross-section including the first sub-pixel of the first light-emitting element 120 is the same as the cross-section including the second sub-pixel of the second light-emitting element 130 and the cross-section including the third sub-pixel of the third light-emitting element 140.

[0051] First, referring to Figures 1 and 3, the display panel PN includes multiple pixels PX, and each pixel PX has multiple sub-pixels SP. Each of the multiple sub-pixels SP may include a light-emitting element LED and pixel circuitry and can emit light independently. A pixel PX may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, a pixel PX may include one first sub-pixel, one second sub-pixel, and one third sub-pixel. In this case, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel. However, this disclosure is not limited to this.

[0052] These light-emitting elements (LEDs) can be disposed in multiple sub-pixels (SPs). Specifically, these LEDs include a first light-emitting element 120, a second light-emitting element 130, and a third light-emitting element 140. The first light-emitting element 120 can be disposed in a first sub-pixel, the second light-emitting element 130 can be disposed in a second sub-pixel, and the third light-emitting element 140 can be disposed in a third sub-pixel. For example, the first light-emitting element 120 can be a red light-emitting element, the second light-emitting element 130 can be a green light-emitting element, and the third light-emitting element 140 can be a blue light-emitting element.

[0053] Referring to Figure 2, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 may have different shapes. For example, the planar shape of the first light-emitting element 120 may be circular, and the planar shape of each of the second light-emitting element 130 and the third light-emitting element 140 may be elliptical. In this case, the second light-emitting element 130 and the third light-emitting element 140 may have different elliptical shapes due to different sizes. Furthermore, the major axis directions of the second light-emitting element 130 and the third light-emitting element 140 may be the same. However, this disclosure is not limited to this.

[0054] Referring also to Figure 3, the first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126. Although not shown in the figures, the planar shape of the first semiconductor layer 121 of the first light-emitting element 120 may be circular, and the planar shape of the second semiconductor layer 123 may be semi-circular. The planar shape of the first electrode 124 may be elliptical. The second electrode 125 may have a semi-circular shape, similar to the top surface of the second semiconductor layer 123.

[0055] The second light-emitting element 130 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the figures, the planar shapes of the first semiconductor layer and the first electrode of the second light-emitting element 130 may be elliptical. In this case, the major axis direction of the first semiconductor layer may be configured differently from the major axis direction of the first electrode. For example, when the first semiconductor layer has an ellipse with its major axis in the horizontal direction, the first electrode may have an ellipse with its major axis in the vertical direction. For example, the first electrode may be disposed on the top surface of the first semiconductor layer and disposed at one end of the first semiconductor layer based on its major axis direction. The planar shape of each of the second semiconductor layer and the second electrode may be a cut-out ellipse.

[0056] The third light-emitting element 140 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. Although not shown in the figures, the planar shapes of the first semiconductor layer and the first electrode of the third light-emitting element 140 may be elliptical. Unlike the second light-emitting element, the major axis direction of the first semiconductor layer may be the same as the major axis direction of the first electrode in the third light-emitting element 140. For example, the first electrode may be disposed on the top surface of the first semiconductor layer and disposed at one end of the first semiconductor layer based on the major axis direction. The planar shape of each of the second semiconductor layer and the second electrode may be an obliterated ellipse.

[0057] In other words, in the display device 100 according to the embodiments of this disclosure, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 can have different shapes, thereby distinguishing multiple light-emitting elements LED. For example, during the self-assembly process of the light-emitting elements LED, the multiple light-emitting elements LED can be formed into different shapes so that the multiple light-emitting elements LED can self-assemble at positions corresponding to multiple sub-pixels SP respectively. However, the shapes of the multiple light-emitting elements LED are merely examples, and this disclosure is not limited thereto.

[0058] Meanwhile, referring to FIG2, in each of the plurality of pixels PX of the display panel PN of the display device 100 of the present embodiment, a first contact area CA1, a second contact area CA2 and an illumination detection area APA may be defined.

[0059] The first contact area CA1 and the second contact area CA2 can be the areas where the power line VDD and the third connecting electrode CE3 are electrically connected. For example, in the first contact area CA1, the third connecting electrode CE3 can be electrically connected to the power line through the second reflective electrode RE2 and the second connecting electrode CE2. In the second contact area CA2, the third connecting electrode CE3 extending from the first contact area CA1 can be additionally connected to the second connecting electrode CE2 extending from the first contact area CA1, so that the third connecting electrode CE3 can be electrically connected to the power line.

[0060] The illumination detection area (APA) can be an area for transmitting illumination detection signals to detect defects in the light-emitting element (LED). For example, in the illumination detection area (APA), the illumination detection pattern can transmit the illumination detection signal to multiple first electrodes of the LED through the first connection electrode CE1 without passing through the driving transistor DT. Therefore, the presence of defects in the LED can be detected regardless of whether the driving transistor DT is defective. Details related to the above configuration will be described with reference to Figure 3 in the following explanation.

[0061] Next, referring to Figure 3, in each of the plurality of sub-pixels SP of the display panel PN of the display device 100 of the present embodiment, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, a cover layer 115, a bonding layer 116, a first planarization layer 117a, a second planarization layer 117b, a dam 118, a third planarization layer 119, a driving transistor DT, a light-emitting element LED, a reflective electrode RE, a light-shielding layer LS, an auxiliary electrode LE, a first connecting electrode CE1, a second connecting electrode CE2, a third connecting electrode CE3, a capacitor Cst, an intermediate electrode TM, and an illumination detection pattern APP may be provided.

[0062] First, the substrate 110 is an assembly that supports the various constituent elements included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, or the like. In addition, the substrate 110 may contain plastics such as polymers and may be made of a flexible material.

[0063] A light-shielding layer LS can be disposed in each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light from entering the active layer ACT of the driving transistor DT from the underside of the substrate 110, which will be described below. The light-shielding layer LS can block light entering the active layer ACT of the driving transistor DT, thereby minimizing or reducing leakage current.

[0064] A buffer layer 111 may be disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited to this. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may be omitted. However, this disclosure is not limited to this.

[0065] The driving transistor DT can be disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0066] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon. However, this disclosure is not limited thereto.

[0067] Gate insulating layer 112 may be disposed on active layer ACT. Gate insulating layer 112 is an insulating layer used to insulate active layer ACT from gate electrode GE. Gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0068] The gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0069] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b may be disposed on the gate electrode GE. Contact holes are formed in the gate insulating layer 112, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b may be insulating layers for protecting components disposed beneath them, and each may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0070] The source electrode SE and drain electrode DE, electrically connected to the active layer ACT, can be disposed on the second interlayer insulating layer 113b. The source electrode SE and drain electrode DE can each be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0071] Furthermore, this disclosure describes the arrangement of a first interlayer insulating layer 113a and a second interlayer insulating layer 113b (i.e., multiple insulating layers) between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, only a single insulating layer may be provided between the gate electrode GE, the source electrode SE, and the drain electrode DE. But this disclosure is not limited to this.

[0072] Furthermore, although not shown in the figures, in addition to the driving transistor DT, the pixel circuit may also include a switching transistor, a sensing transistor, a light-emitting control transistor, etc. However, this disclosure is not limited to these.

[0073] Meanwhile, the intermediate electrode TM can be disposed on the first interlayer insulating layer 113a. The intermediate electrode TM can be configured to overlap with the gate electrode GE of the driving transistor DT, with the first interlayer insulating layer 113a sandwiched between them, and form a capacitor with the gate electrode GE of the driving transistor DT. However, this disclosure is not limited to this.

[0074] An auxiliary electrode LE can be disposed on the gate insulating layer 112. The auxiliary electrode LE is used for electrically connecting the light-shielding layer LS disposed below the buffer layer 111 to either the source electrode SE or the drain electrode DE of the driving transistor DT disposed on the second interlayer insulating layer 113b. For example, the light-shielding layer LS can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the auxiliary electrode LE, thereby avoiding operation as a floating gate and minimizing or reducing the critical voltage change of the driving transistor DT caused by the floating light-shielding layer LS. The figure shows that the light-shielding layer LS is connected to the source electrode SE of the driving transistor DT. However, the light-shielding layer LS can also be connected to the drain electrode DE of the driving transistor DT. But the present invention is not limited thereto.

[0075] The capacitor Cst may be disposed on the gate insulating layer 112. The capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0076] First, the first capacitor electrode Cst1 may be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 may be disposed on the same layer as the gate electrode GE and made of the same material. However, this disclosure is not limited thereto.

[0077] The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode Cst2 may be disposed on the same layer as the intermediate electrode TM and made of the same material. However, the invention is not limited thereto. The second capacitor electrode Cst2 may be configured to overlap with the first capacitor electrode Cst1, with the first interlayer insulating layer 113a sandwiched between them. The second capacitor electrode Cst2 may be connected to the source electrode SE of the driving transistor DT.

[0078] The power line VDD may be disposed on the second interlayer insulating layer 113b. The power line VDD may be electrically connected to the light-emitting element LED together with the driving transistor DT, causing the LED to emit light. The power line VDD may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this disclosure is not limited thereto.

[0079] A first passivation layer 114a may be disposed on the driving transistor DT and the power line VDD. The first passivation layer 114a protects the driving transistor DT and the power line VDD from moisture or dopant penetration. For example, the first passivation layer 114a may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the first passivation layer 114a may be omitted. However, this disclosure is not limited thereto.

[0080] The capping layer 115 may be disposed on the first passivation layer 114a. The capping layer 115 can planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The capping layer 115 may be configured as a single layer or multiple layers and may be made of photoresist or acrylic organic materials, etc. However, this disclosure is not limited thereto.

[0081] Multiple reflective electrodes RE, spaced apart from each other, can be disposed on the cover layer 115. The multiple reflective electrodes RE can be used to electrically connect the light-emitting element (LED) to the power line VDD and the driving transistor DT, and act as a reflector to reflect light emitted from the LED to the top of the LED. The multiple reflective electrodes RE can all be made of conductive materials with excellent reflective properties, reflecting the light emitted from the LED to the top of the LED. Therefore, considering light reflection efficiency and resistance, the multiple reflective electrodes RE can contain various conductive layers. For example, the reflector can be made using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or their alloys, together with a transparent conductive layer made of indium tin oxide (ITO). However, the structure and materials of the reflector RE are not limited to this.

[0082] The plurality of reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 may be electrically connected to the driving transistor DT and the light-emitting element LED. The first reflective electrode RE1 may be connected to the source electrode SE or drain electrode DE of the driving transistor DT through contact holes formed in the first passivation layer 114a and the capping layer 115. In addition, the first reflective electrode RE1 may be electrically connected to the first electrode 124 of the light-emitting element LED through the first connection electrode CE1.

[0083] The second reflective electrode RE2 can be electrically connected to the power line VDD and the light-emitting element LED. The second reflective electrode RE2 can be connected to the power line VDD through the contact holes formed in the first passivation layer 114a and the cover layer 115, and electrically connected to the second electrode 125 of the light-emitting element LED through the second connecting electrode CE2 and the third connecting electrode CE3, which will be described below.

[0084] On multiple reflective electrodes RE, a bonding layer 116 can be formed on the front surface of the substrate 110 and a light-emitting element LED can be fixedly disposed on the bonding layer 116. The bonding layer 116 can be made of a light-curing or thermosetting bonding material that is transmissible to light or heat. For example, the bonding layer 116 can be made of an acrylic material containing a photosensitizer. However, this disclosure is not limited thereto.

[0085] Multiple light-emitting elements (LEDs) can be disposed on the bonding layer 116 and in each of the multiple sub-pixels SP. The multiple LEDs can be elements configured to emit light using current, and include LEDs configured to emit red, green, blue, etc. These LEDs can utilize combinations of red, green, blue, etc., to achieve various colors of light, including white light. For example, each of the multiple LEDs can be a light-emitting diode (LED) or a micro-LED. However, this disclosure is not limited to this.

[0086] The first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126.

[0087] The first semiconductor layer 121 may be disposed on the bonding layer 116, and the second semiconductor layer 123 may be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping with a specific material and an N-type dopant and a P-type dopant, respectively. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping with materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) and N-type and P-type dopant, respectively. Furthermore, the P-type dopant may be magnesium, zinc (Zn), beryllium (Be), etc., and the N-type dopant may be silicon (Si), germanium, tin (Sn), etc. However, this disclosure is not limited to these.

[0088] A portion of the first semiconductor layer 121 may be configured to protrude beyond the second semiconductor layer 123. The top surface of the first semiconductor layer 121 may include a portion overlapping the bottom surface of the second semiconductor layer 123, and a portion disposed outside the bottom surface of the second semiconductor layer 123. The light-emitting element LED may be a lateral light-emitting element LED. However, the dimensions and shapes of the first semiconductor layer 121 and the second semiconductor layer 123 may be modified in various ways. However, this disclosure is not limited thereto.

[0089] For example, the first semiconductor layer 121 may protrude to the outside of the second semiconductor layer 123 in one direction. The first semiconductor layer 121 may protrude to the outside of the second semiconductor layer 123 at the edge of a portion of the second semiconductor layer 123. A portion of the first semiconductor layer 121 may protrude to the outside of the second semiconductor layer 123 in a specific direction.

[0090] The light-emitting layer 122 can be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123.

[0091] The light-emitting layer 122 can be configured as a single layer or a multi-quantum well (MQW) structure. For example, the light-emitting layer 122 can be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, this disclosure is not limited thereto.

[0092] The first electrode 124 may be disposed on the first semiconductor layer 121. The first electrode 124 is an electrode used for electrically connecting the driving transistor DT to the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with an N-type dopant, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 may be disposed around the top surface of the first semiconductor layer 121, and the planar shape of the first electrode 124 may be annular. The first electrode 124 may be made of a conductive material, such as transparent conductive materials like indium tin oxide (ITO) or indium zinc oxide (IZO), or opaque conductive materials like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or their alloys. However, this disclosure is not limited to this.

[0093] The second electrode 125 may be disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. In this case, since the second semiconductor layer 123 is disposed on the first semiconductor layer 121, the second electrode 125 disposed on the top surface of the second semiconductor layer 123 may be disposed at a higher position than the first electrode 124 disposed on the top surface of the first semiconductor layer 121. The second electrode 125 is an electrode used for electrically connecting the power line VDD to the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with a P-type dopant, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, such as transparent conductive materials like indium tin oxide (ITO) or indium zinc oxide (IZO), or opaque conductive materials like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or their alloys. However, this disclosure is not limited to these.

[0094] Next, the passivation film 126 can be configured to surround the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation film 126 can be made of an insulating material and protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. In addition, contact holes can be formed in the passivation film 126 to expose the first electrode 124 and the second electrode 125, thereby electrically connecting the subsequently formed first connecting electrode CE1, third connecting electrode CE3, first electrode 124, and second electrode 125.

[0095] Meanwhile, although not shown in Figure 3, the second light-emitting element 130 and the third light-emitting element 140 can be arranged sequentially in a manner substantially the same as that of the first light-emitting element 120.

[0096] The first planarization layer 117a may be disposed on the bonding layer 116. The first planarization layer 117a may be configured to partially surround the side surfaces of a plurality of light-emitting elements (LEDs) and fix and protect these light-emitting elements (LEDs).

[0097] For example, the first planarization layer 117a can be configured to surround the passivation film 126 disposed on the lower edge of the light-emitting element LED. Therefore, an open circuit in the first connection electrode CE1 caused by tearing of the passivation film 126 can be suppressed. For example, during the process of separating the light-emitting element LED from the wafer, a portion of the passivation film 126 can be peeled off from the lower edge of the light-emitting element LED. Therefore, a portion of the first semiconductor layer 121 may be exposed at the lower edge of the light-emitting element LED due to the exposure of the passivation film 126. Therefore, a step difference may appear at the lower edge of the light-emitting element LED due to the removal of the passivation film 126. In this case, if the first connection electrode CE1 is configured to surround the side surface of the passivation film 126, the first connection electrode CE1 may experience an open circuit due to the step difference caused by the removal of the passivation film 126.

[0098] Therefore, before the first connecting electrode CE1 is provided, the first planarization layer 117a is configured to surround the lower edge of the light-emitting element LED, thereby separating the lower edge of the light-emitting element LED from the first connecting electrode CE1. Therefore, even if an undercut structure is formed at the lower edge of the light-emitting element LED due to the removal of the passivation film 126, the first planarization layer 117a will still contact at least a portion of the side surface of the light-emitting element LED while filling this undercut structure, thereby minimizing or reducing the open circuit of the first connecting electrode CE1 caused by the undercut structure.

[0099] Simultaneously, the first planarization layer 117a can be configured to be lower than the height of the first electrode 124 and expose the first electrode 124. Therefore, the first connection electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124. Details related to the above configuration will be described in detail with reference to Figures 4A to 4H below.

[0100] Furthermore, the first planarization layer 117a may be included in a relatively low-height portion of the region adjacent to the light-emitting element LED. For example, during the process of forming the contact holes of the passivation film 126 to expose the first electrode 124 and the second electrode 125, the relatively low-height portion may be included by removing a portion of the first planarization layer 117a in the region near the light-emitting element LED. Details related to the above configuration will be described in detail with reference to Figures 4A to 4H below.

[0101] The first planarization layer 117a can be configured as a single layer or multiple layers, and is made of photoresist or acrylic organic materials, etc. However, this disclosure is not limited thereto.

[0102] Simultaneously, the first planarization layer 117a can be lower than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a can be adjusted by performing an ashing process. For example, after applying the material layer of the first planarization layer 117a to cover the light-emitting element LED, an ashing process is performed to reduce the total thickness of the material layer of the first planarization layer 117a, thereby making the height of the first planarization layer 117a lower than the height of the first electrode 124. Therefore, the first planarization layer 117a can expose the first electrode 124. Therefore, the first connecting electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without using a separate contact hole. Therefore, the first connecting electrode CE3 and the first electrode 124 can be automatically aligned without ensuring process margin.

[0103] The first connecting electrode CE1 may be disposed on the first planarization layer 117a. The first connecting electrode CE1 is disposed in each of the plurality of sub-pixels SP and configured to electrically connect the light-emitting element LED and the driving transistor DT. The first connecting electrode CE1 may be configured to surround the light-emitting element LED. The first connecting electrode CE1 may be connected to the first reflecting electrode RE1 through contact holes formed in the first planarization layer 117a and the bonding layer 116. Therefore, the first connecting electrode CE1 may be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflecting electrode RE1. For example, the first connecting electrode CE1 may connect the first electrode 124 of the light-emitting element LED to the source electrode SE of the driving transistor DT. However, this disclosure is not limited thereto. For example, the first connecting electrode CE1 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this disclosure is not limited thereto.

[0104] In the first contact area CA1 and the second contact area CA2, the second connecting electrode CE2 can be disposed on the first planarization layer 117a. The second connecting electrode CE2 is an electrode for electrically connecting the light-emitting element LED and the power line VDD. The second connecting electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the first planarization layer 117a and the bonding layer 116. For example, the second connecting electrode CE2 can be electrically connected to the second reflective electrode RE2 through the first contact hole CH1 of the bonding layer 116 in the first contact area CA1 and the second contact hole CH2 of the first planarization layer 117a that overlaps with the first contact hole CH1. Therefore, the second connecting electrode CE2 can be electrically connected to the power line VDD through the second reflective electrode RE2. For example, the second connecting electrode CE2 can connect the second electrode 125 of the light-emitting element LED and the power line VDD. However, this disclosure is not limited to this.

[0105] Meanwhile, the second connecting electrode CE2 and the first connecting electrode CE1 can be disposed on the same layer and made of the same material. However, this disclosure is not limited to this. For example, the second connecting electrode CE2 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). But this disclosure is not limited to this.

[0106] A second passivation layer 114b may be disposed on the first connecting electrodes CE1 and the second connecting electrodes CE2. The second passivation layer 114b may be disposed on the first connecting electrodes CE1 and the second connecting electrodes CE2, and prevent moisture or dopants from penetrating into the plurality of reflective electrodes RE1 connected to the plurality of first connecting electrodes CE1 and the plurality of second connecting electrodes CE2. For example, the second passivation layer 114b may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto.

[0107] Furthermore, the second passivation layer 114b can be configured to cover at least a portion of the first connection electrode CE1, such that the first connection electrode CE1 and the third connection electrode CE3 can be separated from each other. Therefore, the second passivation layer 114b can suppress short circuits between the first connection electrode CE1 and the third connection electrode CE3.

[0108] The second passivation layer 114b may include a first opening portion OP1 that exposes the first planarization layer 117a. For example, the first opening portion OP1 may be disposed between the first connecting electrode CE1 and the second connecting electrode CE2.

[0109] The second planarization layer 117b can be disposed on the second passivation layer 114b. The second planarization layer 117b and the first planarization layer 117a can together planarize the upper part of the substrate 110 on which the light-emitting element LED is disposed. The second planarization layer 117b and the bonding layer 116 together can fix the light-emitting element LED on the substrate 110.

[0110] Furthermore, the second planarization layer 117b can be configured to cover the first connecting electrode CE1, thereby isolating the first connecting electrode CE1 from the third connecting electrode CE3. Therefore, short circuits between the first connecting electrode CE1 and the third connecting electrode CE3 can be suppressed.

[0111] Specifically, the second planarization layer 117b can be configured to cover the end of the first connection electrode CE1 exposed by the second passivation layer 114b, thereby separating the first connection electrode CE1 from the third connection electrode CE3. For example, during the process of forming the second planarization layer 117b, the curing process can cause the second planarization layer 117b to flow downwards, i.e., back to the end of the first connection electrode CE1 exposed through the second passivation layer 114b. Therefore, the portion of the second planarization layer 117b that overlaps with the end of the first connection electrode CE1 exposed through the second passivation layer 114b can have a relatively low height. In other words, the portion of the second planarization layer 117b surrounding the end of the first connection electrode CE1 can have an angle.

[0112] For example, the end of the first connecting electrode CE1 of the LED contactor can be exposed through the second passivation layer 114b. Therefore, the height of the second planarization layer 117b can gradually decrease towards the LED. However, since the second planarization layer 117b is configured to cover the end of the first connecting electrode CE1 exposed through the second passivation layer 114b, the height of the lowest point of the top surface of the second planarization layer 117b can be higher than the height of the highest point of the top surface of the end of the first connecting electrode CE1 exposed by the second passivation layer 114b.

[0113] Meanwhile, the second planarization layer 117b can be disposed within the first opening portion OP1 and cover the ends of the first connecting electrode CE1 and the second connecting electrode CE2, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be separated from each other. Therefore, short circuits between the first connecting electrode CE1 and the second connecting electrode CE2 can be suppressed.

[0114] Specifically, an opening portion overlapping the first opening portion OP1 of the second passivation layer 114b can be formed in the second planarization layer 117b, and the curing process can cause backflow in the first opening portion OP1 of the second planarization layer 117b. Therefore, the width of the second opening portion OP2 formed due to backflow of the second planarization layer 117b can be smaller than the width of the first opening portion OP1. Details related to the aforementioned configuration will be explained with reference to Figures 4A to 4H.

[0115] The second planarization layer 117b can be configured as a single layer or multiple layers. For example, similar to the first planarization layer 117a, the second planarization layer 117b can be made of photoresist or acrylic organic materials. However, this disclosure is not limited to this.

[0116] The third connecting electrode CE3 may be disposed on the second planarization layer 117b. The third connecting electrode CE3 is an electrode for electrically connecting the light-emitting element LED and the power line VDD. The third connecting electrode CE3 may be connected to the second reflective electrode RE2 through a plurality of contact holes formed in the second planarization layer 117b, the second passivation layer 114b, the first planarization layer 117a, and the bonding layer 116. Therefore, the third connecting electrode CE3 may be electrically connected to the power line VDD through the second reflective electrode RE2. For example, the third connecting electrode CE3 may connect the second electrode 125 of the light-emitting element LED to the power line VDD. However, this disclosure is not limited to this. For example, the third connecting electrode CE3 may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this disclosure is not limited to this.

[0117] For example, the third connecting electrode CE3 can be disposed in the first contact hole CH1 of the bonding layer 116 disposed in the first contact area CA1, the second contact hole CH2 of the first planarization layer 117a disposed in the first contact area CA1, the third contact hole CH3 of the second passivation layer 114b overlapping the first contact hole CH1 and the second contact hole CH2, and the fourth contact hole CH4 of the second planarization layer 117b overlapping the first contact hole CH1. The third connecting electrode CE3 can contact the second connecting electrode CE2. Therefore, the third connecting electrode CE3 can be electrically connected to the second reflecting electrode RE2 through the second connecting electrode CE2, and electrically connected to the power line VDD through the second reflecting electrode RE2.

[0118] In this case, the third connecting electrode CE3 can be additionally electrically connected to the second connecting electrode CE2 in the second contact region CA2. For example, the third connecting electrode CE3 can be continuously disposed in the first contact region CA1 and the second contact region CA2 and electrically connected to the second connecting electrode CE2 extending from the first contact region CA1 via the fifth contact hole CH5 of the second passivation layer 114b and the sixth contact hole CH6 of the second planarization layer 117b disposed in the second contact region CA2. In other words, the third connecting electrode CE3 can receive power supply voltage from the power line VDD in the second contact region CA2 and the first contact region CA1. Therefore, the resistance between the power line VDD and the third connecting electrode CE3 can be reduced.

[0119] Specifically, unlike the third contact hole CH3 and the fourth contact hole CH4 in the first contact region CA1, the fifth contact hole CH5 and the sixth contact hole CH6 in the second contact region CA2 may not overlap with the first contact hole CH1 of the bonding layer 116 and the second contact hole CH2 of the first planarization layer 117a. Therefore, the electrical connection between the third connecting electrode CE3 and the second connecting electrode CE2 can be improved by minimizing or reducing defects in the bonding layer 116 and the first planarization layer 117a caused by residual film.

[0120] Furthermore, even if the second connecting electrode CE2 and the third connecting electrode CE3 are not electrically connected to each other in either the first contact region CA1 or the second contact region CA2, the second connecting electrode CE2 and the third connecting electrode CE3 can be connected in the remaining region. Therefore, the electrical connection between the second connecting electrode CE2 and the third connecting electrode CE3 can be improved.

[0121] Meanwhile, the third connecting electrode CE3 is disposed on and in direct contact with the second electrode 125. Therefore, the lighting detection signal can be transmitted directly to the second electrode 125 during lighting detection without passing through the driving transistor DT. Thus, it is not necessary to operate the driving transistor DT separately, so that defects in the light-emitting element LED can be detected regardless of whether the driving transistor DT has defects.

[0122] Furthermore, the third connecting electrode CE3 can be formed before the process of forming the embankment 118 as described below. Therefore, the presence of defects in the light-emitting element LED can be detected before the process of forming the embankment 118.

[0123] Meanwhile, the third connecting electrode CE3 can be disposed in the first opening portion OP1 and the second opening portion OP2 and configured to contact the second planarization layer 117b. In this case, since the width of the second opening portion OP2 is smaller than the width of the first opening portion OP1, the third connecting electrode CE3 may not contact the second passivation layer 114b. However, this disclosure is not limited to this.

[0124] The illumination detection pattern APP can be disposed on the second planarization layer 117b in the illumination detection area APA. The illumination detection pattern APP can contact the first connecting electrode CE1 through the seventh contact hole CH7 formed in the second passivation layer 114b and the eighth contact hole CH8 formed in the second planarization layer 117b.

[0125] Therefore, the illumination detection pattern APP can be electrically connected to the first electrode 124 of the light-emitting element LED via the first connecting electrode CE1. Therefore, the illumination detection signal can be directly transmitted to the first electrode 124 of the light-emitting element LED without passing through the driving transistor DT. Therefore, without the need for independent operation of the driving transistor DT, defects in the light-emitting element LED can be detected regardless of whether the driving transistor DT has defects. The illumination detection pattern APP can be disposed on the same layer as the third connecting electrode CE3 and made of the same material. However, this disclosure is not limited to this. Therefore, similar to the third connecting electrode CE3, the illumination detection pattern APP is formed before the process of forming the embankment 118, which will be described below, thereby enabling the detection of defects in the light-emitting element LED before the process of forming the embankment 118. For example, the illumination detection pattern APP can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, the illumination detection pattern APP can be referred to as a conductive pattern. However, this disclosure is not limited to this.

[0126] A protective pattern PP can be disposed on the second planarization layer 117b. The protective pattern PP can be configured to cover the first reflective electrode RE1 exposed through the contact holes of the bonding layer 116. Therefore, the protective pattern PP can protect the first connecting electrode RE1. For example, the protective pattern PP can act as a mask during the ashing process of the second planarization layer 117b, thereby enabling the ashing process to suppress the oxidation of the first reflective electrode RE1.

[0127] In addition, the protective pattern PP can be connected to the first connection electrode RE1 and reduce the line resistance of the first connection electrode RE1.

[0128] A dam 118 may be disposed on the second planarization layer 117b, the third connecting electrode CE3, and the second illumination detection pattern APP. Therefore, the dam 118 can directly contact the second planarization layer 117b, the third connecting electrode CE3, and the second illumination detection pattern APP. However, this disclosure is not limited to this. The dam 118 may be configured not to overlap with the light-emitting element LED, and the dam 118 may define a light-emitting area. For example, the dam 118 may define the light-emitting area by covering the edge of the third connecting electrode CE3 connected to the light-emitting element LED. In other words, the dam 118 may separate multiple sub-pixels SP. The dam 118 may be made of an insulating material to insulate the second connecting electrodes CE3 of adjacent sub-pixels SP. Furthermore, the dam 118 may include a black component with high light absorption to suppress color mixing between adjacent sub-pixels SP, and the dam 118 may be configured as a black dam. For example, the dam 118 may be made of polyimide resin, acrylic resin, or benzocyclobutene (BCB) resin. However, this disclosure is not limited to this.

[0129] The third planarization layer 119 can be disposed on the second planarization layer 117b and the embankment 118. The third planarization layer 119 can be configured to cover the top surface of the light-emitting element LED and fix and protect the light-emitting element LED, while planarizing the upper part of the substrate 110 on which the light-emitting element LED is disposed. Therefore, the third planarization layer 119 can be referred to as a protective layer or a cover layer. However, this disclosure is not limited thereto. The third planarization layer 119 can be configured as a single layer or multiple layers and is made of photoresist or acrylic organic materials, etc. However, this disclosure is not limited thereto.

[0130] Hereinafter, a method for manufacturing a display device according to an embodiment of the present disclosure will be shown with reference to Figures 4A to 4H.

[0131] Figures 4A to 4H are process diagrams of a display device manufacturing method according to an exemplary embodiment of the present disclosure.

[0132] First, referring to Figures 4A to 4H, the light-emitting element LED can be disposed on the bonding layer 116, and the first planarization layer 117a can be disposed on the bonding layer 116 and surround the light-emitting element LED.

[0133] The connecting electrode material layer CE' and the second first passivation material layer 114b' can be sequentially disposed on the front surface of the substrate 110 on the first planarization layer 117a and on the light-emitting element LED.

[0134] The connecting electrode material layer CE' can be disposed on the front surface of the substrate 110 and cover the light-emitting element LED and the first planarization layer 117a. Therefore, the connecting electrode material layer CE' can also be disposed within the second contact hole CH2 formed in the first planarization layer 117a and within the first contact hole CH1 of the bonding layer 116 that overlaps with the second contact hole CH2. In addition, the connecting electrode material layer CE' can be configured to cover the side surface and top surface of the light-emitting element LED.

[0135] The second first passivation material layer 114b' may be disposed on the front surface of the substrate 110 on the electrode material layer CE'. The second first passivation material layer 114b' may be configured to be separated from the light-emitting element LED, the first planarization layer 117a and the bonding layer 116 by the electrode material layer CE'.

[0136] Simultaneously, the second first passivation material layer 114b' can be formed through a deposition process. In this case, the deposition temperature of the second first passivation material layer 114b' can be determined by considering the connection electrode material layer CE' disposed below the second first passivation material layer 114b'. For example, if the connection electrode material layer CE' is made of the transparent conductive material indium tin oxide (ITO), the connection electrode material layer CE' may crystallize at approximately 250°C. To suppress crystallization, the deposition process of the second first passivation material layer 114b' can be performed at a relatively low temperature condition of approximately 200°C or lower (e.g., approximately 180°C).

[0137] Next, referring to FIG4B, a second first planarization material layer 117b' may be disposed on the second first passivation material layer 114b' and surround the light-emitting element LED. The height of the second first planarization material layer 117b' may be lower than the height of the second electrode 125 of the light-emitting element LED. For example, the thickness of the second first planarization material layer 117b' may be adjusted by performing an ashing process. For example, after covering the light-emitting element LED with the second first planarization material layer 117b', an ashing process is performed to reduce the total thickness of the second first planarization material layer 117b', thereby making the height of the second first planarization material layer 117b' lower than the height of the second electrode 125. Therefore, during subsequent processes, the third connecting electrode CE3 disposed on the second first planarization material layer 117b' may be easily connected to the second electrode 125.

[0138] Simultaneously, the initial second opening portion OP2' can be formed in the second first planarization material layer 117b'. The initial second opening portion OP2' can expose the second first passivation material layer 114b'.

[0139] Next, referring to FIG4C, a second passivation material layer 114b'' can be formed by etching the second first passivation material layer 114b'. The second passivation material layer 114b'' can be formed by etching the second first passivation material layer 114b' exposed from the second first planarization material layer 117b'.

[0140] For example, since the second first planarization material layer 117b' is formed to have a thickness less than that of the light-emitting element LED, the second first passivation material layer 114b' covering the upper side of the light-emitting element LED can be exposed from the second first planarization material layer 117b'.

[0141] Furthermore, since the second first planarization material layer 117b' forms an opening in the initial second opening portion OP2', the second first passivation material layer 114b' overlapping with the initial second opening portion OP2' can be exposed from the second first planarization material layer 117b'. Therefore, the second second passivation material layer 114b'' can be formed by etching a portion of the second first passivation material layer 114b' covering the upper side of the light-emitting element LED and a portion of the second first passivation material layer 114b' overlapping with the initial second opening portion OP2'. Therefore, the first opening portion OP1 overlapping with the initial second opening portion OP2' can be formed in the second second passivation material layer 114b''.

[0142] For example, the second passivation material layer 114b'' can be formed by a wet etching process. Therefore, not only can the portion of the second first passivation material layer 114b' exposed through the second first planarization material layer 117b' be partially removed, but the portion of the second first passivation material layer 114b' overlapping with the second first planarization material layer 117b' can also be partially removed. Therefore, the end of the second passivation material layer 114b'' can be located inside the end of the second first planarization material layer 117b'. Therefore, the width of the first opening portion OP1 can be greater than the width of the initial second opening portion OP2'. However, this disclosure is not limited to this.

[0143] Simultaneously, during the etching process of the second passivation material layer 114b'', the second planarization material layer 117b'' ​​can be formed by etching a portion of the second first planarization material layer 117b'. For example, a portion of the second first planarization material layer 117b' adjacent to the light-emitting element LED can also be etched. However, this disclosure is not limited to this.

[0144] Next, referring to FIG4D, the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE'. The first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be formed by etching the connecting electrode material layer CE' exposed from the second first planarization material layer 117b” and the second second passivation material layer 114b”.

[0145] Specifically, the second planarization material layer 117b" forms an opening in the initial second opening portion OP2', and the second passivation material layer 114b" forms an opening in the first opening portion OP1, so that the connection electrode material layer CE' overlapping with the initial second opening portion OP2' and the first opening portion OP1 can be exposed from the second planarization material layer 117b'' ​​and the second passivation material layer 114b''. Therefore, the first connection electrode CE1, the second connection electrode CE2, and the protective pattern PP can be formed by etching a portion of the connection electrode material layer CE' overlapping with the initial second opening portion OP2' and the first opening portion OP1.

[0146] For example, a first connecting electrode CE1, a second connecting electrode CE2, and a protective pattern PP can be formed through a wet etching process. Therefore, not only can a portion of the connecting electrode material layer CE' exposed through the second planarization material layer 117b'' ​​and the second passivation material layer 114b'' be partially removed, but also a portion of the connecting electrode material layer CE' overlapping with the second planarization material layer 117b'' ​​and the second passivation material layer 114b'' can be partially removed. Therefore, the ends of the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP can be disposed inside the ends of the second planarization material layer 117b'' ​​and the second passivation material layer 114b''. However, this disclosure is not limited to this.

[0147] Simultaneously, the second and third passivation layers 114b''' can also be formed by etching a portion of the second passivation material layer 114b''. For example, not only can the connection electrode material layer CE' disposed on the side surface of the light-emitting element LED be exposed through the second planarization material layer 117b'', but the second passivation material layer 114b'' disposed on the side surface of the light-emitting element LED can also be exposed through the second planarization material layer 117b''. Therefore, the second and third passivation layers 114b''' can be formed by removing a portion of the second passivation material layer 114b''' disposed on the side surface of the light-emitting element LED.

[0148] Simultaneously, a portion of the second passivation material layer 114b'' adjacent to the light-emitting element LED is removed, exposing the end of the first connection electrode CE1 in contact with the light-emitting element LED to the second passivation layer 114b'''. However, this disclosure is not limited to this.

[0149] Next, referring to FIG4E, the second and third planarization material layers 117b''' can be formed by partially graying (e.g., halftone graying) the second planarization material layer 117b''.

[0150] For example, a portion of the second planarization material layer 117b'' ​​overlapping with the second connecting electrode CE2 can be partially ashed. For example, an initial fourth contact hole CH4' can be formed by ashing a portion of the second planarization material layer 117b'' ​​overlapping with the first contact hole CH1 and the second contact hole CH2. Therefore, the initial fourth contact hole CH4' can overlap with the first contact hole CH1 and the second contact hole CH2. The initial fourth contact hole CH4' can be provided on the second connecting electrode CE2 to connect the third connecting electrode CE3 to the second connecting electrode CE2 during subsequent processes.

[0151] Furthermore, an initial sixth contact hole CH6' can be formed by ashing a portion of a second planarization material layer 117b'' ​​that overlaps with the second connecting electrode CE2 but not with the first contact hole CH1 and the second contact hole CH2. The initial sixth contact hole CH6' can be disposed on the second connecting electrode CE2 to additionally connect the third connecting electrode CE3 and the second connecting electrode CE2 during subsequent processes.

[0152] Furthermore, an initial eighth contact hole CH8' can be formed by partially ashing a portion of the second planarization material layer 117b'' ​​that overlaps with the first connecting electrode CE1. The initial eighth contact hole CH8' allows the illumination detection pattern APP to be connected to the first connecting electrode CE1 during subsequent processes.

[0153] Next, referring to FIG4F, the second passivation layer 114b can be formed by etching the second passivation material layer 114b''. The second passivation layer 114b can be formed by etching the second passivation layer 114b''' exposed from the second third planarization material layer 117b'''.

[0154] For example, since the second and third planarization material layers 117b''' form openings in the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8', the second and third passivation material layers 114b''' overlapping with the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8' can be exposed from the second and third planarization material layers 117b'''. Therefore, the second and third passivation material layers 114b''' exposed through the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8' can be etched to form the second passivation layer 114b. Therefore, the third contact hole CH3 overlapping with the initial fourth contact hole CH4', the fifth contact hole CH5 overlapping with the initial sixth contact hole CH6', and the seventh contact hole CH7 overlapping with the initial eighth contact hole CH8' can be formed in the second passivation layer 114b.

[0155] For example, the second passivation layer 114b can be formed by a dry etching process. Therefore, unlike a wet etching process, the portion of the second and third passivation material layer 114b''' overlapping with the second and third planarization material layer 117b''' can be left unremoved; instead, only the portion of the second and third passivation material layer 114b''' exposed through the second and third planarization material layer 117b''' can be removed. Therefore, the ends of the portions of the second passivation layer 114b that form openings through the third contact hole CH3, the fifth contact hole CH5, and the seventh contact hole CH7 can coincide with the ends of the portions of the second and third planarization material layer 117b''' that form openings through the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8'. However, this disclosure is not limited to this.

[0156] Next, referring to FIG4G, the second planarization layer 117b can be formed by curing the second and third planarization material layers 117b'''. Specifically, the curing process can reflow the second and third planarization material layers 117b''', so that the second and third planarization material layers 117b''' can cover the end of the second passivation layer 114b disposed below the second and third planarization material layers.

[0157] Specifically, the second and third planarization material layers 117b''', which form an opening through the initial fourth contact hole CH4', can be reflowed and disposed in the third contact hole CH3. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b that forms an opening through the third contact hole CH3. Therefore, the width of the fourth contact hole CH4 can be smaller than the width of the third contact hole CH3.

[0158] The second and third planarization material layers 117b''', which form an opening through the initial sixth contact hole CH6', can be reflowed and disposed within the fifth contact hole CH5. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b that forms an opening through the fifth contact hole CH5. Therefore, the width of the sixth contact hole CH6 can be smaller than the width of the fifth contact hole CH5.

[0159] The second and third planarization material layers 117b''', which form an opening through the initial eighth contact hole CH8', can be reflowed and disposed within the seventh contact hole CH7. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b that forms an opening through the seventh contact hole CH7. Therefore, the width of the eighth contact hole CH8 of the second planarization layer 117b can be smaller than the width of the seventh contact hole CH7.

[0160] The second and third planarization material layers 117b''', which form an opening through the initial second opening portion OP2', can be reflowed and disposed in the first opening portion OP1. Therefore, the second planarization layer 117b can be configured to cover the end of the second passivation layer 114b that forms an opening through the first opening portion OP1. Therefore, the width of the second opening portion OP2 of the second planarization layer 117b can be smaller than the width of the first opening portion OP1.

[0161] Simultaneously, the second planarization layer 117b can flow back to the first opening portion OP1 and be disposed on the first planarization layer 117a overlapping the first opening portion OP1. In this case, since the first opening portion OP1 is disposed between the first connecting electrode CE1 and the second connecting electrode CE2, the second planarization layer 117b can be configured to cover the ends of the first connecting electrode CE1 and the second connecting electrode CE2. Therefore, the second planarization layer 117b can separate the first connecting electrode CE1 and the second connecting electrode CE2.

[0162] Specifically, the second planarization layer 117b can be configured to cover not only the end of the second passivation layer 114b, but also the end of the first connection electrode CE1 exposed through the second passivation layer 114b. Therefore, the second planarization layer 117b can separate the first connection electrode CE1 and the third connection electrode CE3 from each other during subsequent processes.

[0163] Specifically, as described above, the end of the first connecting electrode CE1 in contact with the light-emitting element LED can be exposed through the second passivation layer 114b. In this case, the curing process can reflow the second planarization layer 117b, thereby allowing the second planarization layer 117b to be disposed on the end of the first connecting electrode CE1 exposed through the second passivation layer 114b. Therefore, the second planarization layer 117b can reflow and cover the end of the first connecting electrode CE1 in contact with the light-emitting element LED. Therefore, the height of the second planarization layer 117b can gradually decrease towards the light-emitting element LED. The second planarization layer 117b can be configured to cover the end of the first connecting electrode CE1 and the end of the second passivation layer 114b surrounding a portion of the side surface of the light-emitting element LED. The tilt direction of the end of the first connecting electrode CE1 and the end of the second passivation layer 114b on the side surface of the light-emitting element LED can be the same as the tilt direction of the second planarization layer 117b covering the end of the first connecting electrode CE1 and the end of the second passivation layer 114b. The second planarization layer 117b and the light-emitting element LED can be defined in a "V" shape at the contact position between the second planarization layer 117b and the side surface of the light-emitting element LED. As shown in Figures 3 and 4H, the side surface of the light-emitting element LED can be the left surface of the light-emitting element LED, the right surface of the light-emitting element LED, or both the left and right surfaces of the light-emitting element LED.

[0164] Next, referring to Figure 4H, the third connecting electrode CE3 and the illumination detection pattern APP can be disposed on the second planarization layer 117b and spaced apart from each other. The third connecting electrode CE3 can be disposed on the light-emitting element LED, and the illumination detection pattern APP can be disposed to overlap with the eighth contact hole CH8.

[0165] As previously described, the second planarization layer 117b is formed by performing only an ashing process until the second electrode 125 of the light-emitting element LED is exposed. The third connection electrode CE3 disposed on the second planarization layer 117b can only contact the top surface of the second electrode 125 exposed from the second planarization layer 117b, and the third connection electrode CE3 can be separated from the first connection electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121 disposed below the second planarization layer 117b. Therefore, the third connection electrode CE3 and the second electrode 125 can be automatically aligned without ensuring process margin.

[0166] Meanwhile, the illumination detection pattern APP can be set in the seventh contact hole CH7 and the eighth contact hole CH8 located on the second planarization layer 117b, and electrically connected to the first connection electrode CE1 exposed through the seventh contact hole CH7 and the eighth contact hole CH8.

[0167] In this configuration, illumination detection can be performed. For example, multiple illumination detection signals can be applied to the illumination detection pattern APP and the third connecting electrode CE3. Therefore, the illumination detection signals applied via the illumination detection pattern APP can be transmitted to the first electrode 124 of the light-emitting element LED through the first connecting electrode CE1. The multiple illumination detection signals applied via the third connecting electrode CE3 can be transmitted to the second electrode 125 of the light-emitting element LED. Thus, the presence of defects in the light-emitting element LED can be detected regardless of whether the driving transistor DT is defective.

[0168] Next, the embankment 118 and the third planarization layer 119 are disposed on the second planarization layer 117b, the third connecting electrode CE3 and the illumination detection pattern APP, thereby completing the manufacturing process of the display device 100.

[0169] During the process of setting or transferring multiple light-emitting elements onto a substrate, some light-emitting elements may be misaligned or incorrectly positioned. In this case, if subsequent processes are performed with some light-emitting elements misaligned or incorrectly positioned, short-circuit defects between electrodes may occur. For example, if light-emitting elements are misaligned and the same electrode is connected to the first and second electrodes of the light-emitting element, or if the electrodes connected to the first and second electrodes of the light-emitting element are set to overlap instead of being separated, a short-circuit defect occurs and the light-emitting element may not emit light normally.

[0170] Therefore, in the display device 100 of this disclosed embodiment, the first electrode 124 of the light-emitting element LED and the first connecting electrode CE1 can be automatically aligned and connected. For example, after applying a material layer of the first planarization layer 117a to cover the light-emitting element LED, the material layer of the first planarization layer 117a is ashed, exposing the first electrode 124. Therefore, the first connecting electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without the need for individual contact holes. Therefore, the first connecting electrode CE1 and the first electrode 124 can be automatically aligned without ensuring process margin. Therefore, short-circuit defects between the first connecting electrode CE1 and the third connecting electrode CE3 caused by process errors can be minimized or reduced.

[0171] Similarly, in the display device 100 of this disclosed embodiment, the second electrode 125 and the third connecting electrode CE3 of the light-emitting element LED can be autonomously aligned and connected. For example, after applying a material layer of the second planarization layer 117b to cover the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED, the material layer of the second planarization layer 117b is ashed to expose only the second electrode 125. Therefore, even if the second connecting electrode CE2 is formed by forming and patterning a material layer of the second connecting electrode CE2 on the front surface of the substrate 110 containing the second planarization layer 117b, the second connecting electrode CE2 can only contact the top surface of the second electrode 125 exposed through the second planarization layer 117b. That is, the third connecting electrode CE3 and the second electrode 125 can be autonomously aligned without ensuring process margin. Therefore, short-circuit defects between the first connecting electrode CE1 and the third connecting electrode CE3 caused by process errors can be minimized or reduced.

[0172] Furthermore, in the display device 100 of this disclosed embodiment, a second passivation layer 114b may be disposed on the first connection electrode CE1 and the second connection electrode CE2. Since the second passivation layer 114b is configured to cover at least a portion of the first connection electrode CE1, the second passivation layer 114b, together with the second planarization layer 117b, can separate the first connection electrode CE1 and the third connection electrode CE3 from each other. Therefore, the second passivation layer 114b can suppress the first connection electrode CE1 and the third connection electrode CE3 from being short-circuited.

[0173] Furthermore, the second passivation layer 114b is made of an inorganic insulating material, which can inhibit moisture or dopants from penetrating into the multiple reflective electrodes RE connected to the multiple first connecting electrodes CE1 and the multiple second connecting electrodes CE2. Therefore, it can suppress the separation and corrosion of the multiple reflective electrodes RE caused by moisture penetration.

[0174] Specifically, in the display device 100 of the present disclosure embodiment, if the first connecting electrode CE1 is exposed by the second passivation layer 114b, the second planarization layer 117b flows back to the exposed first connecting electrode CE1, allowing the first connecting electrode CE1 and the third connecting electrode CE3 to be separated from each other. For example, the curing process causes the second planarization layer 117b to flow back, so that the second planarization layer 117b can be configured to cover the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, in the display device 100 of the present disclosure embodiment, even if the first connecting electrode CE1 is exposed by the second passivation layer 114b during the process, the second planarization layer 117b can flow back, allowing the first connecting electrode CE1 and the third connecting electrode CE3 to be separated, thus suppressing short-circuit defects in the connection between the first connecting electrode CE1 and the third connecting electrode CE3.

[0175] Various exemplary embodiments disclosed herein may also be described as follows:

[0176] According to one aspect of this disclosure, a display device is provided. The display device includes a substrate defining a plurality of sub-pixels, a power line and a driving transistor disposed on the substrate, a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor, the second reflective electrode being connected to the power line, a bonding layer disposed on the first reflective electrode and the second reflective electrode, a plurality of light-emitting elements disposed on the bonding layer and including the first electrode and the second electrode in the sub-pixels, a first planarization layer disposed on the bonding layer and configured to partially surround a plurality of side surfaces of the light-emitting elements, a first connection electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor, a second connection electrode disposed on the first planarization layer and spaced apart from the first connection electrode and connected to the second reflective electrode, a passivation layer disposed on the first connection electrode and the second connection electrode, a second planarization layer disposed on the passivation layer and configured to partially surround the side surfaces of the light-emitting elements, and a third connection electrode disposed on the second planarization layer and configured to connect the second electrode and the power line. This passivation layer exposes the end of the first connection electrode, which is configured to surround a portion of the side surface of one of the light-emitting elements. A second planarization layer covers the end of the first connection electrode.

[0177] The second planarization layer can be configured to cover the end of the first connecting electrode and the end of the passivation layer corresponding to the end of the first connecting electrode.

[0178] The tilt direction of the end of the first connecting electrode and the end of the passivation layer on the side surface of the light-emitting element is the same as the tilt direction of the second planarization layer covering the end of the first connecting electrode and the end of the passivation layer. The second planarization layer may define a "V" shape in the area contacting the light-emitting element.

[0179] The height of a portion of the second planarization layer that overlaps with the end of the first connecting electrode may be lower than the height of a portion of the second planarization layer that does not overlap with the end of the first connecting electrode.

[0180] The passivation layer may include a first opening portion exposing the first planarization layer. The second planarization layer may include a second opening portion overlapping the first opening portion. The width of the first opening portion may be greater than the width of the second opening portion. The second planarization layer may be disposed in the first opening portion and may cover the other end of the first connecting electrode and the end of the second connecting electrode.

[0181] The third connecting electrode can be disposed in the first opening portion and the second opening portion, and configured to contact the first planarization layer.

[0182] The bonding layer may include a first contact hole exposing the second reflective electrode. The first planarization layer may include a second contact hole overlapping the first contact hole and exposing the second reflective electrode. A second connecting electrode may be disposed in the first and second contact holes and may contact the second reflective electrode. The passivation layer may include a third contact hole overlapping the first and second contact holes and exposing the second connecting electrode. The second planarization layer may include a fourth contact hole overlapping the first, second, and third contact holes and exposing the second connecting electrode. A third contact electrode may be disposed in the first, second, third, and fourth contact holes and may contact the second connecting electrode.

[0183] The width of the third contact hole can be greater than the width of the fourth contact hole. The second planarization layer can be disposed in the third contact hole and can cover the end of the passivation layer.

[0184] The bonding layer may include a first contact hole exposing the second reflective electrode. The first planarization layer may include a second contact hole overlapping the first contact hole and exposing the second reflective electrode. A second connecting electrode may be disposed in the first and second contact holes and may contact the second reflective electrode. The passivation layer may include a fifth contact hole exposing the second connecting electrode without overlapping the first and second contact holes. The second planarization layer may include a sixth contact hole overlapping the fifth contact hole. A third connecting electrode may be disposed in the fifth and sixth contact holes and may contact the second connecting electrode.

[0185] The width of the fifth contact hole can be greater than the width of the sixth contact hole. The second planarization layer can be disposed in the fifth contact hole and can cover the end of the passivation layer.

[0186] The display device may further include a conductive pattern disposed on a second planarization layer. The passivation layer may include a seventh contact hole exposing a first connection electrode. The second planarization layer may include an eighth contact hole overlapping the seventh contact hole. The conductive pattern may be connected to the first connection electrode via the seventh and eighth contact holes.

[0187] The width of the seventh contact hole can be greater than the width of the eighth contact hole. A second planarization layer can be disposed in the seventh contact hole and can cover the end of the passivation layer.

[0188] The height of the first planarization layer can be lower than the height of the first electrode, and the height of the second planarization layer can be lower than the height of the second electrode.

[0189] The side surfaces of multiple light-emitting elements can be either or both of the two side surfaces of the multiple light-emitting elements.

[0190] According to another aspect of this disclosure, a display device is provided. This display device includes: a substrate having defined a plurality of pixels, each comprising a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed on the bonding layer, each comprising a first electrode and a second electrode in one of the sub-pixels; a first planarization layer disposed on the bonding layer and configured to partially surround a plurality of side surfaces of the light-emitting elements; a first connecting electrode disposed on the first planarization layer and configured to connect the first electrode and the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and having a height decreasing toward the light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode and the power line.

[0191] The passivation layer may surround the light-emitting elements and expose a portion of the first connection electrode. The height of the lowest point of the top surface of the second planarization layer may be higher than the height of the highest point of the top surface of the exposed portion of the first connection electrode.

[0192] The passivation layer may include an opening that exposes the first planarization layer. The second planarization layer includes an opening that overlaps with the opening of the passivation layer and has a width smaller than that of the opening of the passivation layer. The second planarization layer is disposed in the opening of the passivation layer and separates the first connection electrode from the second connection electrode.

[0193] Each of these pixels may include a first region in which a third connection electrode is electrically connected to a power line, and a second region spaced apart from the first region. The third connection electrode in the first region may be connected to the power line via the second reflective electrode and the second connection electrode. The third connection electrode in the second region may be connected to the power line via a second connection electrode extending from the first region.

[0194] The bonding layer may include contact holes disposed in the first region and exposing the second reflective electrode. The first planarization layer may include contact holes disposed in the first region and overlapping the contact holes of the bonding layer. The second connecting electrode may be connected to the second reflective electrode via the contact holes of the first planarization layer and the contact holes of the bonding layer.

[0195] The passivation layer includes contact holes located in the first region. These contact holes overlap with those of the first planarization layer and the bonding layer, exposing the contact holes of the second connecting electrode. The second planarization layer also includes contact holes located in the first region. These contact holes overlap with those of the first planarization layer, the bonding layer, and the passivation layer, exposing the second connecting electrode. A third connecting electrode is connected to the second connecting electrode via the contact holes of the second planarization layer, the passivation layer, the first planarization layer, and the bonding layer.

[0196] The passivation layer may further include contact holes, which are disposed in the second region and expose a second connection electrode extending from the first region. The second planarization layer further includes contact holes, which are disposed in the second region and expose a second connection electrode extending from the first region. A third connection electrode is connected to the second connection electrode via the contact holes in the passivation layer and the second planarization layer disposed in the second region.

[0197] The display device may further include an illumination detection area disposed in each of the pixels, wherein an illumination detection pattern is disposed on a second planarization layer in the illumination detection area. A passivation layer may include contact holes disposed in the illumination detection area and exposing a first connection electrode. The second planarization layer may include contact holes overlapping the contact holes of the passivation layer and exposing a first connection electrode. The illumination detection pattern may be connected to the first connection electrode via the contact holes of the second planarization layer and the contact holes of the passivation layer.

[0198] The passivation layer and the first connecting electrode may also have a reduced height toward the light-emitting elements.

[0199] The side surfaces of these light-emitting elements may be any one or both of the two side surfaces of these light-emitting elements.

[0200] Although the foregoing examples and embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of this disclosure. Therefore, the foregoing examples and embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above examples and embodiments are illustrative in all respects and do not limit this disclosure. All technical concepts within the equivalent scope of this disclosure should be understood to be within the scope of this disclosure.

[0201] 100: Display device PN: Display panel GD: Gate Driver DD: Data Drive TC: Timing Controller SP: Subpixel PX: pixel AA: Display area NA: Non-display area SL: Scan line DL: Data Line LED: Light-emitting element 120: First light-emitting element 121: First semiconductor layer 122: Emissive Layer 123: Second semiconductor layer 124: First electrode 125: Second electrode 126: Passivation film 130: Second light-emitting element 140: Third light-emitting element CA1: First contact area CA2: Second contact area APA: Lighting Inspection Area 110:Substrate 111: Buffer layer 112: Gate insulation layer 113a: First interlayer insulation layer 113b: Second interlayer insulation layer 114a: First passivation layer 114b: Second passivation layer 114b': Second first passivation material layer 114b'': Second passivation material layer 114b''': Second and third passivation layers 115: Covering layer 116: Bonding layer 117a: First planarization layer 117b: Second planarization layer 117b': Second first planarization material layer 117b'': Second planarization material layer 117b''': Second and third planarization material layers 118: Embankment 119: Third planarization layer DT: Driver Transistor ACT: Active Layer GE: Gate electrode SE: Source electrode DE: Drain electrode RE: Reflective Electrode RE1: First reflective electrode RE2: Second reflective electrode LS: Light-shielding layer LE: Auxiliary electrode CE': Connecting electrode material layer CE1: First connecting electrode CE2: Second connecting electrode CE3: Third connecting electrode Cst: Capacitor Cst1: First capacitor electrode Cst2: Second capacitor electrode VDD: Power cord TM: Intermediate Electrode APP: Lighting Detection Pattern PP: Protective Pattern CH1: First contact hole CH2: Second contact hole CH3: Third contact hole CH4: Fourth contact hole CH4': Initial fourth contact hole CH5: Fifth contact hole CH6: Sixth contact hole CH6': Initial sixth contact hole CH7: Seventh Contact Hole CH8: Eighth Contact Hole CH8': Initial eighth contact hole OP1: First opening section OP2: Second opening section OP2': Initial second opening section

Claims

1. A display device comprising: a substrate having a plurality of sub-pixels defined thereon; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed in the sub-pixels on the bonding layer and including a first electrode and a second electrode; a first planarization layer disposed on the bonding layer and configured to partially surround a plurality of side surfaces of the light-emitting elements; and a first connection electrode disposed on the first planarization layer and configured to... To connect the first electrode and the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode and connected to the second reflecting electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and configured to partially surround the side surfaces of the light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode and the power line, wherein the passivation layer exposes one end of the first connecting electrode, the first connecting electrode is configured to surround a portion of one side surface of one of the light-emitting elements, and wherein the second planarization layer covers the end of the first connecting electrode.

2. The display device as claimed in claim 1, wherein the second planarization layer is configured to cover the end of the first connection electrode and one end of the passivation layer corresponding to the end of the first connection electrode.

3. The display device as claimed in claim 2, wherein the tilting direction of the end of the first connecting electrode and the end of the passivation layer disposed on the side surface of the light-emitting element is the same as the tilting direction of the second planarization layer covering the end of the first connecting electrode and the end of the passivation layer, and wherein the second planarization layer defines a "V" shape in a region contacting the light-emitting element.

4. The display device as claimed in claim 1, wherein the height of a portion of the second planarization layer overlapping the end of the first connecting electrode is lower than the height of a portion of the second planarization layer not overlapping the end of the first connecting electrode.

5. The display device as claimed in claim 1, wherein the passivation layer includes a first opening portion exposing the first planarization layer, wherein the second planarization layer includes a second opening portion overlapping the first opening portion, wherein the width of the first opening portion is greater than the width of the second opening portion, and wherein the second planarization layer is disposed in the first opening portion and covers the other end of the first connecting electrode and the end of the second connecting electrode.

6. The display device as claimed in claim 5, wherein the third connection electrode is disposed in the first opening portion and the second opening portion and is configured to contact the first planarization layer.

7. The display device as claimed in claim 1, wherein the bonding layer includes a first contact hole exposing the second reflective electrode, wherein the first planarization layer includes a second contact hole overlapping the first contact hole and exposing the second reflective electrode, wherein the second connecting electrode is disposed in the first contact hole and the second contact hole and is in contact with the second reflective electrode, wherein the passivation layer includes a third contact hole overlapping the first contact hole and the second contact hole and exposing the second connecting electrode, wherein the second planarization layer includes a fourth contact hole overlapping the first contact hole, the second contact hole and the third contact hole and exposing the second connecting electrode, and wherein the third connecting electrode is disposed in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole and is in contact with the second connecting electrode.

8. The display device as claimed in claim 7, wherein the width of the third contact hole is greater than the width of the fourth contact hole, and wherein the second planarization layer is disposed in the third contact hole and covers the end of the passivation layer.

9. The display device as claimed in claim 1, wherein the bonding layer includes a first contact hole that exposes the second reflective electrode, wherein the first planarization layer includes a second contact hole that overlaps with the first contact hole and exposes the second reflective electrode, wherein the second connecting electrode is disposed in the first contact hole and the second contact hole and contacts the second reflective electrode, wherein the passivation layer includes a fifth contact hole that exposes the second connecting electrode without overlapping with the first contact hole and the second contact hole, wherein the second planarization layer includes a sixth contact hole that overlaps with the fifth contact hole, and wherein the third connecting electrode is disposed in the fifth contact hole and the sixth contact hole and contacts the second connecting electrode.

10. The display device as claimed in claim 9, wherein the width of the fifth contact hole is greater than the width of the sixth contact hole, and wherein the second planarization layer is disposed in the fifth contact hole and covers the end of the passivation layer.

11. The display device as claimed in claim 1 further comprises: a conductive pattern disposed on the second planarization layer, wherein the passivation layer includes a seventh contact hole that exposes the first connection electrode, wherein the second planarization layer includes an eighth contact hole that overlaps with the seventh contact hole, and wherein the conductive pattern is connected to the first connection electrode via the seventh contact hole and the eighth contact hole.

12. The display device as claimed in claim 11, wherein the width of the seventh contact hole is greater than the width of the eighth contact hole, and wherein the second planarization layer is disposed in the seventh contact hole and covers the end of the passivation layer.

13. The display device as claimed in claim 1, wherein the height of the first planarization layer is lower than the height of the first electrode, and the height of the second planarization layer is lower than the height of the second electrode.

14. A display device comprising: a substrate having a plurality of pixels defined thereon, each of the pixels comprising a plurality of sub-pixels; a power line and a driving transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed on the power line and the driving transistor and spaced apart from each other, the first reflective electrode being connected to the driving transistor and the second reflective electrode being connected to the power line; a bonding layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements disposed in the sub-pixels on the bonding layer and comprising a first electrode and a second electrode; and a first planarization layer. The following components are disposed on the bonding layer and configured to partially surround the side surfaces of the light-emitting elements: a first connecting electrode disposed on the first planarization layer and configured to connect the first electrode to the driving transistor; a second connecting electrode disposed on the first planarization layer, spaced apart from the first connecting electrode and connected to the second reflecting electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and having a height decreasing toward the light-emitting elements; and a third connecting electrode disposed on the second planarization layer and configured to connect the second electrode to the power line.

15. The display device as claimed in claim 14, wherein each of the pixels includes a first region in which the third connection electrode is electrically connected to the power line, and a second region spaced apart from the first region, wherein in the first region, the third connection electrode is connected to the power line via the second reflective electrode and the second connection electrode, and wherein in the second region, the third connection electrode is connected to the power line via the second connection electrode extending from the first region.

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