Memory and related method with improved layout

Abstract

A memory with an improved layout and a related method are disclosed, wherein the memory may include a plurality of memory cells, each memory cell may include a data transistor, the data transistor may include a drain terminal, the drain terminal may include a connecting plate, and the connecting plate may be formed of a metal layer. The shape of the connecting plate may include a first stepped edge, the first stepped edge may be located between two vertices, and one of the two vertices may be a concave vertex.

Claims

1. A memory with an improved layout, comprising: one or more bit lines; one or more word lines; and a plurality of memory cells; wherein: Each memory cell includes a data transistor; the data transistor includes a drain terminal, a gate terminal, and a source terminal; the gate terminal and the source terminal are respectively coupled to one of the one or more word lines and a predetermined voltage, and the data transistor is programmed to store a data bit by whether the drain terminal is hardwired to one of the one or more bit lines; the drain terminal includes a connection plate, and the connection plate is formed of a metal layer; the metal layer is above a surface of a substrate; on the surface of the substrate, a projection of the connection plate includes a first stepped edge, and the first stepped edge is located between two vertices; and one of the two vertices is a concave vertex.

2. For the memory requested in item 1, where: The other of these two vertices is a convex vertex.

3. The memory for request item 1, where: The two vertices of the first step edge are a second vertex and a third vertex; the projection of the connecting plate further includes a first edge and a third edge; the first edge is located between a first vertex and the second vertex; the third edge is located between the third vertex and a fourth vertex; and the lengths of the first edge and the third edge are different.

4. The memory for request item 3, wherein: Both the first edge and the third edge are longer than the first step edge.

5. The memory for request item 1, where: The projection of the connecting plate further includes a second stepped edge; the second stepped edge is located between a sixth vertex and a seventh vertex; and one of the sixth vertex and the seventh vertex is a concave vertex.

6. The memory for request item 5, wherein: The sixth vertex and the other of the seventh vertex are convex vertices.

7. The memory for request item 5, wherein: The projection of the connecting plate further includes a fifth edge and a seventh edge; the fifth edge is located between a fifth vertex and a sixth vertex; the seventh edge is located between the seventh vertex and an eighth vertex; and the lengths of the fifth edge and the seventh edge are different.

8. The memory for request item 7, where: Both the fifth edge and the seventh edge are longer than the second step edge.

9. The memory for request item 1, wherein: The two vertices of the first step edge are a second vertex and a third vertex; the projection of the connecting plate further includes a first edge, a third edge, a second step edge, a fifth edge, and a seventh edge; the first edge is located between a first vertex and the second vertex; the third edge is located between the third vertex and a fourth vertex; the second step edge is located between a sixth vertex and a seventh vertex; one of the sixth vertex and the seventh vertex is a concave vertex; the fifth edge is located between a fifth vertex and the sixth vertex; the seventh edge is located between the seventh vertex and an eighth vertex; for a geometrically infinite straight line collinear with the first step edge, the fourth vertex and the fifth vertex are located on the same side of the geometrically infinite straight line; and the lengths of the first edge and the fifth edge are substantially equal.

10. The memory for request item 9, wherein: The third vertex and the seventh vertex are concave vertices; and the first edge is longer than the third edge.

11. The memory for request item 1, wherein: The two vertices of the first stepped edge are a second vertex and a third vertex; the projection of the connecting plate further includes a second stepped edge; the second stepped edge is located between a sixth vertex and a seventh vertex; one of the sixth vertex and the seventh vertex is a concave vertex; the data transistor further includes a body electrode, and the body electrode is formed by doping a predetermined region of the surface of the substrate; on the surface of the substrate, one of the first stepped edge and the second stepped edge is located within the predetermined region of the surface of the substrate.

12. The memory for request item 11, wherein: The first stepped edge and the other of the second stepped edges are located outside the predetermined area on the surface of the substrate.

13. The memory for request item 11, wherein: The projection of the connecting plate further includes a first edge, a third edge, a fifth edge, and a seventh edge; the first edge is located between a first vertex and a second vertex; the third edge is located between the third vertex and a fourth vertex; the fifth edge is located between the fifth vertex and a sixth vertex; the seventh edge is located between the seventh vertex and an eighth vertex; for a geometrically infinite straight line collinear with the first stepped edge, the fourth vertex and the fifth vertex are located on the same side of the geometrically infinite straight line; on the surface of the substrate, the predetermined area of ​​the surface of the substrate includes a bulk electrode edge; the bulk electrode edge intersects with one of the first edge, the third edge, the fifth edge, and the seventh edge; and for a geometrically infinite straight line collinear with the bulk electrode edge, the second vertex, the third vertex, the sixth vertex, and the seventh vertex are located on the same side of the geometrically infinite straight line.

14. The memory for request item 1, wherein: The two vertices of the first stepped edge are a second vertex and a third vertex; the projection of the connecting plate further includes a second stepped edge; the second stepped edge is located between a sixth vertex and a seventh vertex; one of the sixth vertex and the seventh vertex is a concave vertex; the data transistor further includes a gate structure; and on the surface of the substrate, one of the first stepped edge and the second stepped edge is located outside a projection of the gate structure.

15. The memory for request item 14, wherein: One of the second vertex, the third vertex, the sixth vertex, and the seventh vertex lies within the projection of the gate structure.

16. A method for automating the design of a memory by hardware execution, the method comprising: accessing a plurality of memory cells for selection; and, for a memory cell selected from the plurality of memory cells, arranging a plurality of instances of the selected memory cell into the memory; wherein: Each of the plurality of memory cells includes a data transistor; the data transistor includes a gate terminal and a drain terminal; the gate terminal is used to connect to a word line, the drain terminal includes a connecting plate, and the connecting plate is formed of a metal layer; the layout of the connecting plates of the plurality of memory cells is substantially congruent; and the lengths of the gate terminals of the plurality of memory cells are different from each other.

17. As in request item 16, where: This memory is a read-only memory with a via layer programmable structure.

18. The method of claim 16 further comprises: programming the data transistor to store a data bit of a first value or a second value by arranging or not arranging a conductive connection between the connection plate and a bit line.

19. As in request item 16, where: The connection plates of each of the multiple memory cells are arranged in a concave polygon shape.

20. As in request item 19, where: The concave polygon contains two concave vertices; and the two concave vertices are not adjacent to each other.

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