Semiconductor structure and manufacturing method thereof

TWI943661BActive Publication Date: 2026-10-21WINBOND ELECTRONICS CORP
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Patent Information

Application Number
TW114135478
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-09-16
Publication Date
2026-10-21
Estimated Expiration
2045-09-15

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    Figure TWG2TB001917398_003
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Abstract

A semiconductor structure includes a substrate, a substrate via, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The substrate includes a first surface and a second surface opposite to each other. The substrate via is located within the substrate. The first dielectric layer is located between the substrate via and the substrate. The second dielectric layer is located between the first dielectric layer and the substrate via. The third dielectric layer is located between the first dielectric layer and the substrate via. The second dielectric layer is closer to the first surface than the third dielectric layer. The second dielectric layer connects to the substrate via, the first dielectric layer, and the third dielectric layer. The third dielectric layer abuts against the second dielectric layer in a direction perpendicular to the first surface.
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Claims

1. A semiconductor structure, comprising: The base includes the first and second surfaces that are opposite to each other; A substrate perforation is located within the substrate; A first dielectric layer is located between the substrate via and the substrate; The second dielectric layer is located between the first dielectric layer and the substrate via; A third dielectric layer is located between the first dielectric layer and the substrate via, wherein the second dielectric layer is closer to the first surface than the third dielectric layer, the second dielectric layer is connected to the substrate via, the first dielectric layer and the third dielectric layer, and the third dielectric layer abuts against the second dielectric layer in a direction perpendicular to the first surface.

2. The semiconductor structure as claimed in claim 1, wherein a portion of the third dielectric layer is located between the second dielectric layer and the substrate via.

3. The semiconductor structure as claimed in claim 1, wherein the material of the first dielectric layer is the same as the material of the third dielectric layer.

4. The semiconductor structure as claimed in claim 1, wherein the material of the second dielectric layer is different from the material of the first dielectric layer and the material of the third dielectric layer.

5. The semiconductor structure of claim 1, wherein the first dielectric layer extends through the entire substrate, the second dielectric layer extends from the first surface toward the second surface and does not extend through the entire substrate, and the third dielectric layer extends from the second surface toward the first surface and does not extend through the entire substrate.

6. The semiconductor structure of claim 1, wherein the second dielectric layer includes a first connection portion, the third dielectric layer includes a second connection portion, the second connection portion is located between the first connection portion and the substrate via, and the first connection portion is connected to the second connection portion in a direction perpendicular to the first surface.

7. The semiconductor structure of claim 6, wherein the cross-sectional shape of the first connection portion and the cross-sectional shape of the second connection portion include a tapered shape.

8. The semiconductor structure of claim 6, wherein the first connection portion has a first bevel, the second connection portion has a second bevel, and the first bevel directly contacts the second bevel.

9. The semiconductor structure of claim 6, wherein the first connection has a first tip, the second connection has a second tip, and the first tip is closer to the second surface than the second tip.

10. The semiconductor structure of claim 6, wherein the width of the first connection portion decreases in a direction away from the first surface, and the width of the second connection portion decreases in a direction away from the second surface.

11. The semiconductor structure of claim 1, wherein the substrate via extends through the entire substrate.

12. The semiconductor structure of claim 1, wherein the material of the first dielectric layer comprises an oxide, the material of the second dielectric layer comprises a nitride, and the material of the third dielectric layer comprises an oxide.

13. The semiconductor structure of claim 1, wherein the substrate via includes a barrier layer and a conductive layer, and the barrier layer is located between the conductive layer and the substrate.

14. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate includes a first surface and a second surface that are opposite to each other; A substrate perforation is formed in the substrate; A first dielectric layer is formed between the substrate perforation and the substrate; A second dielectric layer is formed between the first dielectric layer and the substrate via; and a third dielectric layer is formed between the first dielectric layer and the substrate via, wherein the second dielectric layer is closer to the first surface than the third dielectric layer, the second dielectric layer is connected to the substrate via, the first dielectric layer and the third dielectric layer, and the third dielectric layer abuts against the second dielectric layer in a direction perpendicular to the first surface.

15. A method for manufacturing a semiconductor structure as claimed in claim 14, wherein the method for forming the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises: An opening is formed in the substrate, wherein the opening extends through the entire substrate; A first dielectric material layer is formed on the first surface and in the opening; A second dielectric material layer is formed on the first dielectric material layer, wherein the second dielectric material layer located in the opening is only located at the upper part of the opening, and the second dielectric material layer exposes a portion of the first dielectric material layer located in the opening; A third dielectric material layer is formed on the first dielectric material layer and the second dielectric material layer; The third dielectric layer is formed by removing the portion of the third dielectric material layer located outside the opening, the portion of the third dielectric material layer located at the top of the opening, and the portion of the third dielectric material layer located at the bottom of the opening. And remove a portion of the first dielectric material layer and a portion of the second dielectric material layer located outside the opening to form the first dielectric layer and the second dielectric layer.

16. A method of manufacturing a semiconductor structure as claimed in claim 15, wherein during the process of removing a portion of the third dielectric material layer located outside the opening, a portion of the third dielectric material layer located at the top of the opening, and a portion of the third dielectric material layer located at the bottom of the opening, a portion of the second dielectric material layer and a portion of the first dielectric material layer located at the bottom of the opening are simultaneously removed.

17. A method for manufacturing a semiconductor structure as claimed in claim 14, wherein the method for forming a substrate through-hole comprises: A substrate perforation material layer is formed on the second dielectric material layer and the third dielectric layer, wherein the substrate perforation material layer fills the opening; And removing a portion of the substrate perforated material layer located outside the opening to form the substrate perforation.

Citation Information

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