Display device

Abstract

A display device includes: a display panel including a first region and at least one second region; a gate line arranged along a first direction in the first region and at least one second region; a first data line arranged along a second direction perpendicular to the first direction in the first region; a second data line arranged along the second direction in at least one second region and having a length shorter than the length of the first data line; a vertical connecting line arranged along the second direction in the first region; and a horizontal connecting line arranged along the first direction in the first region and at least one second region, wherein each of the vertical connecting lines is electrically connected to a corresponding second data line through a corresponding horizontal connecting line, and each of the vertical connecting lines has a length inversely proportional to the length of each of the second data lines to be connected.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device having a minimal bezel area and easily compensating for storage capacity. Prior Technology

[0002] With the development of information technology, the field of display devices for displaying information is developing rapidly, and various display devices with beneficial features (such as thinness, lightness and low power consumption) are being developed.

[0003] In such display devices, the communication lines used to apply various signals to the display area are arranged outside the display area of ​​the displayed image. These communication lines are the main reason for increasing the bezel area of ​​the display device.

[0004] The description of prior art should not be construed as prior art simply because it is mentioned or associated with in this section. The description of prior art contains information describing one or more aspects of the subject matter, and the description in this section does not limit the scope of the invention. Summary of the Invention

[0005] Accordingly, one or more embodiments of this disclosure are directed to a display device, which substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0006] One aspect of this disclosure is to provide a display device that can prevent image quality degradation by compensating for changes in storage capacity caused by freeform or irregular shapes.

[0007] Another aspect of this disclosure is to provide a display device that can minimize the bezel area by arranging a correction component for correcting storage capacity deviation in the display area.

[0008] Other features and aspects will be set forth in the following description, and some will be obvious from the description or may be learned by practicing the disclosed concepts provided herein. Other features and aspects of the disclosed concepts may be realized and achieved through the structures specifically pointed out in the specification, or derived therefrom, and through the scope of this application and its drawings.

[0009] To achieve these and other aspects, as embodied and broadly described, in one aspect, this disclosure provides a display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first region and at least one second region; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in at least one second region and having a length shorter than the length of the first data lines; a plurality of vertical interconnecting lines arranged along the second direction in the first region; and a plurality of horizontal interconnecting lines arranged along the first direction in the first region and at least one second region, wherein each of the vertical interconnecting lines is electrically connected to a corresponding second data line through a corresponding horizontal interconnecting line, and each of the vertical interconnecting lines has a length inversely proportional to the length of each of the second data lines to be connected.

[0010] In one embodiment, the data signal can be applied directly to each of the first data lines, and the data signal can be applied to each of the second data lines through the corresponding vertical and horizontal interconnects.

[0011] The display device may further include: a first contact hole that electrically connects each of the vertical interconnects to the corresponding horizontal interconnect; and a second contact hole that electrically connects each of the horizontal interconnects to the corresponding second data line.

[0012] The display device may further include: a thin-film transistor disposed in the first region and at least one second region; and a light-emitting diode disposed on the thin-film transistor.

[0013] A thin-film transistor may include: a semiconductor layer disposed on a substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the gate electrode.

[0014] The display device may further include: a gate insulating layer disposed between the semiconductor layer and the gate electrode; an interlayer insulating layer disposed between the gate electrode and the source electrode and the drain electrode; a planarization layer disposed on the source electrode and the drain electrode; and a connection pattern disposed on the planarization layer and connected to one of the source electrode and the drain electrode.

[0015] The vertical interconnects may be arranged on the planarization layer, and the horizontal interconnects may be arranged on the interlayer insulating layer. The vertical interconnects may contain the same material as the connection pattern, and / or the horizontal interconnects may contain the same material as the source electrode and the drain electrode. In an embodiment, each of the vertical interconnects may be electrically connected to a corresponding horizontal interconnect through a first contact hole disposed in the planarization layer.

[0016] Each of these vertical connecting lines may extend a predetermined distance from the first contact hole, and the predetermined distance of each of these vertical connecting lines may be inversely proportional to the length of each of the second data lines to be connected.

[0017] The distance between the horizontal connecting lines connected to the second data lines can increase as the length of the second data lines decreases.

[0018] The display panel can be in a free form.

[0019] The first region can be a rectangular region, and at least one second region can be a non-rectangular region.

[0020] The display panel may be circular.

[0021] The first region can be the central region of the circle, and at least one second region can be the regions on either side of the central region.

[0022] These vertical connecting lines may not be arranged in the second area.

[0023] These first data lines can be formed to have the same length.

[0024] In another aspect, this disclosure provides a display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first region and at least one second region; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in at least one second region and having a length shorter than the length of the first data lines; a plurality of vertical interconnecting lines arranged along the second direction in the first region; a plurality of horizontal interconnecting lines arranged along the first direction in the first region and at least one second region; and a plurality of compensating interconnecting lines extending from the vertical interconnecting lines, wherein each of the vertical interconnecting lines is electrically connected to a corresponding second data line through a corresponding horizontal interconnecting line, and each of the compensating interconnecting lines has a length inversely proportional to the length of a corresponding second data line to be connected.

[0025] In another aspect, this disclosure provides a display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first region and the at least one second region; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in the at least one second region and having a length shorter than the length of the first data lines; a plurality of vertical connecting lines arranged along the second direction in the first region; and a plurality of horizontal connecting lines arranged along the first direction in the first region and the at least one second region, wherein the distance between the horizontal connecting lines is inversely proportional to the length of one of the second data lines connected to the respective horizontal connecting lines.

[0026] In one or more embodiments, image quality degradation can be prevented by compensating for differences in storage capacity caused by differences in the length of data lines arranged in freeform or irregular areas in the display device.

[0027] In addition, the display device can minimize its bezel area by arranging a correction pattern used to correct storage capacity deviations in the display area.

[0028] Because storage capacity deviations are corrected to prevent image quality degradation, low power consumption is achieved due to high efficiency.

[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concepts. Simple Explanation of the Diagram

[0030] The drawings are included to provide a further understanding of the disclosure and are incorporated into and form part of this application. These drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. Figure 1 shows a block diagram of a display device according to one or more embodiments of the present disclosure; Figure 2 shows a block diagram of a sub-pixel in a display device according to one or more embodiments of the present disclosure; Figure 3 shows a circuit diagram of a sub-pixel in a display device according to one or more embodiments of the present disclosure; Figure 4 shows a plan view of a display device according to an embodiment of the present disclosure; Figure 5 shows the circuit arrangement in the display area of ​​a display device according to an embodiment of the present disclosure; Figure 6A shows a schematic cross-sectional view of the display device taken along line I-I' in Figure 4; Figure 6B shows a schematic cross-sectional view of the display device taken along line II-II' in Figure 5; and Figure 7 shows the circuit arrangement in the display area of ​​a display device according to another embodiment of the present disclosure. Implementation

[0031] The advantages and features of this disclosure, as well as the methods for achieving such advantages and features, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which it pertains.

[0032] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings for the purpose of describing embodiments of this disclosure are merely illustrative examples, and therefore this disclosure is not limited to the illustrated examples. Unless otherwise specified, throughout this disclosure, the same element symbols refer to the same components. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted or briefly discussed where such descriptions might unnecessarily obscure the essence of this disclosure.

[0033] When terms such as "comprising," "having," and "including" are used in this disclosure, additional parts may be added unless a more restrictive term such as "only" is used herein. Furthermore, when a component is expressed as singular, it includes multiples, and vice versa, unless otherwise specified. For example, an element may be one or more elements. An element may contain multiple elements. The word "exemplary" is used to mean as an example or illustration. An embodiment is an exemplary embodiment. A layer is an exemplary layer. In one or more embodiments, "embodiment," "example," "layer," etc., should not be construed as superior to or better than other embodiments. An embodiment, an example, an exemplary embodiment, a layer, etc., may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more layers, etc., unless otherwise stated. Furthermore, the term "may" includes all the meanings of the term "can."

[0034] When analyzing a component, even if it is not explicitly described, it should be interpreted as including a range of errors.

[0035] When describing positional relationships, for example, when the positional relationship between two parts / layers is described as "above", "up", "above", "below", "below", "next to", etc., one or more other parts / layers may be provided between the two parts / layers unless more restrictive terms such as "immediately" or "directly" are used.

[0036] When describing temporal relationships, such as when temporal sequence is described as "after", "following", "next", "before", etc., discontinuous or sequential situations may be included unless more restrictive terms such as "immediately" or "directly" are used.

[0037] Although the terms first, second, etc., may be used to describe various components, these components are not substantially limited by these terms. These terms are only used to distinguish one component from another and may not limit any particular order or sequence. Therefore, the first component described below may substantially be the second component, and vice versa, within the spirit of the technical disclosure.

[0038] In describing the components of this disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are intended only to distinguish these components from other components, and the nature, order, sequence, or number of these components are not limited by these terms. When describing a component as "connected," "coupled," or "attached" to another component, it should be understood that the component may be directly "connected," "coupled," or "attached" to the other component, but other components may also "intervene" between each component, or each component may be "connected," "coupled," or "attached" through another component.

[0039] The features of the various embodiments disclosed herein may be combined or integrated with each other in part or in whole. Various interlocks and drives are technically possible, and each embodiment may be implemented independently of each other or together in a mutual dependency relationship.

[0040] All components of each display device according to all embodiments of this disclosure are operatively coupled and configured.

[0041] As used herein, "display device" may include a display device in the narrow sense, such as a display module that includes a display panel and a driving unit for driving the display panel. Furthermore, the display device may also include complete electronic devices or assemblies, such as notebook computers, televisions, computer monitors, automotive displays, or other forms of vehicles, which are complete products (or final products) including display modules, device displays, mobile electronic devices (such as smartphones or tablets), etc.

[0042] Therefore, the display device in this disclosure may include the display device itself (e.g., a display module) in a narrow sense, as well as an application product or end-consumer device assembly that includes a display module.

[0043] This disclosure is applicable to various display devices. For example, it can be applied to organic light-emitting display devices, liquid crystal display devices, electrophoretic display devices, quantum dot display devices, micro-light-emitting diode (LED) display devices, and mini LED display devices. For ease of explanation, an example of an organic light-emitting display device may be described. However, this disclosure is not limited to organic light-emitting display devices.

[0044] The aspects disclosed herein will now be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols will be used throughout the drawings to refer to the same or similar parts.

[0045] Figure 1 shows a block diagram of a display device according to the present disclosure. Figure 2 shows a block diagram of a sub-pixel in a display device according to the present disclosure.

[0046] Referring to FIG1, the display device 100 may include an image processor 102, a timing controller 104, a gate driver 106, a data driver 107, a power supply 108, and a display panel 109.

[0047] The image processor 102, together with image data supplied from an external source, outputs drive signals for driving various components. For example, the drive signals output by the image processor 102 may include, but are not limited to, data enable signals, vertical synchronization signals, horizontal synchronization signals, clock signals, etc.

[0048] The timing controller 104 receives drive signals along with image data from the image processor 102. Based on the drive signals input from the image processor 102, the timing controller 104 generates and outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 106 and a data timing control signal DDC for controlling the operating timing of the data driver 107.

[0049] Gate driver 106 outputs a scan signal to display panel 109 in response to a gate timing control signal GDC supplied by timing controller 104. Gate driver 106 outputs the scan signal through multiple gate lines GL1 to GLm (m is an integer greater than or equal to 2). In one embodiment, gate driver 106 may be formed as an integrated circuit (IC), but is not limited thereto. In another embodiment, gate driver 106 may include various gate driving circuits formed directly on display panel 109. In this case, gate driver 106 may be a gate-in-panel (GIP).

[0050] Data driver 107 outputs a data voltage to display panel 109 in response to a data timing control signal DDC input from timing controller 104. Data driver 107 samples and latches a digital data signal DATA supplied from timing controller 104, and converts the digital data signal DATA into an analog data voltage based on gamma voltage. Data driver 107 outputs the data voltage through multiple data lines DL1 to DLn (n is an integer greater than or equal to 2). In one embodiment, data driver 107 may be configured as an IC, but is not limited thereto.

[0051] Power supply 108 outputs a high-potential voltage and a low-potential voltage, and supplies the high-potential voltage and the low-potential voltage to display panel 109. The high-potential voltage is supplied to display panel 109 through the first power line EVDD, and the low-potential voltage is supplied to display panel 109 through the second power line EVSS. Alternatively / additionally, the voltage output from power supply 108 can be output to gate driver 106 and / or data driver 107 to drive drivers 106 and 107.

[0052] The display panel 109 displays images in response to the scan signal supplied by the gate driver 106, the data voltage supplied by the data driver 107, and the power supplied by the power supply 108.

[0053] Display panel 109 includes a plurality of subpixels SP for displaying images. In one embodiment, subpixels SP may include red subpixels (R), green subpixels (G), and blue subpixels (B). Alternatively, subpixels SP may include white subpixels (W), red subpixels (R), green subpixels (G), and blue subpixels (B). In one embodiment, the white subpixels (W), red subpixels (R), green subpixels (G), and blue subpixels (B) may have substantially the same area. Alternatively, the white subpixels (W), red subpixels (R), green subpixels (G), and blue subpixels (B) may have different areas.

[0054] Referring to Figure 2, each sub-pixel SP can be connected to the gate line GL1, the data line DL1, the first power line EVDD, and the second power line EVSS. The number of transistors and capacitors and the driving method can be determined by the configuration of the pixel circuit in the sub-pixel SP. For example, the sub-pixel SP may contain two transistors and one capacitor (2T1C), but is not limited thereto. In another embodiment, the sub-pixel SP may contain 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, etc.

[0055] Figure 3 shows a circuit diagram of a sub-pixel in a display device according to the present disclosure.

[0056] Referring to Figure 3, the display device 100 includes gate lines GL, data lines DL, and power lines PL that intersect each other to define sub-pixels SP. Switching thin-film transistors Ts, driving thin-film transistors Td, storage capacitors Cst, and light-emitting diodes D can be disposed in the sub-pixels SP.

[0057] The switching thin-film transistor Ts is connected to the gate line GL and the data line DL. The driving thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL, and the light-emitting diode D is connected to the driving thin-film transistor Td.

[0058] In the display device 100, when the switching thin-film transistor Ts is turned on by the gate signal applied to the gate line GL, the data signal applied to the data line DL is applied to the gate electrode 114 (FIG. 6A) and the electrode of the storage capacitor Cst through the switching thin-film transistor Ts.

[0059] The driving thin-film transistor Td is turned on by a data signal applied to its gate electrode 114, causing a current proportional to the data signal to be supplied from the power line PL through the driving thin-film transistor Td to the light-emitting diode D. The light-emitting diode D then emits light with a brightness proportional to the current flowing through the driving thin-film transistor Td. In this situation, the storage capacitor Cst is charged with a voltage proportional to the data signal, so that the voltage at the gate electrode 114 in the driving thin-film transistor Td remains constant during one frame. Therefore, the display device 100 can display the desired image.

[0060] In Figure 3, the display device 100 includes two thin-film transistors (a switching thin-film transistor Ts and a driving thin-film transistor Td) and a storage capacitor Cst in the sub-pixel SP. However, the display device 100 may include three or more thin-film transistors and two or more storage capacitors in the sub-pixel SP.

[0061] Figure 4 shows a plan view of a display device according to an embodiment of the present disclosure. Figure 5 shows the wiring arrangement in the display area of ​​the display device according to an embodiment of the present disclosure.

[0062] In one embodiment, the display device 100 may be applied to a freeform display device, but is not limited thereto. As used herein, a freeform display device may refer to a display device having a non-rectangular shape. For example, a freeform display device may be a non-rectangular display device, such as a circular, elliptical, curved, or irregular shape, but is not limited thereto.

[0063] In an exemplary embodiment, the display device 100 may be a free-form display device applicable to various electronic devices (e.g., watches and / or dashboards in vehicles). A display device 100 having a circular shape will be described in more detail below. In another embodiment, the display device 100 may be applied to a display device with corners formed in a circular shape.

[0064] Referring to Figures 4 and 5, a display device according to one embodiment includes a display area AA for displaying a real image and a non-display area NA (i.e., a first non-display area NA1 or a second non-display area NA2) disposed outside the display area AA.

[0065] Multiple gate lines GL1 to GLm and multiple data lines DL1 to DLn are arranged in the display area AA to define multiple sub-pixels SP1, SP2, and SP3. In one embodiment, sub-pixels SP1, SP2, and SP3 may include red sub-pixels (R), green sub-pixels (G), and blue sub-pixels (B). Alternatively / additionally, sub-pixels SP may further include white sub-pixels (W). In one embodiment, sub-pixels SP1, SP2, and SP3 may form a single pixel P.

[0066] Thin-film transistors used to realize the switching elements and display elements of the real image are disposed in each sub-pixel SP1, SP2 or SP3.

[0067] The display element may include various display elements. For example, the display element may include, but is not limited to, organic light-emitting display elements, liquid crystal display elements, quantum dot display elements, micro LED (light-emitting diode) display elements, and mini LED display elements.

[0068] The display area AA can be divided into a first area A1, a second area A2, and a third area A3 along a first direction (horizontal direction, x-axis direction). Furthermore, since the areas on both sides of the first area A1 are referred to as the second area, the second area A2 can be referred to as the left second area, and the third area A3 can be referred to as the right second area.

[0069] Multiple first data lines DL1 and multiple vertical link lines VLINK are arranged along a second direction (vertical direction, y-axis direction) in the first region A1 of the display area AA. In this case, one first data line DL1 and one vertical link line VLINK correspond to one sub-pixel row arranged along the second direction. Each of the multiple sub-pixels arranged in a sub-pixel column is electrically connected to one of the corresponding first data lines DL1 to receive data signals. In this case, the corresponding vertical link line VLINK is not electrically connected to those sub-pixels arranged in the sub-pixel column.

[0070] The second area A2 and the third area A3 of the display area AA are located on both sides of the first area A1. Multiple second data lines DL2 and multiple third data lines DL3 extending along the second direction (vertical direction, y-axis direction) are respectively arranged in the second area A2 and the third area A3. The vertical connecting line VLINK is not arranged in the second area A2 and the third area A3.

[0071] Multiple first data lines DL1 arranged in the first region A1 are formed to have the same length as those from the lower end to the upper end of the circular display region AA. The length of the second data line DL2 arranged in the second region A2 decreases from the central region outwards, that is, from the boundary of the first region A1 to the left end. Furthermore, the length of the third data line DL3 arranged in the third region A3 decreases from the central region outwards, that is, from the boundary of the first region A1 to the right end.

[0072] Multiple horizontal interconnect lines (HLINKs) are arranged along a first direction (x-axis direction) in the first area A1, the second area A2, and the third area A3 of the display area AA. These horizontal interconnect lines (HLINKs) can be spaced apart from each other at the same interval, but are not limited to this.

[0073] Each horizontal interconnect line HLINK is electrically connected to the corresponding vertical interconnect line VLINK in the first region A1 through the first contact hole CNT1. An insulating layer is provided between each horizontal interconnect line HLINK and the second data line DL2 in the second region A2 and the third data line DL3 in the third region A3, and they are electrically connected through the second contact hole CNT2.

[0074] In Figure 4, the vertical connecting lines VLINK and the horizontal connecting lines HLINK are disposed on one side of sub-pixels SP1, SP2, and SP3. In another embodiment, the vertical connecting lines VLINK and the horizontal connecting lines HLINK may be configured to span across sub-pixels SP1, SP2, and SP3.

[0075] The leftmost vertical link VLINK in Zone A1 can be electrically connected via horizontal link HLINK to the nearest second data line DL2 in Zone A2, which is the rightmost second data line DL2 in Zone A2. Furthermore, the second vertical link VLINK from the leftmost position in Zone A1 can be electrically connected via horizontal link HLINK to the second second data line DL2 from the rightmost position in Zone A2, but this is not the only connection.

[0076] The rightmost vertical link VLINK in Zone A1 can be electrically connected via horizontal link HLINK to the nearest third data line DL3 in Zone A3, which is the leftmost third data line DL3 in Zone A3. Furthermore, the second vertical link VLINK from the right in Zone A1 can be electrically connected via horizontal link HLINK to the second third data line DL3 from the left in Zone A3, but this is not a limitation.

[0077] Gate drivers 106 (FIG. 1) that apply various signals to sub-pixels SP1, SP2, and SP3 can be disposed in a first non-display area NA1 surrounding the display area AA. Gate drivers 106 apply scan signals to sub-pixels SP1, SP2, and SP3 through gate lines GL1 to GLm (FIG. 1). In one embodiment, gate driver 106 can be a GIP circuit, wherein the gate driving circuit is directly disposed on substrate 140 (FIG. 6A and 6B).

[0078] A curved region BA extending from the first non-display area NA1 may be formed at the lower end of the first non-display area NA1. The curved region BA may be curved by bending in a specific direction. The second non-display area NA2 is the region extending from the curved region BA. A flexible circuit film FPC is attached to the second non-display area NA2.

[0079] Since the flexible circuit film FPC is disposed on the lower surface of the display device 100 by bending the bending area BA, the bezel of the display device 100 can be reduced.

[0080] The driving element DR is mounted on a flexible circuit film FPC, and various circuits can be formed in the flexible circuit film FPC to supply data signals output from the driving element DR and various signals output from the outside to the display area AA. In one embodiment, the driving element DR can be directly mounted in the second non-display area NA2.

[0081] Multiple data link lines (DLINK) and multiple signal link lines (SLINK) are located in the second non-display area NA2 and the curved area BA.

[0082] The data link lines (DLINK) are electrically connected to the first data line (DL1) in the first region A1. The signal link lines (SLINK) are electrically connected to the vertical link line (VLINK) in the first region A1. The connection between the data link lines (DLINK) and the first data line (DL1), and the connection between the signal link lines (SLINK) and the vertical link line (VLINK), can be made through pad electrodes. Data signals are applied to the data link lines (DLINK) and the signal link lines (SLINK), respectively.

[0083] Data signals are applied directly to the first data line DL1 in the first region A1 of display area AA via data link DLINK, supplying data signals to multiple sub-pixels SP1, SP2, and SP3 in the sub-pixel column corresponding to the first region A1. Data signals are applied to the second data line DL2 in the second region A2 of display area AA via signal link SLINK, vertical link VLINK, and horizontal link HLINK, supplying data signals to multiple sub-pixels SP1, SP2, and SP3 in the sub-pixel column corresponding to the second region A2. Data signals are applied to the third data line DL3 in the third region A3 of display area AA via signal link SLINK, vertical link VLINK, and horizontal link HLINK, supplying data signals to multiple sub-pixels SP1, SP2, and SP3 in the sub-pixel column corresponding to the third region A3.

[0084] In the display device 100 disclosed herein, the connecting lines for supplying data signals to the sub-pixels SP1, SP2 and SP3 in the second region A2 and the third region A3 are not provided in the non-display region NA, but are provided in the display region AA. Each of the second region A2 and the third region A3 is located outside the first direction (width direction, x-axis direction) of the curved region BA and the second non-display region NA2, thus minimizing the border area.

[0085] A compensation link (COLINK) is formed to each of the vertical links (VLINK). In one embodiment, the compensation link (COLINK) may be formed by extending from each of the vertical links (VLINK). Since the vertical links (VLINK) extend from the lower end of the display area AA to the first contact hole (CNT1), the compensation link (COLINK) may be formed by extending a predetermined distance (ℓ) from the first contact hole (CNT1) along the second direction (y-axis direction).

[0086] In this way, the compensation tie line COLINK is formed by extending from the vertical tie line VLINK. This is to compensate for the storage capacity of the data line DL to eliminate storage capacity discrepancies between data lines of different lengths.

[0087] In the freeform or non-rectangular display device 100, the length of the data line DL varies depending on the position, and in particular, the data signal is applied to the sub-pixels SP1, SP2 and SP3 using the vertical interconnect line VLINK and the horizontal interconnect line HLINK, so that the storage capacity formed in the data line DL varies depending on the position.

[0088] This difference in storage capacity is the main cause of image quality degradation by leading to distortion of the displayed image. Various methods can be used to eliminate the difference in storage capacity between data lines DL. For example, parasitic capacitance can be generated by forming an independent metal pattern in the first non-display area NA1 to compensate for the storage capacity. However, in this case, since the metal pattern increases the area of ​​the first non-display area NA1, there is a problem of an increase in the bezel area of ​​the display device 100.

[0089] In this disclosure, the increased border area caused by a single metal pattern can be prevented by arranging the compensation contact line COLINK in the display area AA.

[0090] The compensation link COLINK can be formed as an extension from the vertical link VLINK. In one embodiment, the length ℓ of the compensation link COLINK is inversely proportional to the length of the second data line DL2 in the second region A2 and the length of the third data line DL2 in the third region A3.

[0091] The reason for the storage capacity deviation in the second data line DL2 and the third data line DL3 is that the lengths of the second data line DL2 and the third data line DL3 are shorter than the length of the first data line DL1. Since the storage capacity difference between the first data line DL1 and the second data line DL2 and the third data line DL3 increases as the relative lengths of the second data line DL2 and the third data line DL3 become shorter, the length ℓ of the compensation link COLINK used to compensate for the storage capacity difference must be inversely proportional to the length of the second data line DL2 in the second region A2 and the length of the third data line DL3 in the third region A3.

[0092] That is, the longest length of the compensation connection line COLINK is the vertical connection line VLINK that extends from the shortest second data line DL2 and third data line DL3, which are respectively set on the outermost side of the second region A2 and the third region A3. The length of these compensation connection lines COLINK gradually shortens from the outermost side of the second region A2 and the third region A3 toward the first region A1 (that is, as the length of the second data line DL2 and the third data line DL3 increases).

[0093] As mentioned above, in the display device 100, the pattern used to compensate for the changes in storage capacity caused by the length differences of the data lines DL is not set in the non-display area NA of the display device 100, but is set in the display area AA, thereby minimizing the border area.

[0094] The configuration of the display device 100 will be described in more detail below with reference to the accompanying drawings.

[0095] FIG. 6A is a schematic cross-sectional view of the display device taken along line I-I' in FIG. 4. FIG. 6B is a schematic cross-sectional view of the display device taken along line II-II' in FIG. 5.

[0096] Referring to FIGS. 6A and 6B, a buffer layer 142 is disposed on a substrate 140. In one embodiment, the substrate 140 may comprise a rigid material such as glass. In another embodiment, the substrate may comprise, but is not limited to, plastic materials, such as polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (PC) and combinations thereof.

[0097] For example, when the substrate 140 comprises polyimide, the substrate 140 may comprise a plurality of polyimide layers, and an inorganic layer may be further disposed between the polyimide layers, but the present disclosure is not limited thereto.

[0098] The buffer layer 142 may be disposed on the entire substrate 140 to improve the adhesion between the plurality of layers disposed on the substrate 140 and the substrate 140, and block alkaline components leaking from the substrate 140, etc. In addition, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 140.

[0099] In one embodiment, the buffer layer 142 may comprise, but is not limited to, inorganic insulating materials, such as silicon oxide (SiOx, wherein 0<x≤2) and silicon nitride (SiNx, wherein 0<x≤2). The buffer layer 142 may have a single-layer structure or a multi-layer structure. For example, the buffer layer 142 may have an alternate lamination structure of silicon nitride (SiNx) layers and silicon oxide (SiOx) layers. In some embodiments, the buffer layer 142 may be omitted depending on the kind and material of the substrate 140 and the structure and / or type of the thin film transistor.

[0100] The thin film transistor T is disposed on the buffer layer 142 in the display area AA. For convenience of explanation, only the driving thin film transistor T among various thin film transistors that can be arranged in the display area AA is shown in FIG. 6A, but other thin film transistors such as switching thin film transistors may be provided. In addition, although FIG. 6A illustrates a thin film transistor having a top gate structure, the structure of the thin film transistor T is not limited thereto, and the thin film transistor T having other structures such as a bottom gate structure may be implemented.

[0101] The thin film transistor T may include a semiconductor layer 112 disposed on the buffer layer 142, a gate insulating layer 144 disposed on the semiconductor layer 112, a gate electrode 114 disposed on the gate insulating layer 144, an interlayer insulating layer 146 disposed on the gate electrode 114, and a source electrode 115 and a drain electrode 116 disposed on the interlayer insulating layer 146.

[0102] In one embodiment, the semiconductor layer 112 may include a polycrystalline semiconductor. For example, the polycrystalline semiconductor may include, but is not limited to, low temperature poly silicon (LTPS) with high mobility.

[0103] In another embodiment, the semiconductor layer 112 may include an oxide semiconductor. For example, the oxide semiconductor may include, but is not limited to, indium-gallium-zinc oxide (IGZO), indium-zinc oxide (IZO), indium-gallium-tin oxide (IGTO), indium-gallium oxide (IGO), and combinations thereof. In some embodiments, the semiconductor layer 112 may include a channel region 112a in a central region, and a source region 112b and a drain region 112c as doped regions on both sides of the channel region 112a.

[0104] In one embodiment, the gate insulating layer 144 may be arranged in the display area AA and the non-display area NA. In another embodiment, the gate insulating layer 144 may be only arranged in the display area AA. For example, the gate insulating layer 144 may include inorganic insulating materials, such as silicon oxide (SiOx, where 0<x≤2) and silicon nitride (SiNx, where 0<x≤2). The gate insulating layer 144 may have a single-layer structure or a multi-layer structure. However, embodiments of the present disclosure are not limited thereto.

[0105] In one embodiment, the interlayer insulating layer 146 may be disposed in the display area AA and the non-display area NA. In another embodiment, the interlayer insulating layer 146 may be disposed only in the display area AA. For example, the interlayer insulating layer 146 may include, but is not limited to, organic materials such as photosensitive acrylic or inorganic insulating materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The interlayer insulating layer 146 may have a single-layer structure or a multi-layer structure. In another embodiment, the interlayer insulating layer 146 may have a multi-layer structure including at least one organic layer and at least one inorganic layer. However, embodiments of the present disclosure are not limited thereto.

[0106] In one embodiment, each of the source electrode 115 and the drain electrode 116 may include, but is not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof or alloys thereof. Each of the source electrode 115 and the drain electrode 116 may have a single-layer structure or a multi-layer structure. However, embodiments of the present disclosure are not limited thereto. The source electrode 115 and the drain electrode 116 may be respectively in contact with the source region 112b and the drain region 112c of the semiconductor layer 112 through contact holes formed in the gate insulating layer 144 and / or the interlayer insulating layer 146.

[0107] The horizontal connection line HLINK is disposed on the interlayer insulating layer 146. In one embodiment, the horizontal connection line HLINK may include the same material as the source electrode 115 and the drain electrode 116, but the present disclosure is not limited thereto.

[0108] In some embodiments, a bottom shielding metal layer may be disposed between the substrate 140 and the semiconductor layer 112. The bottom shielding metal layer may be arranged to minimize the back channel phenomenon caused by charges trapped in the substrate 140, and prevent residual images or deterioration of transistor performance. For example, the bottom shielding metal layer may include, but is not limited to, titanium (Ti), molybdenum (Mo) and alloys thereof. The bottom shielding metal layer may have a single-layer structure or a multi-layer structure.

[0109] The first planarization layer 148 is disposed on the substrate 140 on which the thin film transistor T is disposed. In one embodiment, the first planarization layer 148 may include, but is not limited to, organic materials, for example, photosensitive acrylic. In another embodiment, the first planarization layer 148 may have a multi-layer structure including at least one inorganic layer and at least one organic layer.

[0110] A connection pattern 154 is disposed on the first planarization layer 148. The connection pattern 154 can be electrically connected to one of the source electrode 115 and the drain electrode 116 of the thin-film transistor T through contact holes formed in the first planarization layer 148. For example, the connection pattern 154 may contain a metallic component.

[0111] A vertical link VLINK is disposed on the first planarization layer 148. In one embodiment, the vertical link VLINK may contain, but is not limited to, the same metal composition as the connection pattern 154. The vertical link VLINK may be electrically connected to the horizontal link HLINK through a first contact hole CNT1 formed in the first planarization layer 148.

[0112] In Figures 6A and 6B, the horizontal tie line HLINK is disposed on the interlayer insulating layer 146, and the vertical tie line VLINK is disposed on the first planarization layer 148. In another embodiment, the vertical tie line VLINK may be disposed on the interlayer insulating layer 146, and the horizontal tie line HLINK may be disposed on the first planarization layer 148.

[0113] A second planarization layer 150 is disposed on a first planarization layer 148 having a connection pattern 154 and a vertical connecting line VLINK. In one embodiment, the second planarization layer 150 may contain, but is not limited to, an organic material, such as photosensitive acrylic. In another embodiment, the second planarization layer 150 may have a multilayer structure having at least one inorganic layer and at least one organic layer. In one embodiment, the second planarization layer 150 may contain the same material as the first planarization layer 148. In another embodiment, the second planarization layer 150 may contain a different material than the first planarization layer 148.

[0114] By arranging two or more planarization layers 148 and 150, various electrodes and lines can be disposed between the first planarization layer 148 and the second planarization layer 150. In this case, since the electrodes can be arranged vertically, the area occupied by the electrodes and lines in the sub-pixel can be reduced. Therefore, the area of ​​the sub-pixel can be reduced, and a high-resolution display device 100 can be manufactured.

[0115] A light-emitting diode (or light-emitting element) D is disposed on a second planarization layer 150 in the display area AA. The light-emitting diode D may include a first electrode 132, a light-emitting layer 134 and a second electrode 136 disposed sequentially on the second planarization layer 150.

[0116] The first electrode 132 is disposed on the second planarization layer 150. The first electrode 132 can be electrically connected to the connection pattern 154 through a contact hole formed in the second planarization layer 150. In other words, the first electrode 132 can be electrically connected to one of the source electrode 115 or the drain electrode 116 of the thin film transistor T through the connection pattern 154.

[0117] For example, the first electrode 132 may include, but is not limited to, a metal component such as silver (Ag), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), a combination thereof or an alloy thereof. In another embodiment, the first electrode 132 may include, but is not limited to, a transparent metal oxide such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0118] In one embodiment, when the display device 100 is of a top emission type, the first electrode 132 may further include an opaque conductive material serving as a reflective electrode. In another embodiment, when the display device 100 is of a bottom emission type, the first electrode 132 may be disposed with a transparent conductive material (for example, ITO and / or IZO).

[0119] The bank layer BNK is disposed on the second planarization layer 150 at the boundary of each sub-pixel. The bank layer BNK may be a partition wall that defines each sub-pixel. The bank layer BNK partitions each sub-pixel, and can prevent light of specific colors output from adjacent sub-pixels from mixing.

[0120] For example, the bank layer BNK may include, but is not limited to, inorganic materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2), organic materials such as benzocyclobutene (BCB), acrylic-containing resin, epoxy-containing resin, phenolic-containing resin, polyamide-containing resin and / or polyimide-containing resin, a photosensitizer containing black pigment and / or dye, and a combination of the foregoing inorganic materials, organic materials and the photosensitizer.

[0121] The light emitting layer 134 can be arranged on the first electrode 132 in the display area AA, on the inclined surface of the bank layer BNK and on a part of the bank layer BNK, and extends to the non-display area NA.

[0122] In one embodiment, the light-emitting layer 134 may include, but is not limited to, a red light-emitting layer disposed in a red sub-pixel and emitting red light, a green light-emitting layer disposed in a green sub-pixel and emitting green light, and a blue light-emitting layer disposed in a blue sub-pixel and emitting blue light. For example, the light-emitting layer 134 may include, but is not limited to, organic light-emitting layers or inorganic light-emitting layers such as nanoscale material layers, quantum dots, micro-LED light-emitting layers or mini-LED light-emitting layers.

[0123] In one embodiment, the light-emitting layer 134 may include a light-emitting material layer. In another embodiment, the light-emitting layer 134 may further include a hole injection layer, a hole transport layer and / or a hole blocking layer disposed between the first electrode 132 and the light-emitting material layer, and an electron injection layer, an electron transport layer and / or an electron blocking layer disposed between the light-emitting material layer and the second electrode 136.

[0124] The second electrode 136 is disposed on the light-emitting layer 134. In one embodiment, the second electrode 136 may have a single-layer structure or a multilayer structure having a metal component or an alloy thereof. In another embodiment, the second electrode 136 may contain a transparent metal oxide, such as ITO and / or IZO. However, the embodiments disclosed herein are not limited to these.

[0125] In one embodiment, when the display device 100 is a top-emitting type, the second electrode 136 may be arranged using a transparent or semi-transparent conductive material. For example, the second electrode 136 may include, but is not limited to, alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, LiF / Ca:Ag, and combinations thereof.

[0126] In another embodiment, when the display device 100 is a bottom-emitting type, the second electrode 136 may be arranged using an opaque conductive material. For example, the second electrode 136 may include, but is not limited to, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and / or alloys thereof.

[0127] In another embodiment, the light emitting diode D may have a series structure. The series structure comprises a plurality of light emitting portions and at least one charge generating layer disposed between the light emitting portions. The charge generating layer is intended to connect the light emitting portions. In one embodiment, a plurality of charge generating layers including a first charge generating layer and a second charge generating layer may be provided. In one embodiment, the charge generating layer may comprise an N-type charge generating layer and a P-type charge generating layer. For example, the charge generating layer may include, but is not limited to, an organic layer doped with an alkali metal such as Li, Na, K and / or Cs and / or an alkaline earth metal such as Mg, Sr, Ba and / or Ra.

[0128] The encapsulation layer 180 is disposed in the display area AA and the non-display area NA to encapsulate the light emitting diode D. When the light emitting diode D is exposed to moisture or oxygen, a pixel shrinkage phenomenon in which the light emitting area is reduced or a defect of dark spots formed in the light emitting area may occur. In addition, moisture or oxygen may oxidize electrodes made of metal components. The encapsulation layer 180 blocks the penetration of moisture and oxygen from the outside, so as to prevent defects of the light emitting diode D and various electrodes.

[0129] In one embodiment, the encapsulation layer 180 may include, but is not limited to, a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186. In another embodiment, the encapsulation layer 180 may comprise two layers, four layers or more layers.

[0130] In one embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may comprise an inorganic material, such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). Each of the first encapsulation layer 182 and the third encapsulation layer 186 may have a single-layer structure or a multi-layer structure. In another embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may further comprise at least one organic layer disposed between inorganic layers. The second encapsulation layer 184 may comprise an epoxy group-containing resin. However, embodiments of the present disclosure are not limited thereto.

[0131] Although not shown in FIG. 6A and FIG. 6B, a touch member may be disposed on the encapsulation layer 180. The touch member may be disposed in the display area AA and sense a touch input. The touch member can sense external touch information by using a user's finger or a stylus.

[0132] Figure 7 illustrates the wiring arrangement in display area AA of a display device 200 according to another embodiment of this disclosure. In this embodiment of the display device 200, the only difference from the display device 100 of the first embodiment is the arrangement of the horizontal connecting line HLINK and the vertical connecting line VLINK; all other configurations are the same as those of the display device 100. Therefore, Figure 7 only shows the arrangement of the horizontal connecting line HLINK and the vertical connecting line VLINK. Specifically, the second and third areas disposed on both sides of the first area A1 of the display area AA are symmetrical about the first area A1, therefore the arrangements of the horizontal connecting line HLINK and the vertical connecting line VLINK in the second and third areas are identical. Therefore, for ease of description, Figure 7 only shows the first area A1 and the second area A2 of the display area AA.

[0133] Referring to Figure 7, in the first region A1 of the display area AA of the display device 200, multiple first data lines DL1 and multiple vertical connecting lines VLINK are arranged along the second direction (vertical direction, y-axis direction). Multiple second data lines DL2 extending along the second direction are disposed in the second region A2 of the display area AA. In this embodiment, the vertical connecting lines VLINK are not arranged in the second region A2.

[0134] All the multiple first data lines DL1 arranged in the first region A1 are formed to have the same length from the lower end to the upper end of the display area AA. Conversely, the lengths of the multiple second data lines DL2 arranged in the second region A2 decrease from the central region outwards, that is, from the boundary of the first region A1 to the left end.

[0135] Multiple horizontal connecting lines HLINK are arranged along the first direction (horizontal direction, x-axis direction) in the first area A1 and the second area A2 of the display area AA.

[0136] These horizontal interconnect lines HLINK are electrically connected to the vertical interconnect line VLINK in the first region A1 through the first contact hole CNT1. An insulating layer is formed between the horizontal interconnect line HLINK and the second data line DL2 so that they are electrically connected to each other through the second contact hole CNT2.

[0137] The leftmost vertical link VLINK in Zone A1 can be electrically connected via horizontal link HLINK to the closest second data line DL2 in Zone A2, i.e., the rightmost second data line DL2 in Zone A2. Furthermore, the second vertical link VLINK from the leftmost position in Zone A1 can be electrically connected via horizontal link HLINK to the second second data line DL2 from the rightmost position in Zone A2, but this is not a limitation.

[0138] The data signal is directly applied to each first data line DL1 in the first area A1 of the display area AA to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 of the corresponding sub-pixel column in the first area A1. The data signal is applied to each second data line DL2 in the second area A2 of the display area AA through the vertical interconnect line VLINK and the horizontal interconnect line HLINK to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 of the corresponding sub-pixel column in the second area A2.

[0139] In the display device 200 disclosed herein, in the display area AA other than the non-display area NA (FIG. 4), the border area can be minimized by arranging the connecting lines for supplying data signals to the sub-pixels SP1, SP2 and SP3 in the display area AA located outside the curved area BA and the second non-display area NA2 (FIG. 4) in the first direction (width direction).

[0140] In one embodiment, according to the display device 200, the horizontal interconnect lines HLINK disposed in the display area AA are not arranged at equal intervals. In the freeform or non-rectangular display device 200, since there is a difference in storage capacity between data lines DL with different lengths, this difference in storage capacity is compensated by varying the length of the vertical interconnect lines VLINK connected to the data lines DL according to the length of the data lines DL.

[0141] In other words, the difference in storage capacity can be compensated by setting the length of the vertical link VLINK to be inversely proportional to the length of the second data line DL2. For example, the vertical link VLINK connected to the outermost part of the second data line DL2 in the second region A2 has the longest length, and the length of the vertical link VLINK gradually decreases from the outermost part of the second region A2 toward the first region A1.

[0142] In other words, the difference in storage capacity can be compensated by increasing the distance "d" between the horizontal interconnects HLINK connected to the vertical interconnect VLINK and the second data line DL2, based on the length of the second data line DL2. For example, the difference in storage capacity can be compensated by adjusting the distance "d'" between these horizontal interconnects HLINK, each of which is electrically connected to the corresponding second data line DL2, and the distance "d'" is adjusted as the length of these second data lines DL2 decreases.

[0143] While the circular display device has been described in the foregoing as an application to freeform or non-rectangular display devices such as watches, this disclosure is not limited to display devices with a specific shape. In one embodiment, the first region A1 may be a rectangular region, and the second region A2 may be a non-rectangular (circular) region, but is not limited thereto.

[0144] This disclosure can be applied to display devices with shapes other than squares or rectangles, or to display devices with freeform or non-rectangular partial areas. For example, when certain areas have freeform or non-rectangular shapes, the length of data lines in the freeform areas is reduced, and the storage capacity of data lines in the freeform or non-rectangular areas can be compensated for by horizontal and vertical connecting lines arranged in the freeform areas. In one embodiment, the first area A1 may be a rectangular area, and the second area A2 may be a non-rectangular area, but is not limited thereto.

[0145] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, it is intended that this disclosure cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

[0146] 100: Display device 102: Image Processor 104: Timing Controller 106: Gate Driver 107: Data Drive 108: Power Supply 109: Display Panel 112: Semiconductor layer 112a: Channel area 112b: Source region 112c: Drain region 114: Gate electrode 115: Source Electrode 116: Drain electrode 132: First electrode 134: Emissive layer 136: Second electrode 140:Substrate 142: Buffer layer 144: Gate insulation layer 146: Interlayer insulation layer 148: First planarization layer 150: Second planarization layer 154: Connecting Patterns 180: Encapsulation layer 182: First encapsulation layer 184: Second encapsulation layer 186: Third encapsulation layer 200: Display device A1: First Area A2: Second Area A3: Third Area AA: Display area BA: Bending area BNK: Dike Layer CNT1: First contact hole CNT2: Second contact hole COLINK: Compensation Connection Line Cst: Storage capacitor D: Light-emitting diode DATA: Data Signal DDC: Data Timing Control Signal DL, DL1, DL2, DL3, DLn: Data lines DLINK: Data Link DR: Drive element EVDD: First power line EVSS: Second power line FPC: Flexible Circuit Film GDC: Gate timing control signal GL, GL1, GLm: Gate lines HLINK: Horizontal Link ℓ: Length NA, NA1, NA2: Non-display areas P: pixel PL: Power cord SLINK: Signal Link SP, SP1, SP2, SP3: Subpixels T: Thin Film Transistor Td: Driving thin-film transistor Ts: Switching thin-film transistor VLINK: Vertical Link

Claims

1. A display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first region and the at least one second region; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in the at least one second region and having a length shorter than the length of the first data lines; a plurality of vertical connecting lines arranged along the second direction in the first region; and a plurality of horizontal connecting lines arranged along the first direction in the first region and the at least one second region, wherein each of the vertical connecting lines is connected to a corresponding second data line among the second data lines via a corresponding horizontal connecting line, and wherein the length of each of the vertical connecting lines is inversely proportional to the length of each of the second data lines to be connected.

2. The display device as claimed in claim 1, wherein a data signal is applied directly to each of the first data lines, and the data signal is applied to each of the second data lines via each of the vertical interconnects and each of the horizontal interconnects.

3. The display device as claimed in claim 1 further comprises: a first contact hole electrically connecting each of the vertical interconnects to the corresponding horizontal interconnect; and a second contact hole electrically connecting each of the horizontal interconnects to the corresponding second data line.

4. The display device as claimed in claim 3 further comprises: a thin-film transistor disposed in the first region and the at least one second region; and a light-emitting diode disposed on the thin-film transistor.

5. The display device as claimed in claim 4, wherein the thin-film transistor comprises: a semiconductor layer disposed on a substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the gate electrode.

6. The display device as claimed in claim 5 further comprises: a gate insulating layer disposed between the semiconductor layer and the gate electrode; an interlayer insulating layer disposed between the gate electrode, the source electrode and the drain electrode; a planarization layer disposed on the source electrode and the drain electrode; and a connection pattern disposed on the planarization layer and connected to one of the source electrode and the drain electrode.

7. The display device as claimed in claim 6, wherein the vertical interconnects are arranged on the planarization layer and the horizontal interconnects are arranged on the interlayer insulating layer.

8. The display device as claimed in claim 7, wherein the vertical connecting lines and the connecting pattern comprise the same material.

9. The display device as claimed in claim 7, wherein the horizontal interconnects comprise the same material as the source electrode and the drain electrode.

10. The display device as claimed in claim 7, wherein each of the vertical interconnects is electrically connected to the corresponding horizontal interconnect through the first contact hole disposed in the planarization layer.

11. The display device as claimed in claim 3, wherein each of the vertical connecting lines extends a predetermined distance from the first contact hole, and the predetermined distance of each of the vertical connecting lines is inversely proportional to the length of each of the second data lines to be connected.

12. The display device as claimed in claim 1, wherein the distance between the horizontal interconnects connected to the second data lines increases as the length of the second data lines decreases.

13. The display device as claimed in claim 1, wherein the display panel has a free form.

14. The display device as claimed in claim 13, wherein the first region is a rectangular region and the at least one second region is a non-rectangular region.

15. The display device as claimed in claim 1, wherein the display panel is circular.

16. The display device as claimed in claim 15, wherein the first region is a central region of the circle, and the at least one second region is a region on either side of the central region.

17. The display device as claimed in claim 1, wherein the vertical connecting lines are not arranged in the at least one second region.

18. The display device as claimed in claim 1, wherein the first data lines are formed to have the same length.

19. A display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged in the first region and the at least one second region along a first direction; a plurality of first data lines arranged in the first region along a second direction perpendicular to the first direction; a plurality of second data lines arranged in the at least one second region along the second direction and having a length shorter than the length of the first data lines; a plurality of vertical interconnecting lines arranged in the first region along the second direction; a plurality of horizontal interconnecting lines arranged in the first region and the at least one second region along the first direction; and a plurality of compensating interconnecting lines extending from the vertical interconnecting lines, wherein each of the vertical interconnecting lines is electrically connected to a corresponding second data line among the second data lines through a corresponding horizontal interconnecting line among the horizontal interconnecting lines, and wherein the length of each of the compensating interconnecting lines is inversely proportional to the length of each of the second data lines to be connected.

20. A display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first region and the at least one second region; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in the at least one second region and having a length shorter than the length of the first data lines; a plurality of vertical connecting lines arranged along the second direction in the first region; and a plurality of horizontal connecting lines arranged along the first direction in the first region and the at least one second region, wherein the distance between the horizontal connecting lines is inversely proportional to the length of each of the second data lines to which each of the horizontal connecting lines is connected.

Images