Computing device and processing device

Abstract

A suitable calculation device and processing device for performing remainder operations are provided. A multiplication circuit includes a first multiplier and a second multiplier that multiply two values ​​respectively, and a first combination circuit. The first combination circuit combines the multiplication results of the first and second multipliers. The multiplication circuit uses the first multiplier, the second multiplier, and the first combination circuit to calculate the dividend from a first set. The remainder operation circuit includes a first circuit and a second circuit for inputting the dividend, a second combination circuit, a third combination circuit, and a correction circuit. The first circuit includes a third multiplier for multiplying a first constant and a fourth multiplier for multiplying a first divisor. The second circuit includes a fifth multiplier for multiplying a second constant and a sixth multiplier for multiplying a second divisor. The second combination circuit is disposed between the fifth and sixth multipliers. The third combination circuit combines the multiplication results of the fourth and sixth multipliers.

Claims

1. An arithmetic apparatus for performing remainder operations, comprising: a multiplication circuit that inputs a first set of values, a second value, a third value, and a fourth value, each having a maximum bit length of N (N is an integer greater than or equal to 1), and includes a first multiplier for multiplying the first value and the second value, a second multiplier for multiplying the third value and the fourth value, and a first combining circuit configured to combine the multiplication results of the first multiplier and the second multiplier, and using the first multiplier, the second multiplier, and the first combining circuit to calculate a dividend from the first set; a first circuit that inputs a portion of the dividend and includes a third multiplier for multiplying a first constant and a fourth multiplier for multiplying a first divisor; a second circuit that inputs a portion of the dividend and includes a fifth multiplier for multiplying a second constant and a sixth multiplier for multiplying a second divisor; and a second combining circuit disposed between the fifth multiplier and the sixth multiplier. The third combining circuit is configured to combine the multiplication results of the aforementioned fourth multiplier and the aforementioned sixth multiplier; a correction circuit; and a remainder operation circuit, which uses the aforementioned first circuit, the aforementioned second circuit, the aforementioned second combining circuit, and the aforementioned third combining circuit to calculate the approximate value of the remainder of the aforementioned remainder operation, and corrects the aforementioned approximate value by means of the aforementioned correction circuit to calculate the aforementioned remainder.

2. The arithmetic apparatus as described in claim 1, wherein, The aforementioned arithmetic device performs a first calculation; the aforementioned first calculation involves inputting the aforementioned first set twice into the aforementioned multiplication circuit; corresponding to the first input of the aforementioned first set, the aforementioned first combination circuit performs the calculation where vm11 is the multiplication result of the aforementioned first multiplier corresponding to the first input of the aforementioned first set, and vm21 is the multiplication result of the aforementioned second multiplier corresponding to the first input of the aforementioned first set; the aforementioned third combination circuit performs the calculation where vm41 is the multiplication result of the aforementioned fourth multiplier corresponding to the first input of the aforementioned first set, and vm61 is the multiplication result of the aforementioned sixth multiplier corresponding to the first input of the aforementioned first set; corresponding to the second input of the aforementioned first set, the aforementioned first combination circuit performs the calculation where vm12 is the multiplication result of the aforementioned first multiplier corresponding to the second input of the aforementioned first set, and vm22 is the multiplication result of the aforementioned second multiplier corresponding to the second input of the aforementioned first set; The calculations performed by the aforementioned second combination circuit are as follows: vm51 corresponds to the multiplication result of the aforementioned fifth multiplier for the first input set, and vm52 corresponds to the multiplication result of the aforementioned fifth multiplier for the second input set. The calculations performed by the aforementioned third combination circuit are as follows: vm42 corresponds to the multiplication result of the aforementioned fourth multiplier for the second input set, and vm62 corresponds to the multiplication result of the aforementioned sixth multiplier for the second input set.

3. The arithmetic device as described in claim 1, wherein, The aforementioned arithmetic device performs a first calculation; the aforementioned first calculation involves inputting the aforementioned first set twice into the aforementioned multiplication circuit; corresponding to the first input of the aforementioned first set, the aforementioned first combination circuit performs a calculation in which the aforementioned vm31 is the value obtained by deleting N bits from the lower side of vm11, the aforementioned vm11 is the multiplication result of the aforementioned first multiplier corresponding to the first input of the aforementioned first set, the aforementioned vm21 is the multiplication result of the aforementioned second multiplier corresponding to the first input of the aforementioned first set; the aforementioned third combination circuit performs a calculation in which the aforementioned vm41 is the multiplication result of the aforementioned fourth multiplier corresponding to the first input of the aforementioned first set, the aforementioned vm61 is the multiplication result of the aforementioned sixth multiplier corresponding to the first input of the aforementioned first set; corresponding to the second input of the aforementioned first set, the aforementioned first combination circuit performs a calculation in which the aforementioned vm12 is the multiplication result of the aforementioned first multiplier corresponding to the second input of the aforementioned first set, the aforementioned vm22 is the multiplication result of the aforementioned second multiplier corresponding to the second input of the aforementioned first set; The calculations performed by the aforementioned second combination circuit are as follows: vm51 corresponds to the multiplication result of the aforementioned fifth multiplier for the first input set, and vm52 corresponds to the multiplication result of the aforementioned fifth multiplier for the second input set. The calculations performed by the aforementioned third combination circuit are as follows: vm42 corresponds to the multiplication result of the aforementioned fourth multiplier for the second input set, and vm62 corresponds to the multiplication result of the aforementioned sixth multiplier for the second input set.

4. The arithmetic apparatus as described in any one of claims 1 to 3, wherein, The aforementioned arithmetic device performs a second calculation; the aforementioned second calculation involves inputting the aforementioned first set into the aforementioned multiplication circuit once; the aforementioned first combination circuit outputs vm13 and vm23, where vm13 is the multiplication result of the aforementioned first multiplier corresponding to the input of the aforementioned first set, and vm23 is the multiplication result of the aforementioned second multiplier corresponding to the input of the aforementioned first set; the aforementioned second combination circuit outputs vm53, where vm53 is the multiplication result of the aforementioned fifth multiplier corresponding to the input of the aforementioned first set; the aforementioned third combination circuit calculates (vm13-vm43) and (vm23-vm63), where vm43 is the multiplication result of the aforementioned fourth multiplier corresponding to the input of the aforementioned first set, and vm63 is the multiplication result of the aforementioned sixth multiplier corresponding to the input of the aforementioned first set.

5. The arithmetic apparatus as described in any one of claims 1 to 3, wherein, The aforementioned arithmetic device performs a third calculation; the aforementioned third calculation is performed by inputting the aforementioned first set into the aforementioned multiplication circuit once; the aforementioned first combination circuit performs a calculation in which the aforementioned vm14 corresponds to the multiplication result of the aforementioned first multiplier corresponding to the input of the aforementioned first set, and the aforementioned vm24 corresponds to the multiplication result of the aforementioned second multiplier corresponding to the input of the aforementioned first set; the aforementioned second combination circuit outputs vm54, which corresponds to the multiplication result of the aforementioned fifth multiplier corresponding to the input of the aforementioned first set; the aforementioned third combination circuit performs a calculation in which the aforementioned vm44 corresponds to the multiplication result of the aforementioned fourth multiplier corresponding to the input of the aforementioned first set, and the aforementioned vm64 corresponds to the multiplication result of the aforementioned sixth multiplier corresponding to the input of the aforementioned first set.

6. The arithmetic apparatus as described in claim 2 or claim 3, wherein, Let q, q0, q1, a, a0, a1, b, b0, and b1 satisfy q < 22*N, q = q1*2N + q0, a = a1*2N + a0, b = b1*2N + b0, a < q, and b < q. In the aforementioned first calculation, the aforementioned second constant is floor(22*N / q1) or floor(23*N / q). The aforementioned first divisor is q0, and the aforementioned second divisor is q1. The aforementioned first value contained in the aforementioned first set of inputs in the first instance is the aforementioned value a0. The aforementioned second value contained in the aforementioned first set of inputs in the first instance is the aforementioned value b1. The aforementioned third value contained in the aforementioned first set of inputs in the first instance is the aforementioned value a1. The aforementioned fourth value contained in the aforementioned first set of inputs in the first instance is the aforementioned value b1. The aforementioned first value contained in the aforementioned first set of inputs in the second instance is the aforementioned value a0. The second value contained in the first set of the second input is the aforementioned value b0. The third value contained in the first set of the second input is the aforementioned value a1. The fourth value contained in the first set of the second input is the aforementioned value b0. Calculate (a*b)%q.

7. A processing apparatus comprising: an arithmetic unit as described in any one of claims 1 to 6, and a control unit configured to perform number-theoretical transformations using the arithmetic unit; wherein the arithmetic unit inputs the first set once into the multiplication circuit; the first combination circuit outputs vm13 and vm23, vm13 being the multiplication result of a first multiplier corresponding to the input first set, and vm23 being the multiplication result of a second multiplier corresponding to the input first set; the second combination circuit outputs vm53, vm53 being the multiplication result of a fifth multiplier corresponding to the input first set; and the third combination circuit calculates (vm13-vm43) and (vm23-vm63), vm43 being the multiplication result of a fourth multiplier corresponding to the input first set, and vm63 being the multiplication result of a sixth multiplier corresponding to the input first set. Values ​​q0, q1, a0, a1, b0, and b1 satisfy q0 < 2N, q1 < 2N, a0 < q0, b0 < q0, a1 < q1, and b1 < q1. The first constant is floor(22*N / q0), the second constant is floor(22*N / q1), the first divisor is q0, the second divisor is q1, the first value in the input first set is a0, the second value in the input first set is b0, the third value in the input first set is a1, and the fourth value in the input first set is b1. When performing the number theory transformation, the aforementioned computing device uses either the calculation of (a0*b0)%q0 or the calculation of (a1*b1)%q1 to perform the rotation factor calculation included in the number theory transformation. Using the other side of the calculations (a0*b0)%q0 and (a1*b1)%q1, the butterfly operation contained in the aforementioned number theory transformation is performed simultaneously with the aforementioned rotation factor calculation.

8. An arithmetic device comprising: a first circuit and a second circuit, each comprising a first multiplier for obtaining a first value by multiplying two input values, each having a maximum bit length of N (N is an integer greater than or equal to 1); a partitioning circuit for dividing the first value into a second value of upper bit length (2*N-k1, where k1 is an integer greater than or equal to 1 and less than or equal to 2*N-1) bits and a third value of lower bit length (N bits); a second multiplier for obtaining a fourth value by multiplying the second value by a value m; and a shifting circuit for obtaining a fifth value by shifting the fourth value to the right by k2 bits (where k2 is an integer greater than or equal to 1 and less than or equal to 2*N-1). The circuit comprises a third multiplier that multiplies the aforementioned fifth value by the divisor q to obtain the sixth value, and a subtractor that subtracts the aforementioned sixth value from the aforementioned third value to obtain the seventh value; and a third circuit that calculates the remainder when the aforementioned first value is divided by the aforementioned divisor q by correcting the aforementioned seventh values ​​from the aforementioned first circuit and the aforementioned second circuit; the third circuit calculates a ninth value by subtracting the aforementioned remainder from the input eighth value and a tenth value by adding the aforementioned remainder to the aforementioned eighth value for the aforementioned seventh value from the aforementioned first circuit; and calculates the remainder when the aforementioned ninth value is divided by the aforementioned divisor q and the remainder when the aforementioned tenth value is divided by the aforementioned divisor q.

9. A processing apparatus comprising: an arithmetic unit as described in claim 8, and a control unit configured to perform a number-theoretical transformations using the arithmetic unit; wherein, when performing the number-theoretical transformations, the arithmetic unit performs a butterfly operation included in the number-theoretical transformations using the first circuit; and performs a twiddle factor calculation included in the number-theoretical transformations using the second circuit in parallel with the butterfly operation.

10. The processing apparatus as described in claim 9, wherein, The value of k1 used in the first circuit is smaller than the value of k1 used in the second circuit; the value of k2 used in the first circuit is larger than the value of k2 used in the second circuit.

11. The processing apparatus as described in claim 10, wherein, The values ​​of k1 used in the first circuit and the second circuit are variable values ​​corresponding to the bit length of the divisor q. The values ​​of k2 used in the first circuit and the second circuit are both fixed values.

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