Semiconductor device and method of manufacturing the same

Abstract

The integrated circuit includes CFET transistors compatible with the CFET process and a variable reactor. The CFET transistors include stacked P-type and N-type transistors. The variable reactor includes two stacked transistors of the same conductivity type. A doped semiconductor layer is formed below and coupled to the source / drain regions of the lower transistor. A first local source / drain interconnect structure is coupled between the vertically stacked source / drain regions on a first side of the variable reactor. A second local source / drain interconnect structure is coupled between the stacked source / drain regions on a second side of the variable reactor. A common gate metal or gate electrode encapsulates the channels of the two transistors. The capacitance of the variable reactor is reliably adjusted by adjusting the tuning voltage applied to the local source / drain interconnect structure.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming an isolation structure disposed next to an active region; growing a first source / drain region and a second source / drain region of a lower transistor of a variable reactor, the first source / drain region and the second source / drain region being located in the active region and having a first conductivity type, a first channel of the lower transistor of the variable reactor extending between the first source / drain region and the second source / drain region along a first lateral direction; growing a third source / drain region and a fourth source / drain region of an upper transistor of the variable reactor, the third source / drain region and the fourth source / drain region being stacked above the first source / drain region and the second source / drain region in the active region and having the first conductivity type, a second channel of the upper transistor of the variable reactor extending between the third source / drain region and the fourth source / drain region along the first lateral direction; An interface gate dielectric layer is deposited between the first channel of the upper transistor and the second channel of the lower transistor in the variable reactor; a high dielectric constant gate dielectric layer is deposited above the interface gate dielectric layer, wherein the high dielectric constant gate dielectric layer and the isolation structure are mixed at an interface between the high dielectric constant gate dielectric layer and the isolation structure; a gate metal of the variable reactor is deposited above the high dielectric constant gate dielectric layer; a gate spacer layer is formed, the gate spacer layer having a first sidewall interfacely connected to the high dielectric constant gate dielectric layer and a second sidewall facing away from the gate metal; A contact etch stop layer is formed, which extends along the second sidewall of the gate spacer and is interfaced with the second sidewall, wherein the dielectric constant of the high dielectric constant gate dielectric layer is greater than the dielectric constant of the gate spacer or the contact etch stop layer; and a doped semiconductor layer of the variable reactor is formed below the first source / drain region, the first channel and the second source / drain region.

2. The method as described in claim 1, further comprising forming a first local source / drain interconnect structure electrically coupled to the first source / drain region and extending vertically from the first source / drain region to the third source / drain region.

3. The method as described in claim 1, wherein forming the doped semiconductor layer includes performing a dopant implantation process after depositing the gate metal.

4. The method as claimed in claim 1, further comprising: growing a fifth source / drain region and a sixth source / drain region of the lower transistor of a complementary field-effect transistor; and growing a seventh source / drain region and an eighth source / drain region of the upper transistor of the complementary field-effect transistor, wherein the upper transistor and the lower transistor of the complementary field-effect transistor have opposite conductivity types.

5. The method as described in claim 4, further comprising growing the first source / drain region and the second source / drain region in the same process as the fifth source / drain region and the sixth source / drain region.

6. A semiconductor device comprising: an active region; An isolation structure is disposed adjacent to the active region; a variable reactor includes: A first lower transistor having a first source / drain region and a second source / drain region of a first conductivity type in the active region; and a first upper transistor above the first lower transistor in the active region having a third source / drain region and a fourth source / drain region of the first conductivity type. A gate structure is located above the active region, wherein the gate structure includes: an interface gate dielectric layer, interfaceally connected to the active region; a high-dielectric-constant gate dielectric layer, located above the interface gate dielectric layer; and at least one gate metal, located above the high-dielectric-constant gate dielectric layer, wherein the dielectric constant of the high-dielectric-constant gate dielectric layer is greater than the dielectric constant of the isolation structure; a complementary field-effect transistor includes: a second lower transistor, including a fifth source / drain region and a sixth source / drain region; and a second upper transistor, located above the second lower transistor, including a seventh source / drain region and an eighth source / drain region, the seventh source / drain region and the eighth source / drain region having a conductivity type opposite to that of the fifth source / drain region and the sixth source / drain region; and an interlayer dielectric layer disposed above the seventh source / drain region; A source / drain contact is disposed in the interlayer dielectric layer to be electrically coupled to the seventh source / drain region; and a metal silicate layer is located between the seventh source / drain region and the source / drain contact, wherein the metal silicate layer has a curved profile.

7. The apparatus of claim 6 further comprises a doped semiconductor layer of the first conductivity type, the doped semiconductor layer extending below the first source / drain region and the second source / drain region and electrically coupled to the first source / drain region and the second source / drain region.

8. The apparatus as claimed in claim 7 further includes an undoped semiconductor layer extending below the fifth source / drain region and the sixth source / drain region.

9. The apparatus as claimed in claim 6, wherein the variable reactor comprises: A first partial source / drain interconnect structure electrically coupled to the first source / drain region and extending vertically from the first source / drain region to the third source / drain region; and a second partial source / drain interconnect structure electrically coupled to the second source / drain region and extending vertically from the second source / drain region to the fourth source / drain region.

10. A method of manufacturing a semiconductor device, comprising: growing a first source / drain region and a second source / drain region of a lower transistor of a variable reactor; growing a third source / drain region and a fourth source / drain region of an upper transistor of the variable reactor above the lower transistor, wherein the upper transistor and the lower transistor have a first conductivity type; forming a first local source / drain interconnect structure electrically coupled to the first source / drain region and extending vertically from the first source / drain region to the third source / drain region; forming a second local source / drain interconnect structure electrically coupled to the second source / drain region and extending vertically from the second source / drain region to the fourth source / drain region, and electrically short-circuited from the first local source / drain interconnect structure; and growing a fifth source / drain region of a complementary field-effect transistor. A gate structure is formed that is connected to at least three surface interfaces of a channel of the upper transistor of the variable reactor, wherein the gate structure includes a gate dielectric layer above the channel and a gate metal above the gate dielectric layer; a metal silicon layer is formed on the fifth source / drain region; a first dielectric layer is deposited above the fifth source / drain region; A source / drain contact is formed extending through the first dielectric layer, wherein the metal silicate layer is located between the fifth source / drain region and the source / drain contact, wherein the source / drain contact is surrounded by the first dielectric layer, wherein the conductivity of the metal silicate layer is between the conductivity of the fifth source / drain region and the conductivity of the source / drain contact; and an interconnect structure is formed above the variable reactor and includes a plurality of interconnect layers, wherein each of the interconnect layers includes a plurality of metal lines disposed in a second dielectric layer, wherein the metal lines are spaced apart from each other by the second dielectric layer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the second dielectric layer.

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