Manufacturing method of patterned conductive layer

TWI943819BActive Publication Date: 2026-10-21UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW115104863
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2026-02-06
Publication Date
2026-10-21
Estimated Expiration
2046-02-05

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Abstract

A method for fabricating a patterned conductive layer includes the following steps: The distance between a first conductive pattern and a second conductive pattern in a first direction is greater than the distance between a third conductive pattern and a second conductive pattern in the first direction. An adjustment pattern is generated, and the adjustment pattern overlaps with a portion of the space between the first and second conductive patterns. A first pattern group including the first and second conductive patterns is output to a first photomask. The adjustment pattern is output to a third photomask. A first lithography process is performed with the first photomask to form a first trench and a second trench in a first dielectric layer. A third lithography process is performed with the third photomask to enlarge the first trench located in the first dielectric layer.
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Claims

1. A method for fabricating a patterned conductive layer, comprising: Provide a layout pattern; At least a portion of the layout pattern is divided into a first pattern group and a second pattern group, wherein the first pattern group includes a first conductor pattern and a second conductor pattern adjacent to the first conductor pattern in a first direction, and the second pattern group includes a third conductor pattern adjacent to the second conductor pattern in the first direction, and the third conductor pattern is adjacent to the first conductor pattern in a second direction, wherein the distance between the first conductor pattern and the second conductor pattern in the first direction is greater than the distance between the third conductor pattern and the second conductor pattern in the first direction; an adjustment pattern is generated, the adjustment pattern overlapping a portion of the space between the first conductor pattern and the second conductor pattern in a third direction orthogonal to the first and second directions; the first pattern group is output to a first photomask; the second pattern group is output to a second photomask; the adjustment pattern is output to a third photomask; a first lithography process is performed on the first photomask to form a first trench and a second trench in a first dielectric layer; a second lithography process is performed on the second photomask to form a third trench in the first dielectric layer; A third photolithography process is performed using the third photomask to enlarge the first trench located in the first dielectric layer, wherein the first trench is enlarged into an adjusted trench by the third photolithography process; and a first conductor, a second conductor, and a third conductor are formed in the adjusted trench, the second trench, and the third trench, respectively.

2. The method for fabricating a patterned conductive layer as described in claim 1, wherein the adjustment pattern also overlaps with a portion of the first conductor pattern in the third direction.

3. The method for fabricating a patterned conductive layer as described in claim 1, wherein the shape of the first conductor pattern is transferred to the first dielectric layer through the first photolithography process to form the first trench, and the shape of the second conductor pattern is transferred to the first dielectric layer through the first photolithography process to form the second trench.

4. The method for fabricating a patterned conductive layer as described in claim 1, wherein the first trench is adjacent to the second trench in a fourth direction, the third trench is adjacent to the second trench in the fourth direction and to the first trench in a fifth direction, and the distance between the first trench and the second trench in the fourth direction is greater than the distance between the third trench and the second trench in the fourth direction.

5. The method for fabricating a patterned conductive layer as described in claim 4, wherein the first trench extends along the fourth direction, the second trench extends along the fifth direction, and the third trench extends along the fourth direction.

6. The method for fabricating a patterned conductive layer as described in claim 4, wherein the fourth direction is orthogonal to the fifth direction.

7. The method for fabricating a patterned conductive layer as described in claim 4, wherein a patterned photoresist layer is formed on the first dielectric layer in the third photolithography process, and the patterned photoresist layer includes an adjustment opening that overlaps with a portion of the first dielectric layer located between the first trench and the second trench in a sixth direction orthogonal to the fourth and fifth directions.

8. The method of fabricating a patterned conductive layer as described in claim 7, wherein the adjustment opening also overlaps with a portion of the first trench in the ground slip direction.

9. The method for fabricating a patterned conductive layer as described in claim 7, wherein the shape of the adjustment pattern is transferred into a photoresist layer to form the adjustment opening.

10. The method for fabricating a patterned conductive layer as described in claim 7, wherein the third photolithography process includes an etching process using the patterned photoresist layer as an etching mask, and the portion of the first dielectric layer located between the first trench and the second trench is removed by the etching process.

11. The method for fabricating a patterned conductive layer as described in claim 10, wherein a mask layer is formed on the first dielectric layer in the third lithography process, the patterned photoresist layer is formed on the mask layer, and the first trench, the second trench and the third trench are filled by the mask layer before the etching process.

12. The method for fabricating a patterned conductive layer as described in claim 4, wherein the distance between the adjusted trench and the second trench in the fourth direction is less than the distance between the first trench and the second trench in the fourth direction.

13. The method for fabricating a patterned conductive layer as claimed in claim 1, wherein the first conductive pattern includes a first side facing the second conductive pattern in a first direction, the third conductive pattern includes a second side facing the second conductive pattern in the first direction, and the adjustment pattern overlaps with the first side in the third direction.

14. The method of fabricating a patterned conductive layer as described in claim 13, wherein the adjusted pattern includes a third side facing the second conductive pattern in the first direction, and the third side is aligned with the second side.

15. The method for fabricating a patterned conductive layer as described in claim 13, wherein the adjustment pattern includes a third side facing the second conductive pattern in the first direction, and the distance between the third side and the second conductive pattern in the first direction is equal to the distance between the second side and the second conductive pattern in the first direction.

16. The method for fabricating a patterned conductive layer as described in claim 1, wherein the first conductive pattern extends along the first direction, the second conductive pattern extends along the second direction, and the third conductive pattern extends along the first direction.

17. The method for fabricating a patterned conductive layer as described in claim 1, wherein the first direction is orthogonal to the second direction.

18. The method for fabricating a patterned conductive layer as described in claim 1, wherein the patterned layout further includes: A first through-hole pattern is positioned above the first conductor pattern in the third direction; And a second through-hole pattern, located above the third conductor pattern in the third direction, wherein the first conductor pattern includes a first side facing the second conductor pattern, the third conductor pattern includes a second side facing the second conductor pattern, and the distance between the first through-hole pattern and the first side in the first direction is less than the distance between the second through-hole pattern and the second side in the first direction.

19. The method for fabricating a patterned conductive layer as described in claim 18 further includes: outputting the first via pattern and the second via pattern to a fourth photomask; forming a second dielectric layer on the first dielectric layer, the first conductive wire, the second conductive wire, and the third conductive wire; and performing a fourth photolithography process on the fourth photomask to form a first via penetrating the second dielectric layer to expose a portion of the first conductive wire and a second via penetrating the second dielectric layer to expose a portion of the third conductive wire.

20. The method for fabricating a patterned conductive layer as described in claim 19, wherein the distance between the first via pattern and the first side edge in the first direction is less than the alignment tolerance of the fourth photolithography process.

Citation Information

Patent Citations

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  • Integrated circuit and formation method thereof

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