Memory system, memory controller chip and memory control method

Abstract

The implementation provides a memory system and memory control method capable of high-speed reading. The memory system in the embodiment includes: memory capable of storing data of 2 bits or more in each of a plurality of memory cells; and a memory controller for controlling the writing of data to the aforementioned memory cells and controlling the reading of data written to the aforementioned memory cells. If the memory controller receives a first instruction from the host, it reads the data that is the object of the first instruction from the aforementioned memory and writes the read data into the aforementioned memory in a writing mode corresponding to a smaller number of bits than the writing mode when the read data is written. If it receives a read instruction from the aforementioned host for the data that is the object of the aforementioned first instruction, it reads the data that has been written into the aforementioned memory through the aforementioned first write control and transmits it to the aforementioned host.

Description

Technical Field

[0001] The present invention relates to a memory system and a memory control method. [Related Application Case] This application enjoys priority based on Japanese Patent Application No. 2021-152518 (filed on September 17, 2021). This application incorporates all the contents of the basic application by reference to this basic application. Prior Technology

[0002] In recent years, based on the requirements of miniaturization and large capacity, 3D structure has become a pursuit in semiconductor memory devices such as NAND flash memory. Furthermore, in such semiconductor memory devices, in addition to the case of setting the memory cell transistor as SLC (Single Level Cell) that can hold 1 bit (2-value) of data, there are also cases of configuration as MLC (Multi Level Cell) that can hold 2 bits (4-value) of data, TLC (Triple Level Cell) that can hold 3 bits (8-value) of data, QLC (Quad Level Cell) that can hold 4 bits (16-value) of data, and PLC (Penta Level Cell) that can hold 5 bits (32-value) of data. However, because the memory cell transistor system is multi-valued, the limit performance during readout is reduced, and there may be situations where even if the host interface speed is increased, high-speed data transmission cannot be fully achieved. Summary of the Invention

[0003] This embodiment aims to provide a memory system and a memory control method capable of high-speed reading. The implemented memory system comprises: a memory having a plurality of memory cells, capable of storing at least 2 bits of data in each of the plurality of memory cells; and a memory controller that controls the writing of data to each memory cell in a manner corresponding to the number of bits of data that can be written to each memory cell, and controls the reading of data written to each memory cell. The memory controller receives a signal from the host computer... The instruction is to read the data that is the object of the aforementioned first instruction from the aforementioned memory and write the read data into the aforementioned memory using a write method with a smaller number of bits than the write method used when writing the read data. If a read instruction for the data that is the object of the aforementioned first instruction is received from the aforementioned host, the data written into the aforementioned memory will be read out through the aforementioned first write control and transmitted to the aforementioned host. Simple Explanation of the Diagram

[0004] [Figure 1] is a block diagram illustrating a memory system constructed using a semiconductor device according to this embodiment. [Figure 2] is a block diagram illustrating one example of the specific configuration of the memory controller in Figure 1. [Figure 3] is a block diagram illustrating an example of the configuration of memory chip 4. [Figure 4] is an illustrative diagram showing one example of the instruction format used to implement the high-speed read preparation instruction and the write-back instruction described later. [Figure 5] is a timing diagram of readout in the first embodiment. [Figure 6] is a timing diagram for writing and reading in the comparative example. [Figure 7] is a memory map used to illustrate the memory regions of memory chip 4. [Figure 8] is a flowchart demonstrating the actions of the first implementation mode. [Figure 9] is a flowchart illustrating the action flow used in the second embodiment. [Figure 10] is a block diagram illustrating the modified example. [Figure 11] is a flowchart demonstrating the actions of a variation of Figure 10. [Figure 12] is a flowchart illustrating the variation example. Implementation

[0005] Hereinafter, with reference to the figures, the embodiments of the present invention will be described in detail. This implementation improves read performance by re-recording the recorded data according to the requirements from the host, changing the written method to make tR smaller. The amount of information recorded in a single memory cell transistor of NAND flash memory tends to increase from 1-bit (SLC) to 2-bit (MLC), 3-bit (TLC), 4-bit (QLC), and 5-bit (PLC). Increasing the amount of information that can be stored in a single memory cell transistor allows for the necessary capacity to be achieved with fewer cells, thus reducing chip size and cost. However, as multi-leveling progresses—that is, the number of bits of information recorded in a single memory cell transistor (hereinafter referred to as the number of bits) increases—the number of readout voltages required to read 1 bit of data from a single memory cell transistor increases, and the time (tR) required from the host until the data is transmitted to the host increases.

[0006] In addition, tR is a parameter of the memory cell transistor corresponding to the type of NAND memory. If tR increases, the limit performance of reading data (hereinafter referred to as the limit read performance) will decrease. The limit read performance of the memory device is determined by the multiplication of (1) to (3) below. (1) The data capacity (page capacity) that can be read from one die of NAND memory relative to the read requirement in one operation. (2) The reciprocal of tR (3) Number of NAND dies in one device.

[0007] In recent years, the speed of the interface between memory devices and the host (host interface) has been successfully improved. However, if the increase in read speed (tR) is due to multi-level technology, there is a possibility that the maximum read performance of the memory device may be lower than the speed of the host interface. As a result, data transfer during read operations between the host and memory devices will be limited by the maximum read performance of the memory device. Therefore, to improve the ultimate read performance, one could consider increasing the page capacity in (1) or increasing the number of chips in (3). However, increasing the page capacity in (1) would increase the cost of NAND memory chips, making it difficult to implement. Furthermore, if the method of increasing the number of chips in (3) is adopted, although the capacity of the memory device will increase, the increase in chips to increase capacity is not a proper response to the product requirements. Moreover, if one wants to increase the number of chips without changing the device capacity, it would require using NAND memory with smaller chip capacity, leading to increased costs.

[0008] Furthermore, to improve the maximum read performance of the memory device, it is also possible to consider increasing the inverse of tR in (2). Even for the same memory device, it is possible to use write methods with different numbers of cells. For example, it is possible to write data to the same memory device using either the write method corresponding to QLC or the write method corresponding to SLC. Therefore, when recording data, a write method that reduces tR is used, that is, a write method with a small number of cells is used. However, if, in order to reduce tR, for example, SLC is used, which is the write method with the smallest tR (smallest number of cells), it will result in a reduction in the capacity that can be recorded. Therefore, in this embodiment, during writing, a writing method with a larger number of cells than SLC is used for recording. Furthermore, during data reading, the data is pre-recorded in a writing method with a smaller number of cells (tR) according to the requirements from the host. In this way, the maximum read performance of the memory device during reading is improved. (The structure of the memory system)

[0009] Figure 1 is a block diagram illustrating a memory system constructed using a semiconductor device according to this embodiment. Figure 2 is a block diagram illustrating one example of the specific configuration of the memory controller in Figure 1. The memory system 1 of this embodiment includes a memory controller 3 and four memory chips 4A to 4D (hereinafter, when there is no need to distinguish between the four memory chips 4A to 4D, they are representatively referred to as memory chips 4). The number of memory chips 4 is not limited to four, and any number of memory chips, including one or more, can be used. Furthermore, a memory device is constructed by means of the memory controller 3 and the memory chips 4.

[0010] The memory system 1 is capable of connecting to the host 2. The host 2 is, for example, an electronic device such as a personal computer, a portable terminal, an in-vehicle device, or a server. The host 2 includes a central processing unit (CPU) 2a as a processor, a ROM (not shown), and a DRAM 2b. The memory system 1, in response to requests from the host 2, stores data (hereinafter simply referred to as data) from the host 2 in each memory chip 4, or reads data stored in each memory chip 4 and outputs it to the host 2. Specifically, the memory system 1 is capable of writing data to each memory chip 4 in response to write requests from the host 2, and reading data from each memory chip 4 in response to read requests from the host 2. The memory system 1 can be a UFS (Universal Flash Storage) device, which is a package that integrates the memory controller 3 and multiple memory chips 4 into one unit, or an SSD (Solid State Drive). In Figure 1, the memory system 1 is shown connected to the host 2.

[0011] The memory chip 4 is a semiconductor memory device constructed by storing data non-volatilely using NAND flash memory or similar materials. As shown in Figure 1, the memory controller 3 and each memory chip 4 are connected via a NAND bus. The memory controller 3 controls the writing of data to the memory chip 4 according to write requests from the host 2. Furthermore, the memory controller 3 controls the reading of data from the memory chip 4 according to read requests from the host 2. The memory controller 3 may also spontaneously control the writing and reading of data from the memory chip 4 without being prompted by requests from the host 2.

[0012] In Figure 2, the memory controller 3 includes a CPU 11, a ROM 12, a RAM (Random Access Memory) 13, an ECC (Error Check and Correct) circuit 14, a host interface (I / F) circuit 15, and a memory I / F circuit 16. The CPU 11, ROM 12, RAM 13, ECC circuit 14, host I / F circuit 15, and memory I / F circuit 16 are interconnected via an internal bus 17.

[0013] The host I / F circuit 15 receives data from the host 2 and outputs the requests and write data contained in the received data to the internal bus 17. Furthermore, the host I / F circuit 15 sends data read from the memory chip 4 and responses from the CPU 11 to the host 2. Additionally, the host 2 also has an I / F circuit (not shown) corresponding to the host I / F circuit 15. The host 2 and the host I / F circuit 15 are connected via a specific interface. For example, this interface may be a parallel interface such as eMMC (embedded Multi Media Card), a serial expansion interface such as PCIe (Peripheral Component Interconnect-Express), or a high-speed serial interface such as M-PHY.

[0014] The memory I / F circuit 16 controls the writing of data to each memory chip 4 and the reading of data from each memory chip 4 based on the instructions of the CPU 11.

[0015] CPU 11 provides overall control over the memory controller 3. The CPU 11, constituting the control circuit, may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the CPU 11 receives a request from the host via the host I / F circuit 15, it performs control according to that request. For example, the CPU 11, following a request from the host, issues instructions to the memory I / F circuit 16 to write data to each memory chip 4. Furthermore, the CPU 11, following a request from the host, issues instructions to the memory I / F circuit 16 to read data from each memory chip 4.

[0016] RAM 13 temporarily stores data received from the host until it is written into the memory chips 4, or temporarily stores data read from the memory chips 4 until it is sent to the host. RAM 13 may be a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). Furthermore, RAM 13 contains a region LUT 13a for recording the logical-physical translation table. CPU 11 determines the storage area (hereinafter referred to as memory area) on each memory chip 4 for the data stored in RAM 13. The data is stored in RAM 13 via internal bus 17. CPU 11 determines the memory area for data that is written to page units, i.e., page data.

[0017] Physical addresses are allocated in the memory area of ​​memory chip 4. CPU 11 uses physical addresses to manage the memory area to which data is written. CPU 11 instructs memory I / F circuit 16 to write data to memory chip 4 by specifying the physical address of the determined memory area. CPU 11 stores a logical-physical translation table (LUT13a) representing the corresponding logical address of data (logical address managed by the host) and the physical address where the data is written in RAM 13. When CPU 11 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address and instructs memory I / F circuit 16 to read the data by specifying the physical address.

[0018] ECC circuit 14 encodes the data stored in RAM 13 and generates codewords. Furthermore, ECC circuit 14 decodes the codewords read from each memory chip 4.

[0019] Figure 2 shows an example configuration of the memory controller 3, which includes an ECC circuit 14 and a memory I / F circuit 16. However, the ECC circuit 14 can also be embedded within the memory I / F circuit 16. Furthermore, the ECC circuit 14 can also be embedded within each memory chip 4.

[0020] When a write request caused by a write command is received from host 2, memory controller 3 operates as follows: CPU 11 temporarily stores the data to be written in RAM 13. CPU 11 reads the data stored in RAM 13 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and provides the codeword to memory I / F circuit 16. Memory I / F circuit 16 writes the input codeword to each memory chip 4. When the host 2 receives a read request caused by a read instruction, the memory controller 3 operates as follows: The memory I / F circuit 16 provides the codewords read from each memory chip 4 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 13. The CPU 11 sends the data stored in the RAM 13 to the host 2 via the host I / F circuit 15.

[0021] Figure 3 is a block diagram illustrating an example of the configuration of memory chip 4. Memory chip 4 includes a NAND I / O interface 21, control circuitry 22, a NAND memory cell array 23, bit line drivers 24, and word line drivers 25. The NAND I / O interface 21 receives control signals output from the memory controller 3, such as the write enable signal WEn, the read enable signal REn, the address latch enable signal ALE, and the instruction latch enable signal CLE. Furthermore, the NAND I / O interface 21 receives instructions, addresses, and data output from the memory controller 3.

[0022] The bit line driver 24 is configured to independently apply voltage (or current) to a plurality of bit lines BL and to independently detect the voltage (or current) of the plurality of bit lines BL. The character line driver 25 is configured to independently apply voltage to a plurality of character lines and select gate lines. The control circuit 22 receives control signals, instructions, addresses, and data from the NAND I / O interface 21 and controls the operation of the memory chip 4 based on these. For example, the control circuit 22 controls the word line driver 25 and the bit line driver 24 based on the control signals, instructions, addresses, and data, and performs write operations, read operations, delete operations, etc.

[0023] The voltage supplied to the bit line driver 24 and the word line driver 25 is generated by the voltage generation circuit 26. The voltage generation circuit 26 is controlled by the control circuit 22 and generates the necessary voltage. For example, the control circuit 22 controls the voltage generation circuit 26 and controls the voltage applied to a plurality of word lines WL by the word line driver 25 and the voltage applied to a plurality of bit lines BL by the bit line driver 24 (bit line voltage). In this way, writing to the memory cells (memory cell transistors) MT contained in the NAND memory cell array 23, reading from the memory cell transistors MT, and deleting from the memory cell transistors MT are performed.

[0024] For example, when a write command is input, the control circuit 22 controls the bit line driver 24 and the word line driver 25 by writing the data input along with the write command to the designated address on the NAND memory cell array 23. Similarly, when a read command is input, the control circuit 22 controls the bit line driver 24 and the word line driver 25 by reading the data from the designated address on the NAND memory cell array 23. (Host commands)

[0025] When recording data, CPU 2a of host 2 generates a write instruction and sends the logical address of the data (e.g., the start address and data capacity) along with the write instruction to memory controller 3. Similarly, when reading data, CPU 2a generates a read instruction and sends the logical address of the data (e.g., the start address and data capacity) along with the read instruction to memory controller 3. Furthermore, during data recording, for example, a write operation is performed using a method that maximizes the number of bits obtained at the memory device. Furthermore, in this embodiment, CPU2a is configured to generate a high-speed read preparation instruction at a specific timing point before data is read. This first instruction, the high-speed read preparation instruction, is used to implement a mode at the memory controller 3 where data written in a large number of bits is temporarily read and then re-written in a smaller number of bits (hereinafter referred to as the high-speed read preparation mode). When sending the high-speed read preparation instruction, CPU2a sends the logical address information of the data with a high probability of being read to the memory controller 3.

[0026] For example, in game data or OS (operating system) data, there is data that is frequently used or data that needs to be read at a higher speed than other data. Furthermore, there are also situations where "the probability of accessing the written data immediately after it is written is high (temporal locality)" or "the probability of accessing data at addresses adjacent to the address of the read data is high (spatial locality)." CPU2a possesses this knowledge related to data access, and assigns the logical address of this data (hereinafter referred to as high-speed read data) and sends a signal to the memory controller 3 together with the high-speed read preparation instruction.

[0027] Additionally, during writing, the writing method corresponding to SLC can also be considered. However, it's not only data that needs constant high-speed reading; there are also cases where data depends on program characteristics and only needs high-speed reading for a specific period. The high-speed read preparation instruction in this embodiment is extremely effective when high-speed reading is desired for a certain period.

[0028] Figure 4 is an illustrative diagram showing one example of the instruction format used to implement the high-speed read preparation instruction and the write-back instruction described later. In the example in Figure 4, it is for a UFS device.

[0029] In the UFS communication protocol, in order to send commands from the host to the device, the instruction UPIU (UFS Protocol Information Unit) is used. However, the CDB (Command Descriptor Block) of bytes

[16] to bytes

[31] is used to implement various types of commands. The example in Figure 4 is a format example of high-speed read preparation command and write-back command that utilizes this CDB. The OPERATION CODE is the command number for newly set instructions. In MODE, information is recorded that distinguishes between a "high-speed read preparation instruction" and a "write-back instruction." LOGICAL BLOCK ADDRESS represents a logical address. TRANSFER LENGTH represents the capacity of the data as an object.

[0030] For example, host 2 sends a high-speed read preparation instruction in the format shown in Figure 4 to memory controller 3. CPU 11 of memory controller 3, upon receiving the high-speed read preparation instruction, executes high-speed read preparation mode. That is, CPU 11 refers to the data expanded in LUT 13a to convert the logical address specified by host 2 into a physical address. CPU 11 then sends the converted address and read instruction to memory chip 4. Consequently, the control circuit 22 of memory chip 4 drives bit line driver 24 and word line driver 25 to read the data specified by host 2 from the address specified by memory controller 3 and sends the data to memory controller 3. CPU 11 stores the read data in RAM 13.

[0031] Furthermore, CPU 11 selects a write mode that results in a smaller number of bits compared to the write mode used for high-speed data reading, to write the data stored in RAM 13 to memory chip 4. In this case, CPU 11 specifies the address corresponding to the write mode. That is, CPU 11 converts the physical address of the read data into a physical address corresponding to the write mode, updates LUT 13a, and sends this physical address and write instruction to memory chip 4. The control circuit 22 of memory chip 4 drives bit line driver 24 and word line driver 25 based on the specified address, and writes the data using the specified write mode. (effect)

[0032] Next, referring to Figures 5 to 8, the operation of the embodiment configured in this way will be explained. Figure 5 shows the timing table for reading in the first embodiment, and Figure 6 shows the timing diagram for writing and reading in the comparative example. Furthermore, Figure 7 shows the memory mapping used to explain the memory regions of the memory chip 4, and Figure 8 is a flowchart showing the operation of the first embodiment.

[0033] First, the write and read operations of the comparative example shown in Figure 6 will be explained. When writing, the host 2 generates a write command and outputs the logical address of the data to be written (start address (X) and data capacity (Y)) and the write data to the memory controller 3 (Figure 6(1), (2)). The memory controller 3 converts the logical address of the write data to a physical address through logic-to-physical conversion, updates the LUT13a, and sends the write data to the memory chip 4 by specifying the converted physical address. The memory chip 4 writes the write data to the memory area of ​​the NAND memory cell array 23 specified by the physical address. In addition, the memory controller 3 instructs the memory chip 4 to write the data in a manner corresponding to a specific number of cells. For example, in the case of the memory chip 4 corresponding to QLC, the write is performed in a manner corresponding to QLC (Figure 6(3), multi-value data writing).

[0034] Next, assume that host 2 reads the data written to memory chip 4. In this case, host 2 generates a read instruction and outputs the logical address (start address (X) and data capacity (Y)) of the data to be read to memory controller 3 (Fig. 6(4)). Memory controller 3 refers to the information expanded in LUT13a, converts the logical address of the read data into a physical address, and reads the data from memory chip 4 by specifying the converted physical address (Fig. 6(5), multi-value data read). This data is written, for example, in a write mode with a large number of cells such as QLC. The control circuit 22 of memory chip 4 performs read control corresponding to this write mode, obtains the read data, and transmits it to memory controller 3. Memory controller 3 transmits the received read data to host 2 and sends back a read response (Fig. 6(6), (7)). As mentioned above, the tR system will increase when reading data written in a write mode that prioritizes the number of bits.

[0035] In this embodiment, the write operation is the same as in the comparative example. In this embodiment, during the read operation, a high-speed read preparation mode is implemented before the actual read operation, which is different from the comparative example. Figure 5 only shows the read operation. During the read operation, the host 2 generates a high-speed read preparation instruction at a specific timing point before the actual read operation. That is, the CPU 2a of the host 2 sends the logical address (start address (X) and data capacity (Y)) of the data (high-speed read data) that needs to be read at high speed and the high-speed read preparation instruction to the memory controller 3 (Figure 5(1)). The CPU 11 of the memory controller 3 is in a standby state with the high-speed read preparation mode indication at point S1 in Figure 8. If the CPU 11 receives the high-speed read preparation instruction and the logical address (YES determination in S1), it implements the high-speed read preparation mode. That is, CPU 11, referring to the information expanded in LUT 13a, converts the received logical address into a physical address (S2), and controls the reading of data from memory chip 4 by specifying the converted physical address (hereinafter referred to as read-out control). The data that has been read out is, for example, written in a write mode with a large number of cells such as QLC. The control circuit 22 of memory chip 4 performs a read corresponding to this write mode (Fig. 5(2), multi-value data read), obtains high-speed read data, and transmits it to memory controller 3 (S4).

[0036] In the read preparation control, CPU 11 stores the received high-speed read data in RAM 13. CPU 11 writes the high-speed read data read by the read preparation control to memory chip 4 in a write mode that sets the cell number to a smaller (reducing tR) (Fig. 5(3)). For example, when the high-speed read data is written in a write mode corresponding to QLC, it is written in a write mode corresponding to TLC, MLC, or SLC. CPU 11 sets the memory area to be written again by the high-speed read data read by the read preparation control, and updates LUT 13a accordingly. CPU 11 sends the instruction for controlling the rewriting of high-speed read data (hereinafter referred to as write preparation control) to memory chip 4 along with the address of the write target (S6). The control circuit 22 of the memory chip 4 writes high-speed read data to the memory region of the designated NAND memory cell array 23 (S7). In this case, the control circuit 22 controls each part by writing in a method that reduces tR (reduces the number of cell bits). For example, it writes in a method corresponding to SLC.

[0037] Figure 7 illustrates the memory regions before and after this write preparation control. In the example of Figure 7, the NAND memory cell array 23 is configured with two memory regions: an "SLC region for writing in the SLC write mode" and a "QLC region for writing in the QLC write mode". Furthermore, although SLC / QLC write modes are configured, the regions used for each mode are not completely fixed. The SLC region includes a management area and a LUT (Logical-Physical Translation Table) region. Here, for example, it is assumed that high-speed read data is written to region R4 in the QLC region during writing. In the high-speed read preparation mode, the high-speed read data written to region R4 by the memory controller 3 is read out by read preparation control and written to, for example, region R3 in the SLC region by write preparation control. At the point when the high-speed read preparation mode is completed, the physical address of the high-speed read data stored in LUT13a becomes the representative area R3. If the CPU 11 of the memory controller 3 terminates the write preparation control as the first write control, it generates a high-speed read preparation instruction response indicating that the high-speed read preparation instruction has been completed and sends the signal to the host 2 (Figure 5(4)). Then, this high-speed read preparation instruction response can also be omitted by the host 2.

[0038] Next, assume that host 2 is reading high-speed data written to memory chip 4. In this case, host 2 generates a read instruction and outputs the logical address (start address (X) and data capacity (Y)) of the high-speed data to be read to memory controller 3 (Figure 5(5)). At S8, memory controller 3 is in standby state for read instruction. If it receives a read instruction (YES determination in S8), it refers to the information in LUT13a, converts the logical address of the high-speed data to a physical address, and specifies the converted physical address (for example, the physical address representing region R3 in Figure 7) to read the data from memory chip 4 (S9, Figure 5(6)). This high-speed data is written by preparing write control, which is a write method with a small number of cells such as SLC. The control circuit 22 of memory chip 4 performs read control corresponding to this write method to obtain high-speed data. Control circuit 22 transmits the read high-speed data to memory controller 3. Memory controller 3 transmits the received high-speed data to host 2 and responds to host 2's read requests (Figure 5(7), (8)). The high-speed data is written in a tR-small (small number of bits) write mode, thus enabling high-speed reading.

[0039] In this embodiment, by re-recording the data that has already been recorded according to the requirements from the host, changing the write method to make tR smaller, it is possible to improve read performance. This prevents the data transfer speed from the memory device to the host from being limited by tR, enabling high-speed data reading. Furthermore, by targeting only the data specified by the host, it is possible to suppress any adverse effects on the device's recordable capacity. (Second Implementation)

[0040] Figure 9 is a flowchart illustrating the action flow used in the second embodiment. In Figure 9, the same component symbols are added for the same processing procedures as in Figure 8, and the explanations are omitted. The hardware configuration of this embodiment is the same as that of the first embodiment, so the explanation is omitted. In the first embodiment, read performance is improved by employing a high-speed read preparation mode. However, since data recorded using a large number of bits is re-recorded using a smaller number of bits, the recording density of the memory cell transistor is reduced, and the capacity that the memory device can record is reduced. Therefore, this embodiment controls the write-back of data that no longer requires high-speed reading using a larger number of bits.

[0041] Host 2, identical to the first embodiment, is capable of issuing high-speed read preparation instructions and, as a second instruction, a write-back instruction. This write-back instruction is used to write back data set as high-speed read data in a write mode with tR greater than (greater number of bits), such as a write mode during recording. Furthermore, at memory controller 3, when a memory region is set to "write high-speed read data via write preparation control," host 2 may issue a write-back instruction without specifying a logical address corresponding to each individual high-speed read data. Also, at memory controller 3, when restoring each individual high-speed read data to data read at normal speed, a logical address is issued along with the write-back instruction to specify the high-speed read data to be written back.

[0042] The CPU 11 of the memory controller 3 determines whether a read instruction has occurred at point S8 in Figure 9. If there is no read request (NO determination in S8), it determines whether there is a write-back instruction or a power-off instruction at point S10. If there is no write-back instruction or power-off instruction (NO determination in S10), the CPU 11 returns the processing to point S8 and determines whether a read request has occurred.

[0043] Now, assume that host 2 generates a write-back instruction and sends it to memory controller 3. If CPU 11 of memory controller 3 receives this write-back instruction (S10 YES determination), it performs write-back control by writing back the high-speed read data in a larger number of bits format. That is, in the write-back control, CPU 11 specifies the physical address of the memory region containing the high-speed read data stored in LUT 13a and reads it (S11). CPU 11 stores the read data in RAM 13. Next, CPU 11 converts the physical address of the memory region containing the high-speed read data stored in LUT 13a to the physical address of the memory region corresponding to the larger number of bits format and updates the contents of LUT 13a (S12). CPU 11 specifies the updated physical address and sends a write-back instruction for high-speed read data to memory chip 4 (S13).

[0044] The control circuit 22 of the memory chip 4 writes the write-back data to the designated memory region of the NAND memory cell array 23 (S14). In this case, the control circuit 22 controls each part by either increasing tR (increasing the number of cells) or by reverting to the original write method. For example, in the case of the memory chip 4 corresponding to QLC, the write is performed in the QLC-compliant write method.

[0045] Additionally, host 2, when powered off, can also issue a write-back command before power-off and control the re-recording of all high-speed read data in a larger number of bits. Alternatively, memory controller 3, if given a power-off instruction, can also control the re-recording of all high-speed read data in a larger number of bits before power-off, even without receiving a write command. Figure 9, S10, illustrates an example of this situation. In addition, before the power is turned off, the CPU11 transfers the contents of LUT13a to the memory chip 4 and stores them in region R2 of the NAND memory cell array 23.

[0046] In this embodiment, by using write-back instructions, the host system can retain necessary data by writing it in a manner where tR is small (small number of bits) only when necessary. This allows for improved read performance while suppressing the impact on the overall capacity of the memory device. (Modified Example)

[0047] Figure 10 is a block diagram illustrating a modified example. In Figure 10, the same component symbols are added for the same constituent elements as in Figure 2, and the explanations are omitted.

[0048] In the second embodiment, by performing read preparation control, high-speed read data recorded in a write mode with a number of bits is read in a state where it will be unusable later (hereinafter referred to as move mode read). However, if write-back control is required, high-speed read data recorded in a write mode with a number of bits can also be configured to be read in a state where "its area is not deleted but left as a residue" (hereinafter referred to as copy mode read). Therefore, in this embodiment, during read preparation control, the memory area of ​​high-speed read data recorded in a write mode with a number of bits is pre-memorized, and during write-back control, the area where the high-speed read data was recorded, such as the SLC area, is set to be deletable, and LUT13a is updated using the information of the memorized memory area. For example, CPU 11 enables copy-mode reads by storing information in region LUTS 13b of RAM 13 regarding the correspondence between the physical address and logical address of the memory region where high-speed read data is recorded in a write mode with a number of bits as the maximum. Then, during write-back control, CPU 11 uses the information in LUT 13b to update LUT 13a.

[0049] Figure 11 is a flowchart illustrating the actions required in this situation. In Figure 11, the same component symbols are added for the same processing procedure as in Figure 8, and the explanations are omitted. As shown in Figure 11, if a read is performed due to read preparation control, the CPU 11 registers the correspondence between the "physical address that was read" and the "logical address" in LUTS 13b (S21). Furthermore, the CPU 11 updates LUT 13a using the physical address of the write target of the write preparation control (S5). Therefore, in subsequent high-speed data reads, high-speed data written in a small number of bits is read. On the other hand, when a write-back instruction is received, or when a power-off indication is present (YES determination in S10), the CPU 11 reads the correspondence between the physical address and logical address where the high-speed data was originally written from LUTS 13b and updates the physical address information stored in LUT 13a regarding the correspondence between physical and logical addresses (S22). In this way, high-speed read data stored in the NAND memory cell array 23 by writing in a way that is large in number of cells is then read out, thereby reducing the impact on the capacity of the memory area.

[0050] Thus, in this variant, in the high-speed read preparation mode, by not setting the high-speed read data read through the read preparation control to a deleteable state, even when write-back control is implemented, it is possible to simply modify the logic-physical translation table to omit the read and write operations used for write-back control.

[0051] Furthermore, although the above description focused on an example where the memory controller 3 performs either a read in move mode or a read in copy mode, these read modes can also be configured to be switchable. For example, the memory controller 3 can be configured to dynamically switch between read in copy mode when the free capacity is greater than a certain threshold value, and read in move mode when the free capacity is below a certain threshold value. Furthermore, host 2 can also attach an ID to the data, and when the power is off, it can pre-determine whether to perform high-speed read data with write-back control or high-speed read data without write-back control based on the ID. Here, memory controller 3 only needs to record the correspondence between ID, logical address, and physical address in RAM 13. If a power-off indication occurs, it can refer to the ID and determine the high-speed read data to perform write-back control. (Modified Example)

[0052] Figure 12 is a flowchart illustrating a modified example. In the above embodiments, the example described is that "CPU 11, when performing write preparation control, selects a write method with a smaller tR (smaller number of cells) than the original write method of the high-speed read data." This embodiment illustrates one example of this selection. In Figure 12, CPU 11 acquires the original write mode of high-speed read data, that is, acquires the write mode of high-speed read data recorded in NAND memory cell array 23 before preparing write control (S31). For example, assuming that this write mode is for QLC, then the write mode corresponding to SLC, MLC or TLC becomes a candidate as the write mode when preparing write control.

[0053] CPU 11 controls RAM 13 and host I / F circuit 15 to obtain information on host interface speed and free capacity of NAND memory cell array 23 (S32, S33). Based on the obtained information, CPU 11 determines the write method to be used when preparing write control. That is, CPU 11 adopts a write method that can obtain the tR (number of cells) required to achieve maximum read performance faster than the host interface speed. For example, if maximum read performance faster than the host interface speed can be obtained, it is not limited to SLC, but can also use write methods corresponding to TLC or MLC. In addition, when CPU 11 cannot obtain sufficiently high maximum read performance, it selects the write method corresponding to SLC. Furthermore, the CPU11 employs a write method that ensures sufficient free capacity. For example, when a maximum read performance that is faster than the host interface speed can be obtained regardless of whether the write method corresponding to SLC, MLC, or TLC is used, the system can also adopt a write method that will make the free capacity larger, depending on the size of the free capacity.

[0054] In this way, in this variation, it is possible to improve the maximum read performance while ensuring sufficient free capacity. This invention is not limited to the embodiments described above. Various modifications can be made during the implementation phase without departing from the spirit of the invention. Furthermore, the embodiments described above encompass inventions at various stages, and various inventions can be derived by appropriately combining the disclosed constituent elements. For example, if deleting several constituent elements from all those disclosed in the embodiments can solve the problem described in the "Problem Solved by the Invention" section and achieve the effect described in the "Effects of the Invention" section, then the structure in which the constituent elements are deleted can also be derived as an invention.

[0055] 1: Memory System 2: Host 2a: CPU 3: Memory controller 4: Memory chip 11: CPU 12:ROM12 13: RAM 13a:LUT 13b:LUTS 14: ECC circuit 15: Host I / F circuit 16: Memory I / F circuit 17: Internal Busbar 21: NAND I / O Interface 22: Control Circuit 23: NAND Memory Cell Array 24: Bit line driver 25: Character line driver 26: Voltage generation circuit

Claims

1. A memory system comprising a memory chip and a control chip, the memory chip comprising: a memory cell array including a first data region and a second data region; and a first interface circuit configured to receive a programming instruction for storing data at a certain address in the memory cell array; and a first control circuit configured to control a programming operation of programming data to the first data region based on the programming instruction and the address, the control chip comprising: a second interface circuit configured to receive a write instruction including data and an address from a host; and a second control circuit configured to issue an instruction to the memory chip regarding the programming instruction based on the write instruction. When the aforementioned control chip receives the first instruction from the aforementioned host, the aforementioned second control circuit is configured to read the data written by the first write method corresponding to the first number of cells from the aforementioned first data area, and then rewrite the previously read data to the aforementioned second data area by the second write method corresponding to the second number of cells, which is smaller than the aforementioned first number of cells. When a read instruction corresponding to the previously read data related to the aforementioned first instruction is received from the aforementioned host after the aforementioned first instruction, the aforementioned second control circuit is configured to read the rewritten data from the aforementioned second data area and transmit the aforementioned data to the aforementioned host.

2. The memory system as described in claim 1, wherein, The aforementioned first cell number is 4, and the aforementioned second cell number is 1.

3. The memory system as described in claim 1, wherein, The first writing method mentioned above is the MLC (Multi Level Cell) writing method, and the second writing method mentioned above is the SLC (Single Level Cell) writing method.

4. The memory system as described in claim 1, wherein, The first writing method mentioned above is the QLC (Quad Level Cell) writing method, and the second writing method mentioned above is the SLC (Single Level Cell) writing method.

5. The memory system as described in claim 4, wherein, The aforementioned first interface circuit is the UFS (Universal Flash Storage) standard interface.

6. The memory system as described in claim 1, wherein, The aforementioned first interface circuit is the UFS (Universal Flash Storage) standard interface.

7. The memory system as described in claim 6, wherein, The aforementioned control chip stores a lookup table. The aforementioned second control circuit is configured to modify the aforementioned lookup table in response to the aforementioned rewrite after receiving the aforementioned first instruction. The aforementioned lookup table is modified to reflect the movement of data from the aforementioned first data area to the aforementioned second data area caused by the aforementioned rewrite.

8. The memory system as described in claim 1, wherein, The aforementioned control chip stores a lookup table. The aforementioned second control circuit is configured to modify the aforementioned lookup table in response to the aforementioned rewrite after receiving the aforementioned first instruction. The aforementioned lookup table is modified to reflect the movement of data from the aforementioned first data area to the aforementioned second data area caused by the aforementioned rewrite.

9. A memory controller chip comprising: a host interface circuit configured to receive a write instruction containing data and an address from a host; and a control circuit configured to issue programmed instructions to the memory chip based on the write instruction, wherein when the host interface circuit receives a first instruction from the host, the control circuit is configured to read data written from a first data area in the memory chip using a first write method corresponding to a first number of cells, and then rewrite the previously read data to a second data area in the memory chip using a second write method corresponding to a second number of cells smaller than the first number of cells. When the host interface circuit receives a read instruction from the host corresponding to the data read in relation to the first instruction after the first instruction, the control circuit is configured to read the rewritten data from the second data area and transmit the data to the host via the host interface circuit.

10. The memory controller chip as described in claim 9, wherein, The aforementioned first cell number is 4, and the aforementioned second cell number is 1.

11. The memory controller chip as described in claim 9, wherein, The first writing method mentioned above is the MLC writing method, and the second writing method mentioned above is the SLC writing method.

12. The memory controller chip as described in claim 9, wherein, The first writing method mentioned above is the QLC writing method, and the second writing method mentioned above is the SLC writing method.

13. The memory controller chip as described in claim 12, wherein, Furthermore, the system includes: a memory interface circuit, which is connected to the aforementioned memory chip, and the aforementioned memory interface circuit is a UFS standard interface.

14. The memory controller chip as described in claim 9, wherein, Furthermore, the system includes: a memory interface circuit, which is connected to the aforementioned memory chip, and the aforementioned memory interface circuit is a UFS standard interface.

15. The memory controller chip as described in claim 9, wherein, The aforementioned control chip stores a lookup table. The aforementioned control circuit is configured to modify the aforementioned lookup table in response to the aforementioned rewrite after receiving the aforementioned first instruction. The aforementioned lookup table is modified to reflect the movement of data from the aforementioned first data area to the aforementioned second data area caused by the aforementioned rewrite.

16. A memory control method, comprising: receiving a write instruction containing data and an address from a host; and instructing a memory chip to issue programmed instructions based on the aforementioned write instruction, wherein... When the host receives the first instruction, the data written using the first write method corresponding to the first number of bits is read from the first data area of ​​the memory chip. Then, the data that was just read is rewritten to the second data area of ​​the memory chip using the second write method corresponding to the second number of bits, which is smaller than the first number of bits. When the host receives a read instruction corresponding to the data read in relation to the first instruction after the first instruction, the rewritten data is read from the second data area and then transmitted to the host.

17. The memory control method as described in claim 16, wherein, The aforementioned first cell number is 4, and the aforementioned second cell number is 1.

18. The memory control method as described in claim 16, wherein, The first writing method mentioned above is the MLC writing method, and the second writing method mentioned above is the SLC writing method.

19. The memory control method as described in claim 16, wherein, The first writing method mentioned above is the QLC writing method, and the second writing method mentioned above is the SLC writing method.

20. The memory control method as described in claim 16, wherein, This is in response to the rewrite that occurred after receiving the first instruction. The lookup table stored in the control chip is modified to reflect the movement of data from the first data area to the second data area caused by the rewrite.

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