Methods of forming bottom dielectric isolation layers

Abstract

The embodiments disclosed herein relate to a method for removing dummy material from beneath a superlattice structure. In some embodiments, after removing the dummy material, a bottom dielectric isolation layer is used to replace the superlattice structure.

Claims

1. A method for removing a dummy material, comprising the steps of: forming a pad on a transistor structure on a dummy material, the dummy material comprising one or more of silicon (Si) or silicon germanium (SiGe); removing the pad from the dummy material; and removing the dummy material without substantially affecting the transistor structure covered by the pad.

2. The method as described in claim 1, wherein the gasket comprises silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonoxynitride (SiCON), or a combination thereof.

3. The method as described in claim 1, wherein the step of removing the pad includes a directional etching process.

4. The method as described in claim 1, wherein the step of removing the dummy material includes a selective etching process that is more selective for the dummy material than for the pad.

5. The method as described in claim 1, wherein the step of removing the dummy material includes a selective etching process that is more selective to the dummy material than to the transistor structure.

6. The method as described in claim 4, wherein the selective etching process comprises a wet etching process using one or more of trimethylammonium hydroxide (TMAH), ammonium hydroxide, ozone, and water.

7. The method as described in claim 5, wherein the selective etching process comprises a wet etching process using one or more of trimethylammonium hydroxide (TMAH), ammonium hydroxide, ozone, and water.

8. The method as described in claim 1 further comprises the step of: depositing a bottom dielectric isolation layer beneath the transistor structure after removing the dummy material.

9. The method as described in claim 8, wherein the bottom dielectric isolation layer is deposited by a flowable deposition process.

10. The method as described in claim 8, wherein the bottom dielectric insulating layer comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (Al2O3), and hafnium oxide (HfO2).

11. The method as described in claim 8, wherein the bottom dielectric isolation layer comprises silicon oxide (SiOx).

12. The method as described in claim 1, wherein the transistor structure includes a gate-around (GAA) or a FinFET.

13. The method as described in claim 1, wherein the thickness of the pad is in the range of about 3 nm to about 5 nm.

14. The method as described in claim 1, wherein the dummy material is essentially composed of silicon (Si).

15. The method as described in claim 1, wherein the dummy material is essentially composed of silicon germanium (SiGe).

16. The method as described in claim 1, wherein the silicon (Si) is doped with a dopant selected from one or more of boron, phosphorus, arsenic or germanium.

17. The method as described in claim 16, wherein the concentration of the dopant is in the range of 2 atomic percent to 10 atomic percent.

18. The method as described in claim 1, wherein the silicon germanium (SiGe) is doped with one or more of boron, phosphorus or arsenic.

19. The method as described in claim 18, wherein the concentration of the dopant is in the range of 2 atomic percent to 10 atomic percent.

20. The method as described in claim 1, wherein the step of forming the pad includes atomic layer deposition.

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