Hardware controller

Abstract

A hardware controller includes a communication interface circuit, temporary storage memory, and a controller. The controller is configured to: obtain target data and an address list from a host system, and store the target data and the address list in the temporary storage memory, wherein the address list contains address information corresponding to multiple hardware devices; obtain an update trigger command corresponding to the target data from the host system; extract target address information from the address list according to the update trigger command; and send a data update command containing the target data to the target hardware device according to the target address information, instructing the target hardware device to write the target data.

Description

Hardware controller HARDWARE CONTROLLER Technical Field

[0001] This new invention relates to a hardware controller. Prior Technology

[0002] As the performance of electronic devices such as laptops, industrial computers, and servers continues to improve and the services they support become increasingly diverse, a single electronic device may be equipped with multiple devices of the same type. For example, a laptop may have three to five USB ports, while a server may have more than ten. Each USB port may require a controller for independent communication and / or charge / discharge control (or a small number of USB ports may share a controller).

[0003] Traditionally, when the firmware or parameters of these controllers need to be updated, the processor of an electronic device (such as the southbridge chip) might issue firmware or parameter update commands to these controllers one by one to perform individual firmware or parameter updates. However, as the number of these controllers increases, such firmware or parameter updates require more time and system resources, making them uneconomical. In addition, most types of hardware devices do not support broadcast firmware or parameter updates due to factors such as outdated versions, leading to operational challenges for large-scale firmware or parameter update mechanisms. Summary of the Invention

[0004] This invention provides a hardware controller that improves the above-mentioned problems, thereby increasing the efficiency of data updates and management for multiple hardware devices.

[0005] This invention provides a hardware controller, including a communication interface circuit, a temporary storage memory, and a controller. The controller is coupled to the communication interface circuit and the temporary storage memory. The controller is configured to: obtain target data and an address list from a host system, and store the target data and the address list in the temporary storage memory, wherein the address list contains address information corresponding to multiple hardware devices, and the multiple hardware devices have the same hardware structure; obtain an update trigger command corresponding to the target data from the host system; extract target address information from the address list according to the update trigger command, wherein the target address information corresponds to a target hardware device among the multiple hardware devices; and send a data update command containing the target data to the target hardware device according to the target address information, so as to instruct the target hardware device to write the target data.

[0006] Based on the above, after obtaining the target data and address list from the host system, the target data and address list can be stored in the temporary memory of the hardware controller. Specifically, the address list can contain address information corresponding to multiple hardware devices. After obtaining an update trigger command corresponding to the target data from the host system, the target address information corresponding to the target hardware device can be extracted from the address list according to this update trigger command. Subsequently, a data update command containing the target data can be sent to the target hardware device based on this target address information to instruct the target hardware device to write the target data. Therefore, without the need for a broadcast update mechanism, the efficiency of data updates and management for multiple hardware devices can be effectively improved. Simple Explanation of the Diagram

[0007] Figure 1A is a schematic diagram of a hardware control system according to an embodiment of the present invention. Figure 1B is a schematic diagram of the hardware controller according to an embodiment of the present invention. Figure 2 is a schematic diagram illustrating the storage of target data and address list in temporary memory according to an embodiment of the present invention. Figure 3 is a schematic diagram illustrating a mobile reading indicator according to an embodiment of the present invention. Figure 4 is a schematic diagram illustrating a batch data update of a hardware device based on different sub-target data, according to an embodiment of the present invention. Figure 5 is a schematic diagram illustrating a write status list according to an embodiment of the present invention. Figure 6 is a flowchart illustrating a data update method according to an embodiment of the present invention. Figure 7 is a flowchart illustrating a data update method according to an embodiment of the present invention. Implementation

[0008] Figure 1A is a schematic diagram of a hardware control system according to an embodiment of the present invention. Referring to Figure 1A, the hardware control system 10 can be installed in various electronic devices such as smartphones, tablets, laptops, desktop computers, industrial computers, game consoles, servers, or computer mainframes installed in specific carriers (e.g., vehicles, aircraft, or ships), and the types of electronic devices are not limited thereto.

[0009] In one embodiment, the hardware control system 10 includes hardware devices 11(1) to 11(N) and a hardware controller 12. In another embodiment, the hardware control system 10 further includes a host system 13.

[0010] In one embodiment, hardware devices 11(1) to 11(N) are of the same type. For example, in one embodiment, hardware devices 11(1) to 11(N) may have the same hardware structure (including the same hardware circuit composition). Alternatively, in one embodiment, the hardware structures of hardware devices 11(1) to 11(N) may be completely identical. For example, the hardware circuit compositions of hardware devices 11(1) to 11(N) may be completely identical.

[0011] In one embodiment, hardware devices 11(1) to 11(N) may all be the same type of USB controller (e.g., USB Type-C controller). Alternatively, in one embodiment, hardware devices 11(1) to 11(N) may all be the same type of network communication controller, display controller, touch controller, or charging controller, etc., and this invention is not limited thereto. It should be noted that the number of hardware devices 11(1) to 11(N) is multiple. For example, N may be any integer greater than 1.

[0012] Hardware controller 12 is coupled to hardware devices 11(1) to 11(N). Hardware controller 12 can be used to control and / or manage hardware devices 11(1) to 11(N). For example, hardware controller 12 may include an embedded controller (EC), a micro-controller unit (MCU), or other types of controllers (or control circuits), and this invention is not limited thereto. In addition, hardware controller 12 can communicate with hardware devices 11(1) to 11(N) through communication interface standards such as I2C.

[0013] Figure 1B is a schematic diagram of the hardware controller according to an embodiment of the present invention. Referring to Figure 1B, the hardware controller 12 may include a controller 101, a communication interface circuit 102, and a temporary memory 103. The controller 101 is coupled to the communication interface circuit 102 and the temporary memory 103.

[0014] Controller 101 can be used to control the overall or partial operation of hardware controller 12. For example, controller 101 may include a microprocessor or other type of controller (or control circuitry), which is not limited by this invention. In the following embodiments, the description of operation of hardware controller 12 is equivalent to the description of operation of controller 101.

[0015] The communication interface circuit 102 is used to communicate with the hardware devices 11(1) to 11(N) and the host system 13. For example, the communication interface circuit 102 can communicate with the hardware devices 11(1) to 11(N) and the host system 13 through communication interface standards such as I2C.

[0016] Temporary memory 103 is used to temporarily store data. For example, temporary memory 103 may include random access memory (RAM), read-only memory (ROM), solid-state disk (SSD), universal flash storage (UFS), or similar storage media. The number of controller 101, communication interface circuit 102, and temporary memory 103 may be one or more, and this invention is not limited thereto.

[0017] Referring back to Figure 1A, in one embodiment, host system 13 is coupled to hardware controller 12. Host system 13 can be used to be responsible for (e.g., manage) the overall or partial operation of hardware control system 10 (or electronic devices configured with hardware control system 10). For example, host system 13 may include a central processing unit (CPU), graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar devices or combinations thereof.

[0018] In one embodiment, the hardware controller 12 may obtain data (also referred to as target data) and an address list from the host system 13. The target data may contain data to be synchronously written (i.e. updated) to hardware devices 11(1) to 11(N). For example, the target data may include firmware data and / or parameter data available for use by hardware devices 11(1) to 11(N). The address list may contain address information corresponding to hardware devices 11(1) to 11(N). For example, the address list may contain multiple address entries. Each address entry corresponds to one of hardware devices 11(1) to 11(N). For example, each address entry can be used to uniquely identify one of hardware devices 11(1) to 11(N). Subsequently, the hardware controller 12 may communicate with hardware devices 11(1) to 11(N) (e.g., transmit signals, commands, data, or responses) based on the address information in the address list.

[0019] In one embodiment, after obtaining the target data and address list, the hardware controller 12 can store the target data and address list in the temporary memory of the hardware controller 12 (e.g., the temporary memory 103 in FIG1B).

[0020] Figure 2 is a schematic diagram illustrating the storage of target data and address list in temporary memory according to an embodiment of the present invention. Referring to Figure 2, in one embodiment, the hardware controller 12 can simultaneously store the target data 21 and address list 22 in the temporary memory 20. In one embodiment, the temporary memory 20 can be disposed inside the hardware controller 12. For example, the temporary memory 20 may include the temporary memory 103 of Figure 1B. In one embodiment, the temporary memory 20 can also be disposed outside the hardware controller 12 and coupled to the hardware controller 12. Subsequently, the hardware controller 12 can access this temporary memory 20 to read the target data 21 and address list 22.

[0021] In one embodiment, the target data 21 may include data to be synchronously written (i.e. updated) to the hardware devices 11(1) to 11(N). For example, the target data 21 may include firmware data and / or parameter data that can be used by the hardware devices 11(1) to 11(N).

[0022] In one embodiment, the address list 22 may have multiple fields (also called address fields) 22(1) to 22(N). Address fields 22(1) to 22(N) may be used to record address information corresponding to hardware devices 11(1) to 11(N). For example, address field 22(i) may be used to record address information corresponding to hardware device 11(i), where i is an integer between 1 and N. It should be noted that the arrangement of target data 21 and address fields 22(1) to 22(N) in temporary memory 20 may also be adjusted according to practical needs, and this invention does not impose any limitations.

[0023] In one embodiment, after storing the target data and address list to temporary memory (e.g., temporary memory 20 in FIG2), the hardware controller 12 can obtain a trigger command (also known as an update trigger command) corresponding to the target data from the host system 13. This update trigger command can be used to trigger (or instruct) the hardware controller 12 to perform batch data updates on the hardware devices 11(1) to 11(N) based on the target data.

[0024] In one embodiment, after receiving an update trigger command corresponding to target data from the host system 13, the hardware controller 12 can extract specific address information (also referred to as target address information) from the address list currently stored in temporary memory, based on (or in response to) this update trigger command. The target address information corresponds to one of the hardware devices 11(1) to 11(N) (also referred to as the target hardware device). For example, assuming the target hardware device is hardware device 11(i), the target address information can be used to identify hardware device 11(i).

[0025] In one embodiment, after obtaining the target address information, the hardware controller 12 can send an update command (also called a data update command) containing target data to the target hardware device, instructing the target hardware device to write the target data. For example, this data update command can be used to instruct the target hardware device to update the target data in the target hardware device's storage medium (e.g., memory). This achieves the purpose of updating the firmware data and / or parameter data used by the target hardware device. Subsequently, the target hardware device can operate based on this target data (e.g., perform predetermined operating actions of the target hardware device).

[0026] In one embodiment, during the batch data update of hardware devices 11(1) to 11(N), each hardware device 11(1) to 11(N) is set as the target hardware device and the data update is performed one by one. Thus, the purpose of batch updating the firmware data and / or parameter data used by hardware devices 11(1) to 11(N) is achieved.

[0027] In one embodiment, during the batch data update of hardware devices 11(1) to 11(N), the data update command is sent to the target hardware device in a point-to-point manner based on the target address information, rather than being sent synchronously to hardware devices 11(1) to 11(N) via broadcast. This improves the compatibility (e.g., forward compatibility) between the data update method and hardware devices 11(1) to 11(N), preventing data update failures due to at least one of the hardware devices 11(1) to 11(N) not supporting the broadcast update mechanism.

[0028] Figure 3 is a schematic diagram illustrating the movement of a read pointer according to an embodiment of the present invention. Referring to Figure 3, in one embodiment, the hardware controller 12 may set (or adjust) a read pointer Pr in the temporary memory 20 so that the read pointer Pr sequentially points to one of the address fields 22(1) to 22(N). For example, the hardware controller 12 may move the read pointer Pr by adjusting the offset value (also called the address offset value). Then, the hardware controller 12 may extract the target address information from the address list 22 according to the read pointer Pr. For example, assuming that the target address information is the address information corresponding to the hardware device 11(i), the hardware controller 12 may adjust the address offset value to point the read pointer Pr to the address field 22(i). Then, the hardware controller 12 may read the address information corresponding to the hardware device 11(i) from the address field 22(i) according to the read pointer Pr.

[0029] In one embodiment, during the batch data update of hardware devices 11(1) to 11(N), the hardware controller 12 can extract address information (also called first address information) from one of the address fields 22(1) to 22(N) based on the address offset value (also called the first address field). The first address information can correspond to one of the hardware devices 11(1) to 11(N). After obtaining the first address information, the hardware controller 12 can send a data update command (also called the first data update command) with target data to the first hardware device based on the first address information to instruct the first hardware device to write the target data.

[0030] On the other hand, after obtaining the first address information, the hardware controller 12 can extract address information (also called second address information) from another address field (also called second address field) among the address fields 22(1) to 22(N) according to another address offset value (also called second address offset value). The second address information can correspond to another hardware device (also called second hardware device) among the hardware devices 11(1) to 11(N). After obtaining the second address information and sending the first data update command, the hardware controller 12 can send a data update command (also called second data update command) with target data to the second hardware device according to the second address information, so as to instruct the second hardware device to write the target data.

[0031] Taking Figure 3 as an example, assume that the first hardware device and the second hardware device are hardware devices 11(1) and 11(2), respectively. Furthermore, for ease of explanation, assume that the initial position of the read index Pr points to the target data 21. When the read index Pr is in the initial position, the hardware controller 12 can read the target data 21 from the temporary memory 20 through the read index Pr.

[0032] In one embodiment, after obtaining the target data 21, the hardware controller 12 can move the read index Pr according to the address offset value ΔS(1) (i.e., the first address offset value), so that the read index Pr points to the address field 22(1) (i.e., the first address field), and read the address information (i.e., the first address information) corresponding to the hardware device 11(1) from the address field 22(1). Then, the hardware controller 12 can generate a data update command (i.e., the first data update command) with the target data 21 according to the target data 21 and the first address information, and send the first data update command to the hardware device 11(1) to instruct the hardware device 11(1) to write the target data 21.

[0033] In one embodiment, after obtaining the address information (i.e., the first address information) corresponding to the hardware device 11 (1), the hardware controller 12 can restore the read index Pr to the initial position and read the target data 21 from the temporary memory 20 again.

[0034] In one embodiment, after reacquiring the target data 21, the hardware controller 12 can move the read index Pr according to the address offset value ΔS(2) (i.e., the second address offset value), so that the read index Pr points to the address field 22(2) (i.e., the second address field), and read the address information (i.e., the second address information) corresponding to the hardware device 11(2) from the address field 22(2). Then, the hardware controller 12 can generate a data update command (i.e., the second data update command) with the target data 21 according to the target data 21 and the second address information, and send the second data update command to the hardware device 11(2) to instruct the hardware device 11(2) to write the target data 21.

[0035] In one embodiment, the first hardware device and the second hardware device mentioned above can also refer to hardware devices 11(i) and 11(j) in hardware devices 11(1) to 11(N), as long as i is different from j.

[0036] In one embodiment, the hardware controller 12 can repeatedly read the target data 21 from the temporary memory 20 by adjusting the read index Pr. Alternatively, the hardware controller 12 can also adjust the read index Pr to read the address information corresponding to the hardware devices 11(1) to 11(N) one by one from the address fields 22(1) to 22(N). After generating data update commands corresponding to the hardware devices 11(1) to 11(N) one by one and sending the data update commands to the hardware devices 11(1) to 11(N) one by one, batch data updates for the hardware devices 11(1) to 11(N) can be completed.

[0037] In one embodiment, the hardware controller 12 may further divide the target data (e.g., target data 21 in FIG2) into multiple sub-target data. Then, the hardware controller 12 may perform batch data updates on the hardware devices 11(1) to 11(N) based on different sub-target data in different data update stages until the target data is completely updated to the hardware devices 11(1) to 11(N) one by one.

[0038] Figure 4 is a schematic diagram illustrating batch data updates of a hardware device based on different sub-target data according to an embodiment of the present invention. Referring to Figure 4, in one embodiment, the hardware controller 12 can split target data (e.g., target data 21 in Figure 2) into sub-target data 41 (also referred to as first sub-target data) and sub-target data 42 (also referred to as second sub-target data). For example, the data size of each sub-target data may not exceed a preset data size (e.g., 64G or 128G). Furthermore, the preset data size can be adjusted according to practical needs.

[0039] In one embodiment, during the first update phase, the hardware controller 12 can set each of the hardware devices 11(1) to 11(N) as the target hardware device. Based on the target address information, the hardware controller 12 can send a data update command (also called a first-phase data update command) containing sub-target data 41 to the target hardware device, instructing the target hardware device to write the sub-target data 41. Related operational details can be found in the description of the embodiment in Figure 3, and will not be repeated here. After the first update phase has completed updating the sub-target data 41 to the hardware devices 11(1) to 11(N) one by one, the second update phase can proceed.

[0040] In one embodiment, during the second update phase, the hardware controller 12 can set each of the hardware devices 11(1) to 11(N) as a target hardware device. Based on the target address information, the hardware controller 12 can send a data update command (also known as a second-phase data update command) containing sub-target data 42 to the target hardware device to instruct the target hardware device to continue writing the sub-target data 42. Thus, the complete target data (including sub-target data 41 and 42) can be batch-updated (i.e., written) to the hardware devices 11(1) to 11(N).

[0041] In one embodiment, by updating multiple different sub-data in the target data to the hardware devices 11(1)~11(N) in batches at different stages, it can be ensured that the data update operation (i.e., the data write operation) can be executed normally in each data update stage, and abnormal situations such as data update failure due to the large amount of target data to be updated can be avoided. The relevant operational details can be referred to the description of the embodiment in FIG3, and will not be repeated here.

[0042] In one embodiment, during the first update phase, after updating the sub-target data 41 to the target hardware device, the hardware controller 12 may perform a write verification on the target hardware device. This write verification can be used to confirm whether the sub-target data 41 has been completely updated to the target hardware device. For example, during the write verification in the first update phase for the target hardware device, the hardware controller 12 may attempt to read the previously written sub-target data 41 from the target hardware device and confirm the data integrity of the sub-target data 41 read from the target hardware device.

[0043] In one embodiment, if the data integrity of the sub-target data 41 read from the target hardware device meets the requirements (e.g., the bit error rate of the sub-target data 41 read from the target hardware device is lower than the error rate threshold), the hardware controller 12 can determine that the target hardware device has passed the write verification. Conversely, if the data integrity of the sub-target data 41 read from the target hardware device does not meet the requirements (e.g., the bit error rate of the sub-target data 41 read from the target hardware device is not lower than the error rate threshold), the hardware controller 12 can determine that the target hardware device has failed the write verification. Furthermore, the hardware controller 12 can also verify the data integrity of the sub-target data 41 read from the target hardware device through other technical means; this invention is not limited in these ways.

[0044] In one embodiment, if the target hardware device has passed the write verification of the first update phase, the hardware controller 12 may then initiate the second update phase for the target hardware device. Related operational details can be found in the embodiment shown in FIG4, and will not be repeated here. However, if the target hardware device fails the write verification of the first update phase, the hardware controller 12 may not initiate (or disable) the second update phase for the target hardware device.

[0045] In one embodiment, if a target hardware device fails the write verification in the first update phase, it will be skipped upon entering the second update phase. For example, assuming hardware device 11(i) fails the write verification in the first update phase, it will be skipped upon entering the second update phase (i.e., the sub-target data 42 will not be updated to hardware device 11(i)). However, other hardware devices that pass the write verification (e.g., hardware device 11(j)) can continue to have the sub-target data 42 written to them in the second update phase.

[0046] In one embodiment, by stopping or suspending the next stage of data updates for at least some hardware devices that have previously experienced data update errors, the quality of data updates for each hardware device can be ensured, thereby improving the operational stability when performing batch data updates on hardware devices 11(1) to 11(N).

[0047] In one embodiment, after sending a data update command to the target hardware device, the hardware controller 12 can also obtain response information from the target hardware device. This response information can reflect the data writing status of the target hardware device for the target data. For example, this data writing status can include basic data writing success or data writing failure.

[0048] In one embodiment, if a data write failure occurs, the data write status may include one or more error states. After obtaining the response information, the hardware controller 12 may also update the status list (also called the write status list) corresponding to the hardware devices 11(1)~11(N) in the temporary memory (e.g., the temporary memory 20 in FIG2) according to the response information, for the host system 13 to query.

[0049] In one embodiment, the data write status of the target data can be represented by a status identifier. For example, this status identifier can correspond to one of a plurality of write statuses (also referred to as candidate write statuses). Different status identifiers can correspond to different data write statuses. In one embodiment, based on response information obtained from the target hardware device, the hardware controller 12 can update the status identifier corresponding to the target hardware device in the aforementioned write status list in a temporary memory (e.g., temporary memory 20 of FIG2). The updated status identifier can reflect the latest data write status (i.e., data update status) for the target hardware device.

[0050] In one embodiment, the hardware controller 12 can update the data write status of the target hardware device based on the verification result of the write verification performed on the target hardware device. For example, the updated data write status of the target hardware device can reflect the data update result of the target hardware device in at least one update stage (e.g., update success or update failure). In one embodiment, the hardware controller 12 can determine whether to allow the target hardware device to enter the next stage of data update based on the data write status of the target hardware device. Relevant details have been described in detail in the embodiment of FIG4 and will not be repeated here.

[0051] Figure 5 is a schematic diagram of a write status list according to an embodiment of the present invention. Referring to Figure 5, the write status list 51 can be used to record the individual data write status of hardware devices 11(1) to 11(N) for target data.

[0052] Taking hardware device 11(i) as an example, the data writing status of hardware device 11(i) for target data can be represented by a status identification code SN(i). For example, the status identification code SN(i) may include one of "0" (indicating successful writing of target data), "1" (error code #1, indicating that data writing of type #1 failed or was abnormal) and "2" (error code #2, indicating that data writing of type #2 failed or was abnormal). In addition, the type of status identification code SN(i) can be adjusted according to practical needs, and this invention does not impose any limitations.

[0053] In one embodiment, the hardware controller 12 can obtain a query command corresponding to the write status list from the host system 13. Then, based on this query command, the hardware controller 12 can read the write status list from temporary memory (e.g., temporary memory 20 in FIG2) and transmit all (or part) of the contents of the write status list to the host system 13. Subsequently, the host system 13 can obtain the data write status (e.g., whether it was successful or the reason for failure) of at least one hardware device for the target data based on the status identification code (e.g., status identification code SN(i)) corresponding to at least one hardware device recorded in the write status list.

[0054] In one embodiment, the hardware controller 12 can also dynamically detect whether a new hardware device has been added to the hardware devices 11(1) to 11(N) or whether an old hardware device has been removed from the hardware devices 11(1) to 11(N). In response to the addition of a new hardware device to the hardware devices 11(1) to 11(N), the hardware controller 12 can dynamically update the address list and the write status list. For example, the hardware controller 12 can add the address information corresponding to the new hardware device to the address list and add the device number (and status identification code) corresponding to the new hardware device to the write status list.

[0055] In one embodiment, in response to the removal of an old hardware device from hardware devices 11(1) to 11(N), the hardware controller 12 can dynamically update the address list and the write status list. For example, the hardware controller 12 can remove the address information corresponding to the old hardware device from the address list and remove the device number (and status identification code) corresponding to the old hardware device from the write status list.

[0056] In one embodiment, when the address information corresponding to any hardware device changes, the hardware controller 12 can update the address list accordingly to record the new address information in the address list. Thus, regardless of the various changes that occur to the hardware devices 11(1) to 11(N), the hardware controller 12 can still easily complete the subsequent batch data updates for the hardware devices 11(1) to 11(N) without requiring (but allowing) additional management by the host system 13.

[0057] Figure 6 is a flowchart illustrating a data update method according to an embodiment of the present invention. Referring to Figure 6, in step S601, target data and an address list are obtained from the host system and stored in the temporary memory of the hardware controller, wherein the address list contains address information corresponding to multiple hardware devices. In step S602, an update trigger command corresponding to the target data is obtained from the host system. In step S603, target address information is extracted from the address list according to the update trigger command, wherein the target address information corresponds to a target hardware device among the multiple hardware devices. In step S604, a data update command containing the target data is sent to the target hardware device according to the target address information to instruct the target hardware device to write the target data.

[0058] Figure 7 is a flowchart illustrating a data update method according to an embodiment of the present invention. Referring to Figure 7, in step S701, after sending a data update command to the target hardware device, response information is obtained from the target hardware device, wherein the response information reflects the data write status of the target hardware device for the target data. In step S702, based on the response information, the write status list corresponding to the plurality of hardware devices is updated in the temporary memory for query by the host system.

[0059] However, the steps in Figures 6 and 7 have been described in detail above and will not be repeated here. It is worth noting that each step in Figures 6 and 7 can be implemented as multiple pieces of code or circuits, and this invention is not limited thereto. Furthermore, the methods in Figures 6 and 7 can be used in conjunction with the above exemplary embodiments, or they can be used alone, and this invention is not limited thereto.

[0060] In summary, the data update method and hardware control system proposed in this invention allow the host system to pre-store the target data to be updated and the address list corresponding to multiple hardware devices to the hardware controller. Later, the host system can trigger the hardware controller to perform batch data updates based on the target data on multiple hardware devices by sending a small number of update trigger commands. This effectively improves the efficiency of data updates and management for multiple hardware devices.

[0061] In particular, during batch data updates for multiple hardware devices, the target data (or data update command) is sent from the hardware controller to the target hardware device in a point-to-point manner. Therefore, even if any hardware device does not support a broadcast update mechanism, batch data updates for multiple hardware devices can still be completed successfully.

[0062] Furthermore, various optimization operations, such as reusing target data stored in temporary memory, splitting and updating target data to be updated in stages, and / or managing the dynamic status of hardware devices, can further improve the efficiency of data updating and management for multiple hardware devices.

[0063] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0064] 10: Hardware Control System 11(1)~11(N): Hardware device 12: Hardware Controller 101: Controller 102: Communication Interface Circuit 103: Temporary Memory 13: Host System 20: Temporary Memory 21: Target Data 22: Address List 22(1)~22(N): Address field Pr: Reading Indicators ΔS(1), ΔS(2): Address offset values 41, 42: Sub-target data 51: Write to status list SN(i): Status identification code S601~S604, S701, S702: Steps

Claims

1. A hardware controller, comprising: Communication interface circuit; And temporary memory; The controller is coupled to the communication interface circuit and the temporary memory, wherein the controller is configured to: obtain target data and an address list from the host system and store the target data and the address list in the temporary memory, wherein the address list contains address information corresponding to multiple hardware devices and the multiple hardware devices have the same hardware structure; obtain an update trigger command corresponding to the target data from the host system; extract target address information from the address list according to the update trigger command, wherein the target address information corresponds to a target hardware device among the multiple hardware devices; and send a data update command containing the target data to the target hardware device according to the target address information, so as to instruct the target hardware device to write the target data.

2. The hardware controller as described in claim 1, wherein the address list has multiple address fields, each address field being used to record address information corresponding to the multiple hardware devices, and the operation of the controller retrieving the target address information from the address list according to the update trigger command includes: Set a read pointer so that it sequentially points to one of the multiple address fields; And based on the reading index, extract the target address information from the address list.

3. The hardware controller as described in claim 2, wherein the operation of the controller retrieving the target address information from the address list based on the read indicator includes: Based on a first address offset value, first address information is extracted from the first address field among the plurality of address fields, wherein the first address information corresponds to the first hardware device among the plurality of hardware devices; and after extracting the first address information, second address information is extracted from the second address field among the plurality of address fields based on a second address offset value, wherein the second address information corresponds to the second hardware device among the plurality of hardware devices, and the first address offset value is different from the second address offset value.

4. The hardware controller as described in claim 3, wherein the operation of the controller sending a data update command containing the target data to the target hardware device based on the target address information, to instruct the target hardware device to write the target data, includes: Based on the first address information, a first data update command containing the target data is sent to the first hardware device to instruct the first hardware device to write the target data. And after sending the first data update command, based on the second address information, a second data update command containing the target data is sent to the second hardware device to instruct the second hardware device to write the target data.

5. The hardware controller as described in claim 1, wherein the data update command is sent to the target hardware device in a point-to-point manner based on the target address information, rather than being sent synchronously to the multiple hardware devices via broadcast.

6. The hardware controller as described in claim 1, wherein the operation of the controller sending a data update command containing the target data to the target hardware device based on the target address information, to instruct the target hardware device to write the target data, includes: The target data is divided into multiple sub-target data; In the first update phase, based on the target address information, a first-stage data update command containing the first sub-target data from the plurality of sub-target data is sent to the target hardware device to instruct the target hardware device to write the first sub-target data; and after the first update phase, in the second update phase, based on the target address information, a second-stage data update command containing the second sub-target data from the plurality of sub-target data is sent to the target hardware device to instruct the target hardware device to continue writing the second sub-target data.

7. The hardware controller as claimed in claim 6, wherein the controller is further configured to: skip the target hardware device in the second update phase if the target hardware device fails the write verification in the first update phase.

8. The hardware controller as claimed in claim 1, wherein the controller is further configured to: after sending the data update command to the target hardware device, obtain response information from the target hardware device, wherein the response information reflects the data write status of the target hardware device for the target data; and update the write status list corresponding to the plurality of hardware devices in the temporary memory according to the response information for query by the host system.

9. The hardware controller as described in claim 8, wherein the operation of updating the write status list corresponding to the plurality of hardware devices in the temporary memory based on the response information includes: Based on the response information, update the status identification code corresponding to the target hardware device in the write status list, wherein the status identification code corresponds to one of a plurality of candidate write statuses.

10. The hardware controller as claimed in claim 8, wherein the controller is further configured to: obtain a query command corresponding to the write status list from the host system; and transmit the write status list to the host system according to the query command.

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