Power converter circuit

Abstract

A power converter circuit for converting an input voltage into an output voltage includes a switching node; an output terminal; an inductor; a power stage circuit including an upper bridge switch and a lower bridge switch; a control circuit for generating a control signal to control the on and off of the upper bridge switch and the lower bridge switch, and switching the operation of the upper bridge switch and the lower bridge switch in a pulse width modulation mode or a pulse skipping mode according to a zero current condition; and a lower bridge current detection circuit coupled to the switching node and the control circuit for detecting whether the inductor current of the inductor is lower than a preset current level during the conduction period of the lower bridge switch in the pulse width modulation mode, and generating a lower bridge current detection signal to the control circuit accordingly.

Description

Power converter circuit Power Converter Circuit Technical Field

[0001] This invention relates to a power converter circuit, and more particularly to a power converter circuit capable of smooth and reliable switching between pulse width modulation mode and pulse skipping mode. Prior Technology

[0002] Power converter circuits are widely used in various electronic devices to convert input voltage into a stable output voltage. To adapt to different operating conditions, such as load changes, power converter circuits need to switch control modes between heavy and light loads to balance efficiency, stability, and power consumption.

[0003] Generally, under heavy load conditions, the power converter circuit uses pulse width modulation (PWM) mode to switch the upper and lower bridge switches at a fixed frequency, keeping the inductor current in continuous conduction mode (CCM). When the load becomes light, to improve efficiency and reduce static power consumption, the power converter circuit switches to pulse skipping mode (PSM). This mode operates at a variable frequency and only switches to replenish energy when the output voltage drops below its target voltage (insufficient energy). The lighter the load, the longer the switching interval, and the inductor current enters discontinuous conduction mode (DCM).

[0004] To differentiate between heavy and light load operation, the power converter circuit can be set with a minimum peak current (MPC). In PSM mode, MPC limits the energy injection for each pulse to prevent over-compensation; in PWM mode, the average current value corresponding to MPC defines the minimum average current limit for stable operation in that mode. In other words, when the actual load current in PWM mode is lower than this limit, the system should theoretically switch to PSM mode; conversely, it should switch from PSM mode to PWM mode.

[0005] However, voltage noise, transient disturbances, or other non-ideal factors may exist in the system, potentially causing the power converter circuit to abnormally switch to PSM or PWM modes, or even leading to instability caused by frequent switching between PWM and PSM modes. To address this, conventional technology has incorporated a zero-current (ZC) detection mechanism. Specifically, in the existing MPC mechanism architecture, when the inductor current decreases and triggers ZC, the system can confirm that the load is sufficiently light to safely enter PSM mode, thereby ensuring the accuracy of mode transitions and overall operational stability.

[0006] Nevertheless, the ZC detection mechanism may still fail under certain application conditions. For example, when the input-output voltage conversion ratio is too low, or when a large inductor value is used to reduce ripple, the inductor current ripple amplitude is extremely small. Even if the load current is below the minimum average current limit defined by the MPC, the inductor current trough may still fail to drop to zero, thus failing to trigger ZC. In this situation, the system cannot obtain a basis for entering PSM mode and remains in PWM mode, maintaining the minimum average current output defined by the MPC. At this time, the injected energy is far greater than the light load requirement, and the excess energy charges the output capacitor, causing the output voltage to rise continuously, exceeding system requirements, and even leading to overvoltage or affecting the stability of subsequent stages.

[0007] Therefore, how to smoothly and stably switch to PSM mode under light load without causing output voltage runaway remains an urgent issue to be addressed in this field. Summary of the Invention

[0008] Therefore, this invention mainly provides a power converter circuit to improve upon the shortcomings of conventional technology.

[0009] This invention discloses a power converter circuit for converting an input voltage into an output voltage, comprising: a switching node; an output terminal for outputting the output voltage; an inductor coupled between the switching node and the output terminal; a power stage circuit coupled to the input voltage and the switching node, comprising an upper bridge switch and a lower bridge switch; a control circuit coupled to the power stage circuit and the output terminal for generating a control signal to control the on and off of the upper bridge switch and the lower bridge switch, and switching the operation of the upper bridge switch and the lower bridge switch in a pulse width modulation mode or a pulse skipping mode according to a zero current condition; and a lower bridge current detection circuit coupled to the switching node and the control circuit for detecting the current in the pulse width modulation mode. In this formula, during the conduction period of the lower bridge switch, the inductor current of one of the inductors is detected according to a signal of one of the switch nodes to determine whether it is lower than a preset current level, and a lower bridge current detection signal is generated to the control circuit accordingly; wherein, when the lower bridge current detection signal indicates that the inductor current is lower than the preset current level, the control circuit suppresses the conduction of the upper bridge switch in at least one pulse cycle of the pulse width modulation mode, and maintains the conduction state of the lower bridge switch until the inductor current triggers the zero current condition; wherein, when the inductor current triggers the zero current condition, the control circuit adjusts the control signal to switch the upper bridge switch and the lower bridge switch from the pulse width modulation mode to the pulse skipping mode; wherein, the preset current level is higher than zero amperes. Simple Explanation of the Diagram

[0010] Figure 1 is a schematic diagram of a power converter circuit in one embodiment of this invention. Figure 2 is a schematic diagram of the relevant signals of the power converter circuit in Figure 1. Figure 3 is a schematic diagram of a lower bridge current detection circuit in one embodiment of this invention. Figure 4 is a schematic diagram of a lower bridge current detection circuit in one embodiment of this invention. Figure 5 is a schematic diagram of the control flow of one embodiment of this invention. Implementation

[0011] Please refer to Figure 1, which is a schematic diagram of a power converter circuit 10 according to one embodiment of this invention. The power converter circuit 10 converts an input voltage VIN into an output voltage VOUT. It includes an output terminal 102, a switching node NP, an inductor L, a power stage circuit 12, a control circuit 14, a switch driver 16, a zero-current detection circuit 18, and a lower bridge current detection circuit 20. The power stage circuit 12 includes an upper bridge switch UG and a lower bridge switch LG. The upper bridge switch UG is coupled between the input voltage VIN and the switching node NP, and the lower bridge switch LG is coupled between the switching node NP and a ground terminal GND. The inductor L is coupled between the switching node NP and the output terminal 102. The output terminal 102 is coupled with an output capacitor COUT to generate a stable output voltage VOUT. Furthermore, the output terminal 102 is also coupled with feedback resistors R1 and R2. The voltage divider circuit formed by the feedback resistors R1 and R2 divides the output voltage VOUT to output a feedback signal VFB.

[0012] Control circuit 14 is coupled to power stage circuit 12 via switch driver 16. It generates a control signal CTRL and outputs an upper bridge drive signal UG_drv to upper bridge switch UG and a lower bridge drive signal LG_drv to lower bridge switch LG via switch driver 16, controlling the on / off state of upper and lower bridge switches UG and LG. Furthermore, based on a zero-current condition, it controls the power converter circuit 10 to operate in either Pulse Width Modulation (PWM) mode or Pulse Skipping Mode (PSM) mode. In addition, control circuit 14 is coupled to an error amplifier 142 and a comparator 144, and receives a PWM clock signal CLK. Error amplifier 142 compares the feedback signal VFB of output voltage VOUT with a reference voltage Vref in PWM mode to generate an error signal EA for control circuit 14, allowing control circuit 14 to adjust the pulse width accordingly. Comparator 144 is used to compare the feedback signal VFB with the reference voltage Vref in PSM mode to generate a comparison result signal COMP, which is used by control circuit 14 to determine whether to switch to replenish energy.

[0013] Zero-current detection circuit 18 is coupled to switching node NP and control circuit 14 to detect whether the inductor current IL drops to zero current and generates a zero-current condition signal ZC_st to control circuit 14. Control circuit 14 can then determine whether a zero-current condition has occurred and control the power converter circuit 10 to operate in PWM mode or PSM mode accordingly. Specifically, in the operation of power converter circuit 10, PWM mode is suitable for heavy-load conditions. It periodically switches the upper and lower bridge switches UG and LG on and off at a fixed frequency (determined by the PWM clock signal CLK) to keep the inductor current IL continuously conducting. The pulse width is precisely adjusted by error amplifier 142 to stabilize the output voltage VOUT. When the load becomes light, the system needs to switch to PSM mode to reduce power consumption. At this time, the operating frequency becomes variable. Only when the output voltage VOUT drops below its target voltage (e.g., the feedback signal VFB is lower than the reference voltage Vref) (i.e., only when the energy is insufficient) will the comparator 144 trigger a single pulse to replenish energy. The lighter the load, the longer the switching interval, and the inductor current IL enters discontinuous conduction mode.

[0014] To ensure a safe switch from PWM mode to PSM mode, the zero-current detection circuit 18 monitors the voltage change of the switching node NP. It indirectly determines whether the inductor current IL crosses zero by using the on-resistance of the lower bridge switch LG or the body diode voltage drop, and outputs a zero-current condition signal ZC_st as the basis for switching. This avoids the abnormal entry into PSM due to voltage noise or transient disturbances misjudging the light load state under heavy or medium load conditions, thereby preventing the unstable phenomenon of frequent back-and-forth switching between PWM and PSM.

[0015] However, under certain application conditions, such as when the conversion ratio between the input voltage VIN and the output voltage VOUT is too low, or when a larger inductance value is used to reduce ripple, the ripple amplitude of the inductor current IL is extremely small. This may result in the actual load current being lower than the minimum average current limit corresponding to the minimum peak current (MPC), but the trough of the inductor current IL during the conduction of the lower bridge switch LG is still difficult to drop to zero, causing the zero current condition signal ZC_st to be unable to be triggered.

[0016] To address the aforementioned issues, this embodiment introduces a separate lower-bridge current detection circuit 20. The lower-bridge current detection circuit 20 is coupled to the switching node NP and the control circuit 14. In PWM mode, during the conduction of the lower-bridge switch LG, it detects whether the inductor current IL is lower than a preset current level Iref based on a signal S1 from the switching node NP, and generates a lower-bridge current detection signal LGCD to the control circuit 14 accordingly. The signal S1 is typically a voltage signal or a signal related to the inductor current IL; the preset current level Iref is higher than zero amperes and is set to be sufficient to detect the light-load precursor (less than the minimum average current limit corresponding to MPC) before entering PSM mode. Since the preset current level Iref is higher than zero amperes, it provides an early warning threshold higher than that of pure zero current. This allows the control circuit 14 to intervene when the inductor current IL has not completely dropped to zero but has already significantly deviated from the heavy-load continuous conduction state. This avoids the situation where the zero-current condition signal ZC_st fails to trigger for a long time, resulting in continuous power supply with the minimum average current of MPC, causing excess energy and an increase in the output voltage VOUT. During the conduction of the lower bridge switch LG, the inductor current IL is the current from ground GND and passes through the lower bridge switch LG, the switching node NP, and the inductor L. Therefore, the inductor current IL during the conduction of the lower bridge switch LG is equal to the lower bridge current.

[0017] Specifically, when the inductor current IL indicated by the downbridge current detection signal LGCD is lower than the preset current level Iref, the control circuit 14, in PWM mode, suppresses the conduction of the upbridge switch UG for at least one subsequent pulse cycle (i.e., the upbridge drive signal UG_drv remains at a low level) and maintains the conduction state of the downbridge switch LG (i.e., the downbridge drive signal LG_drv remains at a high level) until the inductor current IL triggers the zero-current condition signal ZC_st, thereby switching the power converter circuit 10 from PWM mode to PSM mode. In short, the downbridge current detection circuit 20 can detect the imminent entry into PSM mode in PWM mode to assist the zero-current detection circuit 18 in correctly detecting the occurrence of zero current. In this way, the power converter circuit 10 of this embodiment can effectively overcome the failure problem of conventional zero-current detection under small ripple conditions, not only ensuring a smooth switch to PSM mode under light load to achieve power saving, but also preventing the output voltage VOUT from continuously rising due to excess energy, maintaining high stability and accuracy.

[0018] Please refer to Figure 2, which is a schematic diagram of the relevant signals of the power converter circuit 10. From top to bottom, curves 200 to 214 are shown, where curve 200 represents the inductor current IL, curve 202 represents the load current (i.e., the current output from output terminal 102), curve 204 represents the output voltage VOUT, curve 206 represents the PWM clock signal CLK, curve 208 represents the lower bridge current detection signal LGCD, curve 210 represents the zero current condition signal ZC_st, curve 212 represents the upper bridge drive signal UG_drv, and curve 214 represents the lower bridge drive signal LG_drv.

[0019] Figure 2 clearly shows the operational details of the power converter circuit 10 during the switching process between PWM and PSM modes. In PWM mode, the PWM clock signal CLK (curve 206) generates pulses at a fixed frequency, causing the upper bridge drive signal UG_drv (curve 212) and the lower bridge drive signal LG_drv (curve 214) to conduct alternately in sequence, keeping the inductor current IL (curve 200) continuously conducting and exhibiting obvious triangular ripple. At this time, both the load current (curve 202) and the output voltage VOUT (curve 204) are within a stable range. The power converter circuit 10 adjusts the pulse width through the error amplifier 142 to maintain a constant VOUT.

[0020] As the load gradually decreases, the load current (curve 202) drops, and the average value and ripple amplitude of the inductor current IL also decrease. However, in PWM mode, the minimum average value of the inductor current IL will still be greater than or equal to MPC. When the trough of the inductor current IL during the conduction of the lower bridge switch LG approaches or falls below the preset current level Iref, the lower bridge current detection circuit 20 detects this state and generates a high-level lower bridge current detection signal LGCD (curve 208) at time t1. At this time, the lower bridge current detection signal LGCD is latched. After receiving the high-level lower bridge current detection signal LGCD, the control circuit 14 forcibly suppresses the upper bridge drive signal UG_drv in the next PWM clock cycle (curve 212 maintains a low level and does not generate a conduction pulse), while maintaining the lower bridge drive signal LG_drv (curve 214 maintains a high level), allowing the inductor current IL to continue discharging through the lower bridge switch LG, and the trough of the inductor current IL further decreases.

[0021] Because the upper bridge switch UG is forcibly turned off, the inductor current IL has sufficient time to continue decreasing until it crosses the zero current point. Therefore, at time t2, the zero current detection circuit 18 detects that the inductor current IL has reached the zero current condition and generates a high-level zero current condition signal ZC_st (curve 210). Once the zero current condition signal ZC_st is triggered, the control circuit 14 confirms that it has entered a light-load discontinuous conduction state, and thus switches the power converter circuit 10 to PSM mode. Thereafter, the upper bridge drive signal UG_drv and the lower bridge drive signal LG_drv are no longer fixedly driven by the PWM clock signal CLK, but are only triggered by the comparator 144 to replenish energy when the output voltage VOUT drops below its target voltage (insufficient energy), thereby significantly reducing switching losses and static power consumption.

[0022] It is worth noting that during the switching process, the output voltage VOUT (curve 204) remained stable without a significant rise. This contrasts with conventional technologies that continuously supply power via MPC when zero-current detection fails, leading to overshoot. Therefore, this invention effectively assists the inductor current IL to quickly drop to zero by pre-intervention of the lower bridge current detection signal LGCD and the upper bridge conduction suppression mechanism. This ensures that the zero-current condition signal ZC_st can be effectively triggered, allowing the system to smoothly and stably enter PSM mode, balancing light-load efficiency and output voltage accuracy.

[0023] It should be noted that the power converter circuit 10 shown in Figure 1 is a preferred embodiment of this invention, and its internal circuit architecture can be reasonably changed and adjusted according to actual application requirements. For example, please refer to Figure 3, which is a schematic diagram of a lower bridge current detection circuit 30 of one embodiment of this invention. The lower bridge current detection circuit 30 is a specific implementation of the lower bridge current detection circuit 20 in Figure 1, which includes a switching circuit 300, a voltage-to-current converter 302, a current mirror 304, and a comparator 306. The switching circuit 300 is coupled to the switching node NP and the lower bridge switch LG, and is used to output the signal S1 of the switching node NP during the conduction of the lower bridge switch LG. The voltage-to-current converter 302 is coupled to the switching circuit 300 and is used to generate a sense current Isen according to the signal S1. The current mirror 304 is used to replicate or mirror the sense current Isen to generate a mirrored current Imir. Comparator 306 is used to compare the mirrored current Imir with the preset current level Iref, and generate the lower bridge current detection signal LGCD accordingly.

[0024] In the embodiment shown in Figure 3, when the power converter circuit 10 operates in PWM mode and the lower bridge switch LG is turned on according to the lower bridge drive signal LG_drv, the switching circuit 300 is synchronously turned on according to the lower bridge drive signal LG_drv, and generates a signal S300 to the voltage-to-current converter 302 according to the signal S1 of the switching node NP (usually a voltage signal or a signal related to the inductor current IL). In this embodiment, the signal S300 is associated with the signal S1 of the switching node NP. For example, when the lower bridge switch LG is turned on, the voltage level of the signal S300 is higher than the voltage level of the signal S1, and the magnitude of the difference is related to the equivalent resistance when the switching circuit 300 is turned on. The voltage-to-current converter 302 generates a sense current Isen according to the signal S300, the magnitude of which is proportional to the instantaneous value of the current inductor current IL during the lower bridge conduction period (i.e., the instantaneous value of the lower bridge current). The current mirror 304 receives the sensed current Isen and copies it to the mirrored current Imir, then sends it to the comparator 306. When the mirrored current Imir is lower than the preset current level Iref, the comparator 306 outputs a high-level lower bridge current detection signal LGCD to notify the control circuit 14 that a light load precursor has been detected.

[0025] Therefore, the lower bridge current detection circuit 30 can ensure through the switching circuit 300 that the detection action only occurs during the conduction of the lower bridge switch LG, avoiding misjudgments during the conduction of the upper bridge or the dead time. At the same time, the combination of the voltage-to-current converter 302 and the current mirror 304 can provide high linearity and low offset current sensing capability, making the setting of the preset current level Iref more accurate and reliable. When the lower bridge current detection signal LGCD is triggered, the control circuit 14 can suppress the upper bridge drive signal UG_drv, causing the inductor current IL to continue to decrease until the zero current condition signal ZC_st is triggered, thereby successfully switching to PSM mode.

[0026] Please refer to Figure 4, which is a schematic diagram of the lower-bridge current detection circuit 40 in one embodiment of this invention. The lower-bridge current detection circuit 40 is another implementation of the lower-bridge current detection circuit 20, and is also derived from the lower-bridge current detection circuit 30 in Figure 3. The lower-bridge current detection circuit 40 employs a three-terminal voltage lockout technique and includes transistors M1, M2, M3, and M4, an operational amplifier 400, and a comparator 402. Transistor M1 functions as a switching circuit, corresponding to the switching circuit 300 in Figure 3, and is used to generate a signal S300 to subsequent circuits based on the signal S1 of the switching node NP when the lower-bridge switch LG is turned on. Transistor M2 and operational amplifier 400 together constitute a voltage-to-current converter, used to lock the voltage level of signal S300 to the ground voltage at ground terminal GND, and generate a sensing current Isen based on signal S300. Transistors M3 and M4 constitute a current mirror, used to replicate or mirror the sensing current Isen to generate a mirrored current Imir. Comparator 402 is used to compare the mirrored current Imir with the preset current level Iref, and generate the lower bridge current detection signal LGCD accordingly.

[0027] In the embodiment shown in Figure 4, as described above, the operational amplifier 400 and transistor M2 form a negative feedback loop, locking the source terminal of transistor M1 to the ground voltage of ground GND. Referring to Figures 1 and 4, the voltages at the three terminals (gate, drain, and source) of transistor M1 are the same as the corresponding voltages at the three terminals of power switch M2. Through the connection architecture of transistors M1, M2, and M3 with the operational amplifier 400, during the conduction of the lower bridge switch LG, the current flowing sequentially through transistors M3, M2, and M1 is the sensing current Isen on the input side of the current mirror. Its direction is the same as the direction of the lower bridge current, and based on the size ratio between the lower bridge switch LG and transistor M1, the magnitude of the sensing current Isen is proportional to the lower bridge current (i.e., proportional to the inductor current IL), thus realizing the detection of the lower bridge current. In this embodiment, the voltage level of signal S300 is higher than the voltage level of signal S1. In detail, the voltage level of signal S1 is related to the voltage level of signal S300 (the ground voltage locked to ground GND, e.g., 0 volts), the sensing current Isen, and the on-resistance (RM1) of transistor M1. Depending on the direction of the sensing current Isen, the voltage level of signal S1 is equal to the voltage level of signal S300 (0 volts) minus the product of the sensing current Isen and the on-resistance (RM1) of transistor M1 (simply expressed as: S1 = 0 - Isen * RM1).

[0028] In addition, the voltage lockout circuit formed by the operational amplifier 400 and the transistor M2 constitutes a three-terminal voltage lockout architecture, which can further reduce the detection error caused by on-resistance variation or temperature effect. Other operating modes can be referred to the above description and will not be repeated here.

[0029] The operation of the power converter circuit 10 described above can be summarized as a control flow 50, as shown in Figure 5. The control flow 50 includes the following steps:

[0030] Step 500: Begin.

[0031] Step 502: Generate a control signal CTRL to control the on and off of the upper bridge switch UG and the lower bridge switch LG, and switch the upper bridge switch UG and the lower bridge switch LG to operate in PWM mode or PSM mode according to the zero current condition.

[0032] Step 504: In PWM mode, and during the conduction period of the lower bridge switch LG, based on the signal S1 of the switch node NP, detect whether the inductor current IL is lower than the preset current level Iref, and generate the lower bridge current detection signal LGCD accordingly;

[0033] Step 506: When the underbridge current detection signal LGCD indicates that the inductor current IL is lower than the preset current level Iref, suppress the conduction of the upper bridge switch UG for at least one pulse cycle in PWM mode, and maintain the conduction state of the lower bridge switch LG until the inductor current IL triggers the zero current condition.

[0034] Step 508: When the inductor current IL triggers the zero current condition, adjust the control signal CTRL to switch the upper bridge switch UG and the lower bridge switch LG from PWM mode to PSM mode.

[0035] Step 510: End.

[0036] For a detailed description of the control process 50 and its derivative variations, please refer to the aforementioned implementation method, which will not be repeated here.

[0037] In conventional technologies, the system relies on zero-current detection (ZC) as the primary condition for switching from PWM mode to PSM mode. However, when the input-output conversion ratio is too low or the inductance value is too large, resulting in minimal ripple, the inductor current is difficult to drop to zero, the zero-current condition cannot be triggered, and the system remains stuck in PWM mode. This leads to excess energy, which is then charged into the output capacitor, causing the output voltage VOUT to rise continuously, potentially triggering overvoltage protection or affecting the stability of subsequent circuits. In contrast, this invention uses an independent lower-bridge current detection circuit to pre-detect when the inductor current IL is lower than the preset current level Iref in PWM mode, and forcibly suppresses the upper-bridge conduction to assist the current in rapidly dropping to zero. This effectively solves the problem of failure to switch to PSM mode in time due to zero-current detection failure, ensuring smooth entry into power-saving mode under light load and maintaining high stability and accuracy of the output voltage VOUT.

[0038] In summary, this invention provides a power converter circuit that combines high efficiency and high stability, which can smoothly and stably switch to PSM mode under light load without causing output voltage runaway.

[0039] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of this invention. Those skilled in the art should recognize that this invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of this invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

[0040] 10: Power converter circuit 12: Power stage circuit 14: Control Circuit 16: Switch driver 18: Zero Current Detection Circuit 20: Lower bridge current detection circuit 102: Output terminal 142: Error Amplifier 144: Comparator NP: Switch node L: Inductance COUT: Output capacitor UG: Upper Bridge Switch LG: Downbridge switch UG_drv: Upper bridge drive signal LG_drv: Downbridge driver signal CTRL: Control Signal CLK: PWM clock signal VFB: Feedback Signal Vref: Reference voltage EA: Error Signal COMP: Comparison result signal IL: Inductor current Iref: Preset current level S1, S300: Signals Isen: Sensing Current Imir: Mirror current LGCD: Downbridge Current Detection Signal ZC_st: Zero-current condition signal R1, R2: Feedback resistors t1, t2: time points M1~M4: Transistors 30: Lower bridge current detection circuit 40: Lower bridge current detection circuit 300: Switching circuit 302: Voltage to Current Converter 304: Current Mirror 306: Comparator 400: Operational Amplifier 402: Comparator 50: Control Flow 500~510: Steps

Claims

1. A power converter circuit for converting an input voltage into an output voltage, comprising: a switching node; an output terminal for outputting the output voltage; an inductor coupled between the switching node and the output terminal; a power stage circuit coupled to the input voltage and the switching node, including an upper bridge switch and a lower bridge switch; a control circuit coupled to the power stage circuit and the output terminal for generating a control signal to control the on and off of the upper bridge switch and the lower bridge switch, and switching the operation of the upper bridge switch and the lower bridge switch in a pulse width modulation mode or a pulse skipping mode according to a zero current condition; and a lower bridge current detection circuit coupled to the switching node and the control circuit for detecting, in the pulse width modulation mode and during the on-state of the lower bridge switch, whether the inductor current of the inductor is lower than a preset current level according to a signal from the switching node, and thereby generating a lower bridge current detection signal to the control circuit; wherein... When the lower bridge current detection signal indicates that the inductor current is lower than the preset current level, the control circuit suppresses the conduction of the upper bridge switch for at least one pulse cycle in the pulse width modulation mode and maintains the conduction state of the lower bridge switch until the inductor current triggers the zero current condition; wherein, when the inductor current triggers the zero current condition, the control circuit adjusts the control signal to switch the upper bridge switch and the lower bridge switch from the pulse width modulation mode to the pulse skipping mode; and wherein, the preset current level is higher than zero amperes.

2. The power converter circuit as described in claim 1, wherein the signal of the switching node is a voltage signal or a current-related signal.

3. The power converter circuit as claimed in claim 1, wherein the lower bridge current detection circuit comprises: a switching circuit coupled to the switching node and the lower bridge switch, for outputting the signal of the switching node when the lower bridge switch is turned on; a voltage-to-current converter coupled to the switching circuit, for generating a sense current based on the signal of the switching node when the lower bridge switch is turned on; a current mirror for replicating or mirroring the sense current to generate a mirrored current; and a comparator for comparing the mirrored current with the preset current level and generating the lower bridge current detection signal accordingly.

4. The power converter circuit as described in claim 1 further includes a zero current detection circuit coupled to the control circuit and the switching node, for detecting the inductor current based on the signal from the switching node, and notifying the control circuit that the inductor current triggers the zero current condition when the inductor current reaches zero current.

5. The power converter circuit as claimed in claim 1, wherein in the pulse width modulation mode, the control signal generated by the control circuit periodically drives the upper bridge switch and the lower bridge switch to switch according to a fixed frequency clock; and in the pulse skipping mode, the control signal generated by the control circuit drives the upper bridge switch and the lower bridge switch to switch only when insufficient energy of the inductor is detected.

6. The power converter circuit as claimed in claim 5, wherein the control circuit further includes an error amplifier for generating an error signal based on the output voltage and a reference voltage in the pulse width modulation mode, so as to control the pulse width of the control signal.

7. The power converter circuit as claimed in claim 5, wherein the control circuit further includes a comparator for determining, in the pulse-skipping mode, whether to drive the upper bridge switch and the lower bridge switch to switch based on the output voltage and a reference voltage.

8. The power converter circuit as claimed in claim 1, wherein the preset current level is less than a minimum peak current, the minimum peak current being the lowest average value that the inductor current can reach in the pulse width modulation mode and the instantaneous highest value that the inductor current can reach in the pulse skipping mode.

9. The power converter circuit as claimed in claim 8, wherein in the pulse skipping mode, the average value of the inductor current is less than the minimum peak current.

10. The power converter circuit as claimed in claim 1, wherein the control circuit is further configured to drive the lower bridge current detection circuit in the pulse width modulation mode, and to turn off the lower bridge current detection circuit after switching from the pulse width modulation mode to the pulse skipping mode.

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