substrate-free double-sided semiconductor packaging structure

Abstract

A substrate-free double-sided semiconductor package structure includes a first circuit layer, a first encapsulation layer, at least one first electronic component, a second circuit layer, a second encapsulation layer, and at least one second electronic component. The first circuit layer includes a signal region and a heat dissipation region different from the signal region. The first encapsulation layer is disposed on the first circuit layer. The at least one first electronic component is disposed above the first circuit layer and within the first encapsulation layer. The heat dissipation region assists in heat dissipation for the at least one first electronic component. The second circuit layer is directly disposed on the first encapsulation layer. The second encapsulation layer is disposed on the second circuit layer. The at least one second electronic component is disposed on the second circuit layer and within the second encapsulation layer. This novel structure has the advantages of short trace distance, small thickness, high pin count, and excellent heat dissipation.

Claims

1. A substrate-free double-sided semiconductor package structure, comprising: a first circuit layer including a signal region and a heat dissipation region different from the signal region; a first package layer disposed on the first circuit layer in a vertical direction; at least one first electronic component disposed above the first circuit layer and within the first package layer in the vertical direction, the at least one first electronic component being positioned corresponding to the heat dissipation region, the heat dissipation region being used to assist the at least one first electronic component in dissipating heat; a second circuit layer directly disposed on the first package layer; a second package layer disposed on the second circuit layer in the vertical direction; and at least one second electronic component disposed on the second circuit layer and within the second package layer in the vertical direction.

2. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The first encapsulation layer includes a plurality of spaced-apart conductive pillars, and the signal region has a plurality of first electrical connection portions disposed below and electrically connected to the conductive pillars.

3. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, It also includes a plurality of contacts disposed below the first line layer, the signal area having a plurality of first electrical connection portions respectively electrically connected to the contacts, the heat dissipation area having at least one metal heat dissipation portion, and the total surface area of ​​any of the first electrical connection portions being less than the total surface area of ​​the metal heat dissipation portion.

4. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The heat dissipation area has a plurality of metal heat dissipation parts, each of which is copper-faced.

5. The substrate-free double-sided semiconductor package structure as described in claim 1, comprising a plurality of first electronic components.

6. The substrate-free double-sided semiconductor package structure as described in claim 1, comprising a plurality of second electronic components.

7. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The first electronic component has a plurality of through holes extending through the top and bottom sides, and a plurality of conductive portions respectively disposed in the through holes for signal connection between the first circuit layer and the second circuit layer.

8. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The second encapsulation layer has a heat sink located on the outside for heat dissipation.

9. The substrate-free double-sided semiconductor packaging structure as described in claim 8, wherein, The heat sink has a base wall disposed on the second electronic component, and a surrounding wall that surrounds the base wall, encloses the second electronic component, and is tightly fitted to the second circuit layer.

10. The substrate-free double-sided semiconductor packaging structure as described in claim 8, wherein, The heat sink is bonded to the second electronic component with a thermal interface material.

11. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The first electronic component has a chip and a plurality of first bonding wires connecting the chip and the second circuit layer.

12. The substrate-free double-sided semiconductor package structure as described in claim 11, wherein, The first packaging layer includes a plurality of spaced-apart conductive pillars, and the second circuit layer has a plurality of second electrical connection portions respectively electrically connected to the conductive pillars. Each of the second electrical connection portions has a pad formed in the region adjacent to the wafer for connection to a corresponding first bonding wire.

13. The substrate-free double-sided semiconductor packaging structure as described in claim 1, wherein, The second electronic component has a die and a filler material between the die and the second circuit layer.

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