Package structure

Abstract

The package structure includes a circuit layer, a memory element layer, a logic element layer, and a plurality of silicon through-holes (SiHV). The memory element layer is disposed on the circuit layer and includes a plurality of memory elements, wherein the plurality of memory elements have different access speeds. The logic element layer is disposed on the memory element layer and includes a plurality of logic elements. The plurality of SiHV penetrates the memory element layer and electrically connects the plurality of logic elements and the circuit layer.

Claims

1. A packaging structure, comprising: Circuit layer; A memory element layer is disposed on the circuit layer and includes a plurality of memory elements, wherein the plurality of memory elements have different access speeds; A logic element layer is disposed on the memory element layer and includes a plurality of logic elements; and a plurality of silicon vias penetrate the memory element layer and electrically connect the plurality of logic elements and the circuit layer.

2. The packaging structure as described in claim 1, wherein each of the plurality of logic elements has a metal contact, wherein the metal contacts are electrically connected to the plurality of memory elements or the plurality of silicon through-holes.

3. The packaging structure as described in claim 1, wherein one of the plurality of logic elements further includes a cooperative operation scheduler that transmits electrical signals to the plurality of memory elements.

4. The packaging structure as described in claim 3, wherein the cooperative operation scheduler transmits the electrical signal according to the access speed of each of the plurality of memory elements.

5. The packaging structure as described in claim 1, wherein the plurality of memory elements are arranged adjacently.

6. The packaging structure as described in claim 5, wherein the plurality of memory elements are stacked in a horizontal or vertical orientation.

7. The packaging structure as described in claim 1, wherein the memory element with faster access speed among the plurality of memory elements is configured closer to the logic element layer.

8. The packaging structure as described in claim 7, wherein the memory elements with slower access speeds among the plurality of memory elements are positioned further away from the logic element layer.

9. The packaging structure as described in claim 1 further includes a plurality of electrical connectors disposed below the circuit layer and electrically connected to the circuit layer.

10. The packaging structure as described in claim 9 further includes a substrate disposed below the plurality of electrical connectors.

11. The packaging structure as described in claim 1 further includes a packaging material layer that encapsulates the memory element layer, the logic element layer, and the circuit layer.

12. The packaging structure as described in claim 9 further includes a packaging material layer that encapsulates the memory element layer, the logic element layer, the circuit layer, and the plurality of electrical connectors.

13. The package structure as described in claim 1 further includes a redistribution layer disposed between the logic element layer and the memory element layer, electrically connecting the plurality of logic elements, the plurality of memory elements and the plurality of silicon vias.

14. The packaging structure as described in claim 13 further includes a packaging material layer that encapsulates the memory element layer, the logic element layer, the circuit layer, and the redistribution layer.

15. The packaging structure as described in claim 1, wherein the plurality of logic elements includes a central processing unit (CPU), a graphics processing unit (GPU), a tensor processor (TPU), a neural network processor (NPU), or a combination thereof.

16. The packaging structure as described in claim 15, wherein the plurality of logic elements comprises a plurality of wafers.

17. The package structure as described in claim 1, wherein the plurality of memory elements includes dynamic random access memory (DRAM), high bandwidth memory (HBM), static random access memory (SRAM), flash memory, or a combination thereof.

18. The packaging structure as described in claim 17, wherein one of the plurality of memory elements is a memory element including in-memory processing (PIM) and is configured to be adjacent to another memory element among the plurality of memory elements.

19. The packaging structure as described in claim 1, wherein one of the plurality of logic elements is electrically connected to one of the plurality of memory elements by a hybrid bonding.

20. The package structure as claimed in claim 1, wherein one of the plurality of logic elements and one of the plurality of memory elements are electrically connected via one of the plurality of silicon through-holes.

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