Power management system
Patent Information
- Application Number
- TW115205006
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2026-06-02
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2036-06-01
Smart Images
Figure TWG2TB001909512_001 
Figure TWG2TB001909512_002 
Figure TWG2TB001909512_003
Abstract
Claims
1. A power management system, comprising: A power supply device configured to supply a power voltage; A display card; And a connector, including a first pin and a second pin, configured to detachably connect the power supply device and the graphics card through the first pin and the second pin, wherein the power supply device determines whether the graphics card supports an overvoltage performance mode based on the state of the second pin, and sends an acknowledgment signal to the graphics card through the first pin accordingly, and the graphics card decides whether to step down the received power supply voltage based on the acknowledgment signal.
2. The power management system as claimed in claim 1, wherein the first pin includes a first power terminal for electrically connecting to the power supply device and a first graphics card terminal for electrically connecting to the graphics card, the second pin includes a second power terminal for electrically connecting to the power supply device and a second graphics card terminal for electrically connecting to the graphics card, the first power terminal and the first graphics card terminal are electrically connected to each other, and the second power terminal and the second graphics card terminal are electrically connected to each other.
3. The power management system as claimed in claim 1, wherein the power supply device comprises: A conversion circuit; A first logic circuit is configured to provide a notification signal having a second logic level when the second pin is maintained at a first logic level; A control circuit electrically connected to the conversion circuit and the first logic circuit is configured to determine that the display card supports the overvoltage performance mode in response to the notification signal at the second logic level, thereby controlling the conversion circuit to generate an overvoltage voltage as the power supply voltage supplied by the power supply device.
4. The power management system as claimed in claim 3, wherein when the second pin is not maintained at the first logic level, the control circuit reacts to the notification signal provided by the first logic circuit having the first logic level and determines that the graphics card does not support the overvoltage performance mode, thereby controlling the conversion circuit to generate a standard voltage as the power supply voltage supplied by the power supply device.
5. The power management system as claimed in claim 3, wherein after the overvoltage is generated, the control circuit provides an indication signal having the second logic level to the first logic circuit, so that the first logic circuit outputs the acknowledgment signal having the first logic level to the first pin.
6. The power management system as claimed in claim 3, wherein the first logic circuit includes: A first resistor, the first end of which is electrically connected to the second pin; a second resistor, the first end of which receives a first standby voltage, and the second end of which is electrically connected to the second end of the first resistor; a first capacitor, the first end of which is electrically connected to the second end of the first resistor, and the second end of which is electrically connected to a ground terminal; a first transistor, the first end of which is electrically connected to the ground terminal, and the control terminal of which is electrically connected to the second end of the first resistor; a third resistor, the first end of which receives the first standby voltage, and the second end of which is electrically connected to the second end of the first transistor to provide the notification signal to the control circuit; a second transistor, the first end of which is electrically connected to the ground terminal, and the control terminal of which is electrically connected to the second end of the third resistor; a third transistor, the first end of which is electrically connected to the second end of the second transistor, and the second end of which is electrically connected to the first pin to output the confirmation signal; and a fourth resistor, the first end of which receives the first standby voltage, and the second end of which is electrically connected to the control terminal of the third transistor to receive an indication signal from the control circuit.
7. The power management system as claimed in claim 3, wherein the first logic circuit is composed of a microcontroller.
8. The power management system as claimed in claim 1, wherein the graphics card includes: A step-down circuit is electrically connected between an input node and an output node; A second logic circuit configured to provide a switch signal having a second logic level when the acknowledgment signal having a first logic level is received; a bypass switch connected in parallel with the buck circuit between the input node and the output node, configured to open in response to the switch signal having the second logic level, so that the buck circuit steps down the power supply voltage input from the input node.
9. The power management system of claim 8, wherein when no acknowledgment signal having the first logic level is received, the second logic circuit provides the switch signal having the first logic level, and the bypass switch is turned on in response to the switch signal having the first logic level, so that the power supply voltage input from the input node bypasses the buck circuit and is provided to the output node.
10. The power management system as claimed in claim 8, wherein the second logic circuitry includes: A fifth resistor, the first end of which is electrically connected to the first pin to receive the confirmation signal; A sixth resistor, the first end of which receives a second standby voltage, and the second end of which is electrically connected to the second end of the fifth resistor; a second capacitor, the first end of which is electrically connected to the second end of the fifth resistor, and the second end of which is electrically connected to a ground terminal; a fourth transistor, the first end of which is electrically connected to the ground terminal, and the control terminal of which is electrically connected to the second end of the fifth resistor; a seventh resistor, the first end of which is electrically connected to the second end of the fourth transistor; and an eighth resistor, the first end of which is electrically connected to the input node, and the second end of which is electrically connected to the second end of the seventh resistor to provide the switching signal to the bypass switch.
11. The power management system as claimed in claim 10, wherein the second logic circuit further comprises: A fifth transistor, the first terminal of which is electrically connected to the ground terminal, and the control terminal of which is electrically connected to the second terminal of the fifth resistor; And a ninth resistor, the first end of which receives the second standby voltage, and the second end of which is electrically connected to the second end of the fifth transistor to provide a consistent power signal to the buck circuit.
12. The power management system as claimed in claim 10, wherein the bypass switch comprises: A transistor array in parallel has its first terminal electrically connected to the input node, its second terminal electrically connected to the output node, and its control terminal electrically connected to the second terminal of the seventh resistor.
13. The power management system as claimed in claim 8, wherein the second logic circuit is composed of a microcontroller.