Electronic package assembly

TWM687741UActive Publication Date: 2026-09-21ADVANCED SEMICON ENG INC
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Patent Information

Application Number
TW115203744
Authority / Receiving Office
TW · TW
Patent Type
Utility models
Current Assignee / Owner
Filing Date
2026-04-28
Publication Date
2026-09-21
Estimated Expiration
2036-04-27

Smart Images

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    Figure TWG2TB001912755_003
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Abstract

An electronic packaging assembly includes a reinforcement layer, a circuit structure, a balancing layer, a wafer, and a molding layer. The circuit structure is disposed on the reinforcement layer. The balancing layer is disposed on the circuit structure and includes a first conductive pillar. The circuit structure is located between the balancing layer and the reinforcement layer. The wafer is disposed on the balancing layer and electrically connected to the first conductive pillar. The molding layer is disposed on the balancing layer and covers the wafer. The molding layer has a cavity. The cavity exposes portions of the balancing layer.
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Claims

1. An electronic packaging component, comprising: a reinforcing layer; a circuit structure disposed on the reinforcing layer; a balancing layer disposed on the circuit structure and including a first conductive pillar, wherein the circuit structure is located between the balancing layer and the reinforcing layer; a wafer disposed on the balancing layer and electrically connected to the first conductive pillar; and a molding layer disposed on the balancing layer and covering the wafer, wherein the molding layer has a cavity and the cavity exposes a portion of the balancing layer.

2. The electronic packaging assembly as claimed in claim 1, wherein the balancing layer further includes a second conductive post spaced apart from the first conductive post, and the first height of the first conductive post is the same as the second height of the second conductive post.

3. The electronic packaging assembly as claimed in claim 2, wherein the molding layer includes a first region and a second region, the first conductive post is located in the first region, the second conductive post is located in the second region, and the coverage area of ​​the first conductive post in a unit area of ​​the first region is smaller than the coverage area of ​​the second conductive post in the unit area of ​​the second region.

4. The electronic packaging assembly as claimed in claim 3, wherein the molding layer further includes a transition region located between the first region and the second region, and the balancing layer further includes a third conductive post located in the transition region, wherein a coverage area of ​​the third conductive post in the unit area of ​​the transition region is located between the coverage area of ​​the first conductive post in the unit area of ​​the first region and the coverage area of ​​the second conductive post in the unit area of ​​the second region.

5. The electronic packaging assembly as claimed in claim 4, wherein two adjacent first conductive posts have a first spacing in the first region, two adjacent second conductive posts have a second spacing in the second region, and two adjacent third conductive posts have a third spacing, a fourth spacing, and a fifth spacing in the transition region located between the second spacing and the first spacing, wherein the third conductive post with the fourth spacing is located between the third conductive post with the third spacing and the third conductive post with the fifth spacing, the third conductive post with the third spacing is adjacent to the first region, and the third conductive post with the fifth spacing is adjacent to the second region.

6. The electronic packaging assembly as claimed in claim 2, wherein the molding layer includes a first region and a second region, the first conductive post located in the first region and the second conductive post located in the second region respectively having a first diameter and a second diameter, wherein the first height is between 1 and 5 times the first diameter, and the second height is between 1 and 5 times the second diameter.

7. The electronic packaging assembly as claimed in claim 6, wherein the molding layer further includes a transition region located between the first region and the second region, and the balancing layer further includes a third conductive post located in the transition region, wherein adjacent third conductive posts have a spacing in the transition region, and the spacing is between 0.5 times and 5 times the first diameter or the second diameter.

8. The electronic packaging assembly as claimed in claim 7, wherein the spacing of the third conductive post gradually increases along one of the directions from the first region to the second region.

9. The electronic packaging assembly as claimed in claim 2, wherein the second conductive post protrudes from one of the upper surfaces of the balancing layer.

10. The electronic packaging assembly as claimed in claim 1, wherein the circuit structure further includes a dielectric layer, a conductive layer located in the dielectric layer, and a connecting post located in the dielectric layer and in contact with the conductive layer.