Integrated circuit structure
Patent Information
- Application Number
- TW115201001
- Authority / Receiving Office
- TW · TW
- Patent Type
- Utility models
- Current Assignee / Owner
- Filing Date
- 2026-01-29
- Publication Date
- 2026-10-01
- Estimated Expiration
- 2036-01-28
Smart Images
Figure TWG2TB001914283_001 
Figure TWG2TB001914283_002 
Figure TWG2TB001914283_003
Abstract
Claims
1. An integrated circuit structure comprising: a chip, wherein an upper surface of the chip includes a first source electrode, a second source electrode, and a gate electrode; a first conductive plate comprising: a first contact portion electrically connected to the first source electrode; a second contact portion electrically connected to the second source electrode; and a first connecting portion electrically connected and located between the first contact portion and the second contact portion, wherein the first connecting portion has an opening exposing the chip; a second connecting portion connected to the first contact portion; a plurality of first signal transmission portions connected to the second connecting portion, wherein the first signal transmission portions are spaced apart by a plurality of grooves; and a second conductive plate comprising: a third contact portion electrically connected to the gate electrode, wherein the third contact portion has a curved profile; a third connecting portion connected to the third contact portion; and a second signal transmission portion connected to the third connecting portion.
2. The integrated circuit structure as claimed in claim 1, wherein the first connection portion is separated from the upper surface of the wafer.
3. The integrated circuit structure as claimed in claim 2, wherein an upper surface of the first connection portion is higher than the upper surfaces of the first contact portion and the second contact portion.
4. The integrated circuit structure as claimed in claim 1, wherein the third contact has a concave surface and a convex surface, wherein the convex surface contacts the gate electrode.
5. The integrated circuit structure as claimed in claim 1, wherein the third connection portion is separated from the upper surface of the wafer.
6. The integrated circuit structure as claimed in claim 1 further comprises: a first leadframe, wherein the first signal transmission units contact an upper surface of the first leadframe; and a plurality of first pins extending from the first leadframe.
7. The integrated circuit structure as claimed in claim 6 further includes: a second leadframe, wherein the second signal transmission section contacts an upper surface of the second leadframe; and a second pin extending from the second leadframe.
8. The integrated circuit structure as claimed in claim 1 further includes a carrier located below the wafer and electrically connected to the wafer.
9. The integrated circuit structure as described in claim 8 further includes a plurality of pins extending from the carrier.
10. The integrated circuit structure as claimed in claim 1, further comprising a housing covering the wafer, the first conductive piece, and the second conductive piece.