Low thermal expansion metal substrate packaging structure

TWM688562UActive Publication Date: 2026-10-11KINSUS INTERCONNECT TECH
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Patent Information

Application Number
TW115206498
Authority / Receiving Office
TW · TW
Patent Type
Utility models
Current Assignee / Owner
Filing Date
2026-07-09
Publication Date
2026-10-11
Estimated Expiration
2036-07-08

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Abstract

A low thermal expansion metal substrate packaging structure includes an alloy core substrate, insulating material, metal pillars, a first circuit layer, a second circuit layer, a first solder pad layer, a first solder resist layer, a second solder pad layer, and a second solder resist layer. The alloy core substrate has a coefficient of thermal expansion of less than or equal to 3 ppm / °C and a Young's modulus of greater than or equal to 100 GPa, and has a plurality of first through-holes. The insulating material covers the outer surface of the alloy core substrate and fills the first through-holes. The insulating material includes a plurality of second through-holes, which penetrate the insulating material filled in the first through-holes. The metal pillars are located in the second through-holes. The first circuit layer and the second circuit layer are located on the insulating material on both sides and connected to the metal pillars. The first spacing between the first solder pads in the first solder pad layer is smaller than the second spacing between the second solder pads in the second solder pad layer.
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Claims

1. A low thermal expansion metal substrate encapsulation structure, comprising: an alloy core substrate having a plurality of first through holes penetrating the alloy core substrate, wherein the alloy core substrate has a coefficient of thermal expansion less than or equal to 3 ppm / °C and a Young's modulus greater than or equal to 100 GPa; an insulating material covering the outer surface of the alloy core substrate and filling the first through holes, the insulating material comprising a first insulating layer, a second insulating layer and a plurality of second through holes, the first insulating layer and the second insulating layer being respectively located on a first surface and a second surface opposite to each other of the alloy core substrate, the aperture of the second through holes being smaller than the aperture of the first through holes and respectively penetrating the insulating material filled in the first through holes; a plurality of metal pillars respectively located in the second through holes; a first circuit layer located on the first insulating layer and connected to the metal pillars; and a second circuit layer located on the second insulating layer and connected to the metal pillars. A first solder pad layer comprising a plurality of first solder pads electrically connected to the first circuit layer; a first solder resist layer located on the first solder pad layer comprising a plurality of first solder resist openings, the first solder resist openings exposing the first solder pads respectively; a second solder pad layer comprising a plurality of second solder pads electrically connected to the second circuit layer, wherein a first spacing between the first solder pads is smaller than a second spacing between the second solder pads; and a second solder resist layer located on the second solder pad layer comprising a plurality of second solder resist openings, the second solder resist openings exposing the second solder pads respectively.

2. The low thermal expansion metal substrate packaging structure as described in claim 1, wherein the alloy core substrate is selected from the group consisting of Invar, Kovar, iron-platinum alloy, and iron-palladium alloy.

3. The low thermal expansion metal substrate encapsulation structure as described in claim 1, wherein the insulating material is an insulating resin.

4. The low thermal expansion metal substrate packaging structure as described in claim 3, wherein each of the metal pillars is an electroplated metal pillar.

5. The low thermal expansion metal substrate packaging structure as described in claim 3, wherein each of the metal pillars is an implanted metal pillar.

6. The low thermal expansion metal substrate packaging structure as described in claim 1, wherein the insulating material is an insulating oxide layer.

7. The low thermal expansion metal substrate packaging structure as described in claim 6, wherein each of the metal pillars is an implantable metal pillar, and a resin layer is further included between the implantable metal pillar and the wall of the second through hole.

8. The low thermal expansion metal substrate packaging structure as described in claim 6, wherein each of the metal pillars is an electroplated metal pillar.

9. The low thermal expansion metal substrate packaging structure as described in claim 1 further includes a first protective layer and a first redistribution circuit layer, the first protective layer and the first redistribution circuit layer being located between the first circuit layer and the first pad layer, the first protective layer covering the first circuit layer and having a plurality of first openings exposing a portion of the first circuit layer, the first redistribution circuit layer being located on the first protective layer and in the first openings and connected to the first circuit layer.

10. The low thermal expansion metal substrate packaging structure as described in claim 9 further includes a second protective layer covering the first redistribution circuit layer and having a plurality of second openings exposing a portion of the first redistribution circuit layer, wherein the first solder pad layer is located on the second protective layer and is filled into the second openings and connected to the first redistribution circuit layer.

11. The low thermal expansion metal substrate packaging structure as described in claim 9 further includes a third protective layer and a second redistribution circuit layer, the third protective layer and the second redistribution circuit layer being located between the second circuit layer and the second pad layer, the third protective layer covering the second circuit layer and having a plurality of third openings exposing a portion of the second circuit layer, the second redistribution circuit layer being located on the third protective layer and in the third openings and connected to the second circuit layer.

12. The low thermal expansion metal substrate packaging structure as described in claim 11 further includes a fourth protective layer covering the second redistribution circuit layer and having a plurality of fourth openings exposing a portion of the second redistribution circuit layer, wherein the second solder pad layer is located on the fourth protective layer and is filled into the fourth openings and connected to the second redistribution circuit layer.