Multilayer wiring structure

Abstract

A multilayer wiring structure is provided, comprising a first wiring layer and a second wiring layer. The first wiring layer includes at least one first functional region having conductive lines and at least one first non-functional region filled with dielectric material. The first non-functional region surrounds the first functional region and forms a first interface with the first functional region. The second wiring layer is stacked with the first wiring layer in a first direction, and includes at least one second functional region having conductive lines and at least one second non-functional region filled with dielectric material. The second functional region at least partially overlaps the first functional region in the first direction, and the conductive lines of the second functional region are connected to the conductive lines of the first functional region. The second non-functional region surrounds the second functional region and forms a second interface with the second functional region.

Claims

1. A multi-layer wiring structure, comprising: A first wiring layer includes: at least one first functional area with conductive lines; The system includes at least one first non-functional region filled with dielectric material, the first non-functional region surrounding the first functional region and forming a first interface with the first functional region; a second wiring layer stacked with the first wiring layer in a first direction and including: at least one second functional region having conductive lines, the second functional region at least partially overlapping the first functional region in the first direction, and the conductive lines of the second functional region being connected to the conductive lines of the first functional region; and at least one second non-functional region filled with dielectric material, the second non-functional region surrounding the second functional region and forming a second interface with the second functional region.

2. The multilayer wiring structure as described in claim 1, wherein the first interface and the second interface are substantially aligned in the first direction.

3. The multilayer wiring structure as claimed in claim 1, wherein the first non-functional area at least partially overlaps the second non-functional area in the first direction.

4. The multilayer cabling structure as claimed in claim 1, wherein the first cabling layer includes a plurality of the first functional areas spaced apart, and the first non-functional area fills the gaps between the first functional areas.

5. The multilayer cabling structure as described in claim 4, wherein at least one of the second functional areas bridges two of the first functional areas.

6. The multilayer wiring structure as claimed in claim 1, wherein the conductive line in the first functional area and the conductive line in the second functional area together form a cross-layer conductive path, the cross-layer conductive path alternately passing through the first functional area and the second functional area and advancing in the extension direction of the first wiring layer or the second wiring layer.

7. The multilayer wiring structure as claimed in claim 1, further comprising: a wafer disposed on the side of the second functional area away from the first wiring layer; and a molding layer covering the wafer and the surface of the second wiring layer away from the first wiring layer.

8. The multi-layer wiring structure as described in claim 7, wherein the width of the first functional area is greater than the width of the second functional area.

9. The multi-layer cabling structure as described in claim 7, wherein the line spacing of the first functional area is greater than the line spacing of the second functional area.

10. The multilayer wiring structure as claimed in claim 7, further comprising a plurality of conductive bumps disposed on the side of the first functional region away from the second wiring layer, a plurality of pads being provided between the chip and the second functional region, and the distance between the conductive bumps being greater than the distance between the pads.

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