Structure and method of multiplexing bitline signals within a memory array

Abstract

An integrated circuit memory is provided in which a multiplexer is operable to select one of a plurality of bitlines to couple to a master bitline using select transistors of an array of transistors, the array of transistors including access transistors of a storage cell array of the memory.

Description

BACKGROUND OF THE INVENTION [0001] As the storage capacity of an integrated circuit (IC) memory is increased from one generation to the next, the sizes of memory arrays increase, as measured in terms of the row and column space of the array, i.e., the number of wordlines of the memory array, as multiplied by the number of bitlines of the memory array. Memory arrays having larger numbers of wordlines and bitlines generally have less overhead in form of support circuitry for accessing the arrays, as a percentage of the total IC area occupied by the memory. Support circuitry including row decoders, wordline drivers, column decoders, first sense amplifiers and second sense amplifiers, etc. must be provided for every memory array on the IC. However, such support circuitry takes up a significant amount of IC area that cannot be used for the storage of data. To increase the utilization efficiency of IC area, it is therefore advantageous to increase the numbers of wordlines and bitlines of ...

AI Technical Summary

Benefits of technology

This approach reduces bitline capacitance, enables clearer signal distinction, and maintains access speed, improving the efficiency of memory array operations by reducing the length of bitlines and utilizing vertical transistors that occupy less chip area, thus enhancing storage capacity and access speed.

Problems solved by technology

However, such support circuitry takes up a significant amount of IC area that cannot be used for the storage of data.

In a conventional dynamic random access memory (DRAM), it is evident that a single memory array cannot have a row space including an arbitrary number of wordlines that is served by a single set of the same bitlines, because the bitlines which span the row space would have very large capacitance, such that the charge stored on a capacitor of a storage cell coupled to the bitline would appear as an extremely small signal, making it difficult to read the storage cell.

Even at the scale of integration density in today's leading DRAM technology, bitline capacitance can be, for example, 200 fF, which significantly exceeds the capacitance of a storage cell within the DRAM, which is, for example, 30 fF, such that bitline capacitance may soon become a limiting factor in the design of DRAMs.

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