Semiconductor Devices and Methods of Forming the Same

Abstract

Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be to adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This patent application claims priority from Korean Patent Application No. 10-2007-0044596, filed May 8, 2007, the contents of which are hereby incorporated by reference in their entirety.FIELD OF THE INVENTION[0002]The present invention relates generally to semiconductor devices and, more particulaly to semiconductor fabrication.BACKGROUND[0003]Generally, semiconductor devices are fabricated using a semiconductor substrate having a cell array region and a peripheral circuit region. The semiconductor substrate has a plurality of cell gate patterns in the cell array region and a plurality of peripheral gate patterns in the peripheral circuit region. The cell gate patterns and the peripheral gate patterns are simultaneously formed on the semiconductor substrate for simplifying a semiconductor manufacturing process. The cell gate patterns and the peripheral gate patterns are formed to overlap impurity diffusion regions disposed in the semicon...

AI Technical Summary

Benefits of technology

This approach enables the formation of semiconductor devices with higher integration density by allowing for the precise control of heat budgets in different regions, facilitating the reduction of impurity diffusion regions and enhancing the performance of semiconductor devices.

Problems solved by technology

However, when the selected insulating layer is used, the electrical characteristics of the semiconductor device may not be easily controlled according to a reduced design rule of a semiconductor device.

However, the semiconductor integrated circuit device cannot have a smaller size of the semiconductor regions below the gate electrodes as compared with prior to a reduced design rule while the silicon oxide layer is formed in the logic portion and the DRAM portion of the semiconductor substrate.

As a result, the silicon oxide layer may not correspond to the reduced design rule, so that it can be difficult to realize a semiconductor integrated circuit device having high integration density.

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