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Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions

a technology of exposed regions and semiconductors, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of adversely affecting the production yield of the device, the inability to simultaneously activate left and right transistors, and the significant deterioration of the device characteristics

Inactive Publication Date: 2011-11-10
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach improves transistor characteristics, reduces bump failure rates, and increases production yield by up to 20% by maintaining uniform offset characteristics and reducing two-column failure rates.

Problems solved by technology

However, during operation of the transistors, the left and right transistors may not be simultaneously activated due to a variation in the threshold voltage between the left and right transistors.
Thus, the characteristics of the device significantly deteriorate.
The difference between the threshold voltages of the transistors included in the sense amplifier deteriorates the offset characteristics of the sense amplifier, thereby adversely affecting the production yield of the device.

Method used

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  • Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions
  • Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions
  • Method of fabricating a semiconductor device including ion implantation at a tilt angle in exposed regions

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Embodiment Construction

[0029]The present invention examines the cause of mismatched transistors included in a sense amplifier and provides a method of solving problems associated with the mismatch. In order to examine the cause of the mismatch, the mask layout of the sense amplifier will be described.

[0030]FIG. 3 is a view showing a mask layout of a sense amplifier.

[0031]Four transistors are symmetrically provided between a pair of bit lines BL (210) and / BL (220). In particular, two left transistors are spaced from the edge of a P-well 230 by at least a predetermined distance, and two right transistors are spaced from the edge of the P-well 230 by about 0.9 μm.

[0032]As shown in FIG. 2, the bump failure rate of the two right transistors 240 is larger than that of the two left transistors. Accordingly, the bump failure rate is associated with the distance between the transistor and the P-well.

[0033]In order to fabricate a semiconductor memory device, a variety of processes including a laminating process, a...

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Abstract

A method of fabricating a semiconductor device includes forming a mask pattern for defining a region on a semiconductor substrate. A well will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 10-2006-0137138, filed on Dec. 28, 2006, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of ion implantation and a method of fabricating a semiconductor device which increases the production yield of the semiconductor device.[0003]A semiconductor memory device such as a dynamic random access memory (DRAM) stores data in and reads data from a plurality of memory cells. The semiconductor memory device includes a plurality of bit lines and a plurality of word lines. The semiconductor memory device also includes a circuit for selecting a bit line and a word line. The semiconductor memory device further includes peripheral circuits, such as a sense amplifier, for sensing data read from a memory cell and for amplifying ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/265H10B12/00
CPCH01L21/26586H01L29/1083H01L29/1045H01L21/265H10B99/00H10B12/00
Inventor LEE, MIN YONGJUNG, YONG SOO
Owner SK HYNIX INC
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