Phase interpolation circuit

Abstract

A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 100133747, filed on Sep. 20, 2011. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The invention relates to a phase interpolation circuit. Particularly, the invention relates to a phase interpolation circuit capable of generating a differential output signal with 50% of duty cycle.[0004]2. Description of Related Art[0005]In a high-speed transmission interface module (for example, a universal serial bus (USB) 3.0 interface module), a clock and data recovery circuit is generally configured to recover signals containing noise components, where a phase interpolation circuit is a core circuit composing the clock and data recovery circuit. Therefore, it is an important issue to ameliorate the phase interpolation circuit...

AI Technical Summary

Benefits of technology

The solution stabilizes the duty cycle of differential output signals, mitigates variations caused by process changes, and expands the operating range of the phase interpolation circuit, enhancing its performance in high-speed transmission environments.

Problems solved by technology

Therefore, it is an important issue to ameliorate the phase interpolation circuit to improve whole performance of the clock and data recovery circuit.

However, the phase interpolation circuit of the current mode logic has following disadvantages: (1) a linearity thereof is liable to be influenced by a parasitic capacitance and a front-end circuit load, so that a duty cycle of an output signal has a great variation, especially under an influence of process variation; (2) it is of no avail for low-voltage operations, which leads to a limited operating range.

Therefore, how to adjust the duty cycle of the output signal or implement the low-voltage operations is an important issue to be developed in design of the phase interpolation circuit.

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