Components for interfacing a semiconductor die to a printed circuit board
VN10059543BActive Publication Date: 2026-08-03QUALCOMM INC
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Patent Information
- Application Number
- VN1202208627
- Authority / Receiving Office
- VN · VN
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-07-01
- Publication Date
- 2026-08-03
- Estimated Expiration
- 2041-07-01
Abstract
The invention refers to the components used to mount semiconductor dies onto printed circuit boards (PCBs). A pin map covers the surface area of each layer of the printed circuit board (PCB). The pin map includes multiple electrical symbols for each pin in the pin map and several empty spaces within the pin map. Each electrical symbol can be assigned to a pin on the pin map. Each electrical symbol includes a positive polarity (P+), a negative polarity (P-), or a ground (G) pin. If the space in the pin map is not electrically marked, it may include the blank / plain space of a printed circuit board (PCB). The pin map may include multiple rows and a first-order repeating pin polarity pattern. The first-order repeating pin polarity pattern may include a unit cell. The pin map may facilitate the connection of two circuit elements attached to a single layer of the PCB. In addition, the invention relates to a method for planning the connection location between circuit elements.
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