MEMORY AND METHODS FOR CHECKING MEMORY COLUMNS

Abstract

The invention relates to a memory and method for checking columns in memory. The proposed memory consists of a scan sequence comprising redundant logic circuits for column redundancy as well as redundant multiplexers in each column. The redundant logic circuit comprises multiple redundant logic circuits arranged in series. Each redundant logic circuit corresponds to a corresponding column in memory. Each column is configured to route the input signal through its redundant multiplexers while operating in scan mode.