Direct backside power delivery system for stacked chips
The direct power delivery system using a permanent carrier to supply power to the top side of stacked semiconductor chips addresses efficiency and heat dissipation issues, improving performance and flexibility in stacked chip designs.
Patent Information
- Application Number
- PCT/IB2025/061489
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-05
- Filing Date
- 2025-11-11
- Publication Date
- 2026-06-11
AI Technical Summary
Stacked semiconductor chips face challenges in efficient power delivery and heat dissipation due to complex manufacturing processes and intricate design requirements, particularly when powering the backside power delivery network (BSPDN) through the chip stack.
A direct power delivery system is implemented using a permanent carrier that supplies power signals directly to the BSPDN on the top side of the chip stack, bypassing the need for power transmission through individual chips, and includes features like through vias, redistribution layers, and hybrid bonding to enhance efficiency and heat dissipation.
This approach improves power delivery efficiency, reduces heat dissipation challenges, and enhances the overall performance and flexibility of stacked chip designs by allowing for better heat management and reduced fabrication defects.