METHOD FOR SELECTING A HARDWARE ARCHITECTURE FOR IMPLEMENTING A SOFTWARE APPLICATION

Abstract

The invention relates to a method for determining a target hardware architecture suitable for a software application, the method comprising steps consisting in: defining a first input data set (ID0) of the application (AL2); executing the application by a processor (PRC) from the first input set to obtain a first output data set (OD0); executing several iterations each comprising: selecting an input data item; generating a second input set (ID1, ID2) from the first input set, by modifying the selected input data item; executing the application from the second input set to obtain a second output set (OD1, OD2); and calculating a metric relating to the first and second input and output sets of the iteration; calculating a parallelization score (PS) from the metrics calculated at each iteration; and determining the target architecture according to the parallelization score.

Description

Technical field

[0001] The present invention relates to the determination of a hardware architecture suitable for the implementation of a software application. State of the art

[0002] Software applications are becoming increasingly complex. In addition, there are a large number of hardware architectures, including a large number of single-core and multi-core microprocessors, microcontrollers, programmable logic circuits such as FPGAs (Field-Programmable Gate Arrays), systems-on-chips (SOCs), graphics processing units (GPUs), and artificial intelligence engines. These hardware architectures each have advantages and disadvantages. When a software application is to be embedded, it is necessary to determine the most suitable hardware architecture, particularly in terms of execution speed, power consumption, and computing resource requirements, as well as in terms of application development costs.

[0003] It is known to determine empirically, that is to say by experimentation, the hardware architecture adapted to the most efficient implementation of an application. To this end, the application must be executed on different target hardware architectures to evaluate its performance. This execution can also be simulated. Whether simulated or executed directly on the target architectures, the application must be ported to each of them, providing for a possible prior adaptation and / or optimization for each target architecture. This porting operation may require rewriting the application in an appropriate programming language depending on the target architecture,

[0004] This approach, generally called "dynamic program analysis," is tedious and expensive, and requires detailed knowledge of the target architecture and a programming language adapted to it.

[0005] It is therefore desirable to be able to easily determine a type of hardware architecture that is best suited to a given software application. In particular, it is desirable to be able to determine such a type of hardware architecture without having to know a particular hardware architecture or a particular programming language. It may also be desirable to achieve this result without having to know or determine the internal structure of the software application. Summary

[0006] Embodiments relate to a method for determining a target hardware architecture for implementing a software application having input data and output data, the method comprising steps of: defining a first set of input values ​​assigning a value to each of the input data of the software application; executing the software application by a processor from the first set of input values ​​to obtain a first set of output values ​​assigning a value to each of the output data of the software application; executing several iterations, each iteration comprising steps of: selecting an input data from the input data of the software application;generating a second set of input values ​​from the first set of input values ​​or from a second set of input values ​​generated during a previous iteration, by modifying the value of the selected input data, the selected data being different from input data selected during previous iterations; executing the software application by the processor from the second set of input values ​​to obtain a second set of output values; and calculating by the processor a metric result relating to the first sets of input and output values ​​and the second sets of input and output values ​​of the iteration, the metric result representing an impact of a modification of the first set of input values ​​on the first set of output values; calculating by the processor a parallelization score from the metric results calculated at each iteration;and determine the target hardware architecture based on the parallelization score.;

[0007] In this way, a hardware architecture suitable for a defined software application can be determined without having to carry out multiple and very costly tests of execution of the application by different architectures. It is also not necessary to analyze in detail the application code to evaluate possibilities of implementing parallel operations, nor to know in detail the target architectures. The method can be implemented by any processor, as long as the latter is compatible with the programming language and / or the compiler used to generate the executable code of the application.

[0008] According to one embodiment, the number of iterations executed corresponds to a number of elements in the input data of the software application, each element being individually manipulable by the processor.

[0009] In this way, a large number of possibilities for parallel execution of application operations can be explored and highlighted.

[0010] According to one embodiment, the metric calculated using a function belongs to a set comprising: a correlation function applied to the first and second sets of values, a signal-to-noise ratio calculation function, a function for calculating a number of modified output values ​​in the second set of output values ​​relative to the first set of output values ​​relative to a number of modified values ​​in the second set of input values ​​relative to the first set of input values, a function for locating modified elements in the second set of outputs, a function for calculating a number of modified data, elements or bits in the second set of output values, and a function for calculating the maximum and / or minimum distance between modified elements in the second set of output values.

[0011] According to one embodiment, the calculation of the parallelization score comprises at least one of the following calculations: a sum of the metric results, a mean calculation of the metric results, a variance or standard deviation calculation applied to the metric results, a Euclidean distance calculation applied to the metric results, and a Manhattan, Minkowski and / or Cheychev type distance calculation applied to the metric results.

[0012] According to one embodiment, the target hardware architecture is selected from among elements of a set of hardware architectures, a range of parallelization score values ​​being assigned to each element of the set of hardware architectures.

[0013] This greatly simplifies the selection of a hardware architecture based on the parallelization score.

[0014] According to one embodiment, the set of hardware architectures includes a single-core microprocessor, a multi-core microprocessor, a graphics processor, and a programmable logic circuit.

[0015] According to one embodiment, the method further comprises steps consisting of: generating from the software application, an executable code adapted to the determined target hardware architecture, and installing the executable code in the target hardware architecture, in order to produce a device performing functions offered by the software application. Brief description of the figures

[0016] The present invention will be better understood with the aid of the following description of exemplary embodiments with reference to the appended figures, in which identical reference signs correspond to structurally and / or functionally identical or similar elements. There Figure 1represents steps of a method for determining a hardware architecture suitable for the implementation of a software application, according to one embodiment, The Figure 2 represents a simplified example of execution of a software application from different input data sets, illustrating a step of evaluating output data of the method, according to one embodiment, The Figure 3 represents a simplified example of executing another software application from different input data sets, illustrating the step of evaluating output data of the method, according to one embodiment, The Figure 4 represents a simplified example of executing another software application from different input data sets, illustrating the step of evaluating output data of the method, according to one embodiment. Detailed description

[0017] There Figure 1represents steps S1 to S10 of a method for determining a hardware architecture suitable for implementing an ALG software application, according to one embodiment. Steps S1 to S10 can be executed by a processor capable of executing the ALG application. In step S1, an initial set of input data values ​​ID[0] is defined for an ALG software application. In what follows, the term "data" designates a set bringing together one or more elements that can be individually manipulated by the PRC processor executing the software application. Thus, each element can be made up of one or more bits, the minimum number of bits forming an element constituting a predefined characteristic of the hardware architecture to be defined. For example, image-type data or signal acquisition is made up of elements (pixels or samples) formed of several bits.

[0018] In step S2, an initial output data value set OD[0] is calculated by executing the ALG application from the input data value set ID[0]. The ALG application is therefore available in the form of executable or interpretable code. In step S3, an index J is initialized for a first iteration of execution of steps S4 to S8. In step S4, an input data value set ID[J] is obtained using a derivation function DER applied to the input value set ID[0], so that the input value set ID[J] is different from all input value sets ID[J] previously generated during previous executions of step S4. For this purpose, the derivation function DER can receive the iteration index J. In step S5, the input value set ID[J] is provided to the ALG application to obtain a corresponding output data value set OD[J].In step S6, a metric or set of metrics SC[J] is calculated for iteration J using one or more metric calculation functions FS applied to the sets of input values ​​ID[J] and output values ​​OD[J] of iteration J and to the initial data sets of input values ​​ID[0] and output values ​​OD[0].

[0019] In step S7, the index J is incremented by 1. In step S8, the index J is compared to a maximum number of iterations N to be executed. If the last iteration of index N is not executed, steps S4 to S8 are executed again, otherwise steps S9 and S10 are executed. In step S9, a parallelization score PS is calculated by applying a function for calculating such a score to the metric values ​​SC[J] obtained during the successive executions of step S6. In step S10, a hardware architecture TA is determined based on the score PS. According to one embodiment, the hardware architecture TA is specified in a table ATB referencing hardware architectures based on the possible values ​​of the score PS.

[0020] The selection of a hardware architecture based on the PS score may be followed by the generation of executable code suitable for the selected hardware architecture and the installation of this executable code in the hardware architecture, in order to produce a device realizing the functions offered by the software application. The generation of executable code suitable for the selected hardware architecture may include rewriting the software application in an appropriate language, possibly with a reorganization of the operations of the application, in particular in the case where the selected hardware architecture is capable of executing operations simultaneously or in parallel.

[0021] The derivation function DER used in step S4 may use the received index J to determine a data item to be modified in the initial input value set ID[0] to generate the input value set ID[J]. Thus, the maximum number of iterations N to be executed may correspond to the number of input data items of the software application. More generally, combinations of possible alterations of the input value set ID[0] are determined. The maximum number of iterations N may then correspond to the number of these alteration combinations. Thus, in some applications, it is possible to determine all of these alteration combinations.

[0022] The metric SC[J] calculated in step S6 may comprise a correlation function applied to the sets of values ​​ID[J], OD[J], ID[0], OD[0], and / or a signal-to-noise ratio calculation function, and / or a function for calculating the number of modified output values ​​in the output set OD[J] with respect to the initial set of output values ​​OD[0] relative to the number of modified values ​​in the input set ID[J] with respect to the initial set of input values ​​ID[0]. More simply, the metric calculated in step S6 may provide a number of modified data, elements or bits in the output set, and / or a location of the modified elements in the output set, and / or a distance, for example a maximum and / or minimum distance between the modified elements in the output set.

[0023] More generally, the metric calculated in step S6 provides a representative number or a quantification of the impact or extent of the modifications on the output set resulting from a modification of the input set, in particular in terms of the number and positions of the modified output data relative to the initial output data set. For example, a high metric result may reflect a small modification of the output set, for example a reduced number of modified data between the initial output data set and the output data set obtained from the modified input data set.

[0024] The PS parallelization score calculated in step S9 may comprise a distance calculation between the metric values ​​obtained at each execution of step S6. This score calculation may comprise a sum, and / or a mean calculation, and / or a variance or standard deviation calculation and / or a Euclidean distance calculation, and / or a Manhattan, Minkowski, and / or Cheychev type distance calculation.

[0025] The PS parallelism score is evaluated for all metrics. For example, a high score means that the software application being analyzed has a low level of parallelism, while a low score means that the software application being analyzed has a high level of parallelism.

[0026] Target hardware architectures can be microprocessor, programmable logic circuit, or graphics processing unit (GPU). The ATB table referencing hardware architectures based on possible PS score values ​​can associate a range of PS score values ​​with each of these hardware architecture types.

[0027] THE figures 2 to 4 illustrate the steps S2 and maximum number of iterations N to be executed S5 for three types of software applications AL1, AL2, AL3 executed by a PRC processor. The figures 2 to 4present in particular an example of an initial input data value set ID0 and the corresponding output data value set OD0 obtained in step S2, and examples of input data value sets ID1, ID2 used respectively during two successive executions of step S5 and the corresponding output data value sets OD1, OD2. The input value sets ID1, ID2 differ from the initial input value set ID0 in that only one input data item is modified.

[0028] In the output value sets OD11, OD12 of the Figure 2 , corresponding to the input value sets ID1, ID2, only one data item is modified compared to the initial output value set OD0. The Figure 2therefore illustrates the case of an AL1 application with a low parallelization score. It follows that the hardware architecture best suited to the AL1 application may be of the programmable logic circuit type suitable for software applications that can be highly parallelized.

[0029] In the output value sets OD12, OD22 of the Figure 3 , corresponding to the input value sets ID1, ID2, four data are modified compared to the initial output value set OD0. The Figure 3 therefore illustrates the case of an AL2 application with a higher parallelization score than that of the AL1 application. It follows that the hardware architecture best suited to the AL2 application may be of the graphics processor type.

[0030] In the output value sets OD13, OD23 of the Figure 4, corresponding to the input value sets ID1, ID2, six data are modified compared to the initial output value set OD0. The Figure 4 therefore illustrates the case of an AL3 application with a higher parallelization score than that of the AL2 application and which can therefore be weakly or not at all parallelized. It follows that the hardware architecture most suited to the AL3 application is of the single-core microprocessor type executing a program.

Claims

1. Method for determining a target hardware architecture for implementing a software application comprising input data and output data, the method comprising steps consisting of: defining a first set of input values ​​(ID[0]) assigning a value to each of the input data of the software application (ALG); executing the software application by a processor (PRC) from the first set of input values ​​to obtain a first set of output values ​​(OD[0]) assigning a value to each of the output data of the software application; executing several iterations, each iteration comprising steps consisting of: selecting an input data from the input data of the software application;generating a second set of input values ​​(ID[J]) from the first set of input values ​​or from a second set of input values ​​generated during a previous iteration, by modifying the value of the selected input data, the selected data being different from input data selected during previous iterations; executing the software application by the processor from the second set of input values ​​to obtain a second set of output values ​​(OD[J]); and calculating by the processor a metric result (SC[J]) relating to the first sets of input and output values ​​and the second sets of input and output values ​​of the iteration, the metric result representing an impact of a modification of the first set of input values ​​on the first set of output values; calculating by the processor a parallelization score (PS) from the metric results calculated at each iteration;and determine the target hardware architecture based on the parallelization score.; 2. Method according to claim 1, in which the number (N) of iterations executed corresponds to a number of elements in the input data of the software application (ALG), each element being individually manipulable by the processor (PRC).

3. Method according to claim 1 or 2, wherein the metric (SC[J]) calculated using a function belongs to a set comprising: a correlation function applied to the first and second sets of values ​​(ID[J], OD[J], ID[0], OD[0]), a signal-to-noise ratio calculation function, a function for calculating a number of modified output values ​​in the second set of output values ​​(OD[J]) relative to the first set of output values ​​(OD[0]) relative to a number of modified values ​​in the second set of input values ​​(ID[J]) relative to the first set of input values ​​(ID[0]), a function for locating modified elements in the second set of outputs, a function for calculating a number of modified data, elements or bits in the second set of output values, and a function for calculating the maximum and / or minimum distance between modified elements in the second set of output values.

4. Method according to one of claims 1 to 3, in which the calculation of the parallelization score (PS) comprises at least one of the following calculations: a sum of the metric results (SC[J]), a calculation of the average of the metric results, a calculation of variance or standard deviation applied to the metric results, a calculation of Euclidean distance applied to the metric results, and a Manhattan, Minkowski and / or Tcheychev type distance calculation applied to the metric results.

5. Method according to one of claims 1 to 4, in which the target hardware architecture is selected from elements of a set of hardware architectures, a range of parallelization score (PS) values ​​being assigned to each element of the set of hardware architectures.

6. The method of claim 5, wherein the set of hardware architectures comprises a single-core microprocessor, a multi-core microprocessor, a graphics processor, and a programmable logic circuit.

7. Method according to one of claims 1 to 6, further comprising steps consisting of: generating from the software application, an executable code adapted to the determined target hardware architecture, and installing the executable code in the target hardware architecture, in order to produce a device performing functions offered by the software application.