Heterojunction battery and preparation method therefor

Abstract

A heterojunction battery and a preparation method therefor. The heterojunction battery comprises a crystalline silicon layer (1), wherein a first intrinsic amorphous silicon layer (2), an N-type doped amorphous silicon layer (3), a first transparent conductive layer (4) and a first metal electrode (5) are sequentially arranged on the front face of the crystalline silicon layer (1) from inside to outside, and a second intrinsic amorphous silicon layer (6), a P-type doped amorphous silicon layer (7), a second transparent conductive layer (8) and a second metal electrode (9) are sequentially arranged on the back face of the crystalline silicon layer (1) from inside to outside; and a local reduction layer (10) is formed on the surface of the first transparent conductive layer (4) that is under the first metal electrode (5) and / or on the surface of the second transparent conductive layer (8) that is under the second metal electrode (9).

Description

Heterojunction battery and preparation method thereof

[0001] Related applications

[0002] This application claims priority to the Chinese patent application filed on May 16, 2022, with application number 202210530719.0, and invention name “A heterojunction battery and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of heterojunction batteries, and more specifically, to a heterojunction battery and a method for preparing the same. Background Art

[0004] Single-crystal silicon heterojunction solar cells have high conversion efficiency and are recognized by the photovoltaic industry as one of the key technologies for the next generation of large-scale industrialization.

[0005] Silicon-based heterojunction solar cells are generally made of N-type single-crystal silicon wafers with a double-sided pyramid velvet structure. An intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are deposited on the front of the silicon wafer, and an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer are deposited on the back of the silicon wafer. Then, a transparent conductive film and metal electrodes are formed on both sides of the silicon wafer respectively.

[0006] In related technologies, the transparent conductive layer is easily affected by water vapor, oxygen, and organic matter adsorption in the air, which causes the contact performance between the transparent conductive layer and the low-temperature slurry to deteriorate, the contact resistance to increase, and ultimately leads to low battery efficiency.

[0007] Summary of the Invention

[0008] According to various embodiments of the present application, a heterojunction cell is provided, comprising a crystalline silicon layer, wherein a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer, and a first metal electrode are sequentially arranged on the front side of the crystalline silicon layer from the inside out, and a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conductive layer, and a second metal electrode are sequentially arranged on the back side of the crystalline silicon layer from the inside out. A localized reduction layer is formed on the surface of the first transparent conductive layer at a position below the first metal electrode and / or on the surface of the second transparent conductive layer at a position below the second metal electrode, wherein the carrier concentration of the localized reduction layer is higher than that of the first transparent conductive layer and / or the second transparent conductive layer.

[0009] By setting a local reduction layer on the surface of the transparent conductive layer below the metal electrode, the contact resistance between the transparent conductive layer and the metal electrode is improved, and the battery filling factor and photoelectric conversion efficiency are improved.

[0010] In some embodiments, the local reduction layer has a width of 5 μm-50 μm.

[0011] In some embodiments, the crystalline silicon layer is N-type doped single crystal silicon, N-type doped analog single crystal silicon, P-type doped single crystal silicon or P-type doped analog single crystal silicon, and the thickness of the crystalline silicon layer is 50 μm-250 μm.

[0012] In some embodiments, the first intrinsic amorphous silicon layer is a composite thin film layer of undoped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide semiconductor thin films or a combination thereof, and the thickness of the first intrinsic amorphous silicon layer is 2nm-8nm.

[0013] In some embodiments, the N-type doped amorphous silicon layer is a composite thin film layer of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor thin films or a combination thereof, and the thickness of the N-type doped amorphous silicon layer is 4nm-30nm.

[0014] In some embodiments, the P-type doped amorphous silicon layer is a composite thin film layer of P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor films or a combination thereof, and the thickness of the P-type doped amorphous silicon layer is 4nm-30nm.

[0015] In some embodiments, the first transparent conductive layer is a composite thin film layer stacked by doped indium oxide, zinc oxide or tin oxide or a combination thereof, and the thickness of the first transparent conductive layer is 70nm-120nm; the second transparent conductive layer is a composite thin film layer stacked by doped indium oxide, zinc oxide or tin oxide or a combination thereof, and the thickness of the second transparent conductive layer is 70nm-120nm.

[0016] In some embodiments, the first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films, wherein the mass percentage of indium element in the first transparent conductive layer and the second transparent conductive layer is 90%, and the mass percentage of tin element in the first transparent conductive layer and the second transparent conductive layer is 10%.

[0017] In some embodiments, the first metal electrode is a low-temperature metal paste electrode composed of Ag, Cu, Al, Ni, or a combination thereof, and has a thickness of 10 μm to 50 μm and a width of 5 μm to 50 μm. The second metal electrode is a low-temperature metal paste electrode composed of Ag, Cu, Al, Ni, or a combination thereof, and has a thickness of 10 μm to 50 μm and a width of 5 μm to 50 μm.

[0018] The present application also provides a method for preparing the above-mentioned heterojunction battery, comprising the following steps:

[0019] Step 1, providing a crystalline silicon layer;

[0020] Step 2: texturing the surface of the crystalline silicon layer and cleaning the surface of the crystalline silicon layer;

[0021] Step 3: depositing a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer in sequence on the front surface of the crystalline silicon layer obtained in Step 2, and depositing a second intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back surface of the crystalline silicon layer obtained in Step 2;

[0022] Step 4: depositing a first transparent conductive layer on the N-type doped amorphous silicon layer obtained in step 3, and depositing a second transparent conductive layer on the P-type doped amorphous silicon layer obtained in step 3;

[0023] Step 5: placing a mask on the surface of the first transparent conductive layer and / or the second transparent conductive layer, and locally cleaning and reducing the transparent conductive layer using hydrogen plasma treatment to obtain a local reduced area with a relatively increased local carrier concentration, wherein the width of the local reduced area is 5 μm-50 μm, and can be optionally 30 μm-50 μm;

[0024] Step six, forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask plate, and the first metal electrode and / or the second metal electrode are located directly above the local reduction area.

[0025] In some embodiments, a mask having an opening pattern consistent with a metal electrode pattern is placed on the surface of the transparent conductive layer, and then the transparent conductive layer is locally cleaned and reduced using hydrogen plasma treatment to obtain a local reduction layer with a relatively increased local carrier concentration.

[0026] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the implementation methods of the present application, the following is a brief introduction to the drawings required for use in the implementation methods. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0028] FIG1 is a diagram of a battery layer structure in one embodiment of the present application.

[0029] FIG2 is a flow chart of a heterojunction battery preparation process in one embodiment of the present application.

[0030] In the figure, 1. crystalline silicon layer; 2. first intrinsic amorphous silicon layer; 3. N-type doped amorphous silicon layer; 4. first transparent conductive layer; 5. first metal electrode; 6. second intrinsic amorphous silicon layer; 7. P-type doped amorphous silicon layer; 8. second transparent conductive layer; 9. second metal electrode; 10. local reduction layer. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is sought, but merely represents the selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] This embodiment forms a localized reduction zone on the surface of the transparent conductive layer below the low-temperature metal paste electrode, thereby increasing the local carrier concentration of the transparent conductive layer and reducing the interface barrier height between the transparent conductive layer and the low-temperature metal paste electrode, thereby achieving a lower contact resistance. In addition, the locally treated surface is cleaner and is not affected by the adsorption of water vapor, oxygen, and organic matter. As shown in Figure 1, in some embodiments of the present application, a heterojunction cell includes a crystalline silicon layer 1, on the front side of the crystalline silicon layer 1, a first intrinsic amorphous silicon layer 2, an N-type doped amorphous silicon layer 3, a first transparent conductive layer 4, and a first metal electrode 5 are sequentially arranged from the inside to the outside, and a second intrinsic amorphous silicon layer 6, a P-type doped amorphous silicon layer 7, a second transparent conductive layer 8, and a second metal electrode 9 are sequentially arranged from the inside to the outside on the back side of the crystalline silicon layer 1, wherein: a localized reduction layer 10 is formed on the surface of the first transparent conductive layer 4 below the first metal electrode 5 and / or on the surface of the second transparent conductive layer 8 below the second metal electrode 9, and the carrier concentration of the localized reduction layer 10 is higher than that of the first transparent conductive layer and / or the second transparent conductive layer.

[0033] By setting a local reduction layer on the surface of the transparent conductive layer below the metal electrode, the contact resistance between the transparent conductive layer and the metal electrode is improved, thereby improving the battery filling factor and photoelectric conversion efficiency.

[0034] In some embodiments, the local reduction layer 10 has a width of 5 μm to 50 μm.

[0035] In some embodiments, the crystalline silicon layer 1 is N-type doped single crystal silicon, N-type doped analog single crystal silicon, P-type doped single crystal silicon or P-type doped analog single crystal silicon, and has a thickness of 50 μm-250 μm.

[0036] In some embodiments, the first intrinsic amorphous silicon layer is a composite thin film layer of undoped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide semiconductor thin films or a combination thereof, and has a thickness of 2 nm to 8 nm.

[0037] In some embodiments, the N-type doped amorphous silicon layer is a composite thin film layer of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor thin films or combinations thereof, and has a thickness of 4nm-30nm.

[0038] In some embodiments, the P-type doped amorphous silicon layer is a composite thin film layer of P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor films or a combination thereof, and the thickness of the P-type doped amorphous silicon layer is 4nm-30nm.

[0039] In some embodiments, the first transparent conductive layer is a composite thin film layer of doped indium oxide, zinc oxide or tin oxide or a combination thereof, and its thickness is 70nm-120nm; the second transparent conductive layer is a composite thin film layer of doped indium oxide, zinc oxide or tin oxide or a combination thereof, and its thickness is 70nm-120nm.

[0040] In some embodiments, both the first transparent conductive layer and the second transparent conductive layer are ITO (indium tin oxide) transparent conductive films, wherein the mass percentage of indium element is 90% and the mass percentage of tin element is 10%.

[0041] In some embodiments, the first metal electrode is a low-temperature metal slurry electrode composed of a composite of Ag, Cu, Al, Ni or a combination thereof, with a thickness of 10μm-50μm and a width of 5μm-50μm; the second metal electrode is a low-temperature metal slurry electrode composed of a composite of Ag, Cu, Al, Ni or a combination thereof, with a thickness of 10μm-50μm and a width of 5μm-50μm.

[0042] This embodiment also provides a method for preparing the above-mentioned heterojunction battery, which includes the following steps.

[0043] Step S101: providing a crystalline silicon layer, including using an N-type Czochralski single crystal silicon wafer with a thickness of 50 μm-250 μm, a resistivity of 3 Ω·cm, and a minority carrier lifetime of 2000 μs.

[0044] Step S102: Texturing and cleaning the surface of the crystalline silicon layer, including texturing the silicon wafer using a 2% by mass solution of NaOH and a texturing additive. The silicon wafer is then cleaned using a standard RCA cleaning method to remove surface contaminants. Next, the surface oxide layer is removed using a 2% by mass hydrofluoric acid solution.

[0045] Step S103: Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to deposit a first intrinsic amorphous silicon layer with a thickness of 2 nm to 8 nm on the front surface of the crystalline silicon layer. The reaction gases are SiH4 and H2, with a flow ratio of H2 to SiH4 of 5:1. The power density of the PECVD equipment is 20 mW / cm 2 , pressure of 70Pa, substrate temperature of 200℃; then, an N-type doped amorphous silicon layer with a thickness of 4nm-30nm is deposited on the first intrinsic amorphous silicon, wherein the reaction gases are SiH4, H2 and PH3, the flow ratio of H2 to SiH4 is 5:1, the flow ratio of PH3 to SiH4 is 0.02, and the power density of the PECVD equipment is 15mW / cm 2 , pressure 80Pa, substrate temperature 200℃. PECVD process is used to deposit a second intrinsic amorphous silicon with a thickness of 2nm-8nm on the front of the crystalline silicon layer. The reaction gases are SiH4 and H2, where the flow ratio of H2 to SiH4 is 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure of 70Pa, substrate temperature of 200℃; then, a P-type doped amorphous silicon layer with a thickness of 4nm-30nm is deposited on the second intrinsic amorphous silicon. The reaction gases are SiH4, B2H6 and H2, where the flow ratio of H2 to SiH4 is 4, the flow ratio of B2H6 to SiH4 is 0.04, and the power density of the PECVD equipment is 15mW / cm 2 , the pressure is 60Pa, and the substrate temperature is 200℃.

[0046] Step S104: Using a PVD (Physical Vapor Deposition) method, a first transparent conductive layer having a thickness of 70 nm to 120 nm is deposited on the N-type doped amorphous silicon layer, and a second transparent conductive layer having a thickness of 70 nm to 120 nm is deposited on the P-type doped amorphous silicon layer. Both the first and second transparent conductive layers are ITO transparent conductive films, wherein the mass percentage of indium in the ITO is 90% and the mass percentage of tin is 10%. The PVD apparatus is filled with Ar and O2, with an O2 to Ar flow ratio of 0.025, a pressure of 0.5 Pa, and the substrate temperature is room temperature.

[0047] Step S105: placing a mask plate on the surface of the first transparent conductive layer and / or the second transparent conductive layer, wherein the opening pattern of the mask plate is consistent with the metal electrode pattern, and locally cleaning and reducing the transparent conductive layer by hydrogen plasma treatment to obtain a local reduction area with a relatively increased local carrier concentration, wherein the width of the local reduction area is between 5 μm and 50 μm, and can be optionally between 30 μm and 50 μm; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and / or the second transparent conductive layer.

[0048] Step S106: forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask plate, and the first metal electrode and / or the metal electrode are located directly above the local reduction area.

[0049] In some embodiments of the present application, a mask plate is placed on the surface of the transparent conductive layer, the opening pattern of the mask plate is consistent with the metal electrode pattern, and then hydrogen plasma treatment is used to locally clean and reduce the transparent conductive layer to obtain a local reduction layer with a relatively increased local carrier concentration.

[0050] In the present application, the surface of the crystalline silicon layer is the front side of the crystalline silicon layer, the back side of the crystalline silicon layer or a combination thereof.

[0051] In some embodiments of the present application, the texturing additive is a commonly used texturing additive in the art. In some embodiments of the present application, the texturing additive includes an alkaline mixture including alkali, surfactant, weak acid salt, water and other ingredients.

[0052] In some embodiments of the present application, the mask plate is selected from common mask plates in the art. In some embodiments of the present application, the mask plate is selected from a mask plate of a resin substrate or a mask plate of a glass substrate.

[0053] In some embodiments of the present application, the RCA standard cleaning method is used to clean the crystalline silicon layer after texturing. The RCA standard cleaning method includes the following steps.

[0054] (1) Pre-cleaning: Mix hydrogen peroxide, ammonia and deionized water to remove residual organic matter on the surface of the silicon wafer.

[0055] (2) Alkali polishing: Mix potassium hydroxide with deionized water and use potassium hydroxide to dissolve the surface layer of both sides of the silicon wafer for a total of 5μm-25μm.

[0056] (3) Texturing: Mix potassium hydroxide, texturing additives and deionized water to form a surface covered with pyramids.

[0057] (4) Rounding: Mix hydrofluoric acid, ozone and deionized water to remove the peaks and valleys of the pyramid to make it round.

[0058] (5) Post-cleaning: Mix hydrogen peroxide, hydrochloric acid and deionized water to remove metal impurities remaining on the surface of the silicon wafer.

[0059] (6) Hydrophobicity: Mix hydrofluoric acid and deionized water, and use hydrofluoric acid to remove silicon oxide on the surface of the silicon wafer, so that a hydrophobic layer is formed on the surface of the silicon wafer.

[0060] (7) Soaking and rinsing: After steps 1-6, soak and rinse with deionized water.

[0061] (8) Drying: After step 6, use hot air to dry the silicon wafer.

[0062] Example 1:

[0063] A method for preparing a heterojunction battery includes the following steps.

[0064] Step 1: Provide a crystalline silicon layer; use an N-type Czochralski single crystal silicon wafer with a thickness of 150 μm, a resistivity of 3 Ω·cm, and a minority carrier lifetime of 2000 μs.

[0065] Step 2: Texturing and cleaning the crystalline silicon surface. A mixture of NaOH and a texturing additive is used to texturize the wafer. The wafer is then cleaned using standard RCA cleaning methods to remove surface contaminants. Next, a hydrofluoric acid solution is used to remove the surface oxide layer.

[0066] Step 3: Use PECVD process to deposit the first intrinsic amorphous silicon with a thickness of 6nm on the front of the crystalline silicon layer. The reaction gases are SiH4 and H2, where the flow ratio of H2 to SiH4 is 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure 70Pa, substrate temperature 200℃; then deposit a 6nm thick N-type doped amorphous silicon layer on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, with a flow ratio of H2 to SiH4 of 5 and a flow ratio of PH3 to SiH4 of 0.02. The power density of the PECVD equipment is 15mW / cm 2 , the pressure is 80Pa, and the substrate temperature is 200℃.

[0067] A second intrinsic amorphous silicon layer with a thickness of 7nm is deposited on the front of the crystalline silicon layer using the PECVD process. The reaction gases are SiH4 and H2, with a flow ratio of H2 to SiH4 of 5. The power density of the PECVD equipment is 20mW / cm 2, pressure of 70Pa, substrate temperature of 200℃; then, a 10nm thick P-type doped amorphous silicon layer was deposited on the second intrinsic amorphous silicon. The reaction gases were SiH4, B2H6, and H2, with a flow ratio of H2 to SiH4 of 4 and a flow ratio of B2H6 to SiH4 of 0.04. The power density of the PECVD equipment was 15mW / cm 2 , the pressure is 60Pa, and the substrate temperature is 200℃.

[0068] Step 4: Using PVD, a first transparent conductive layer with a thickness of 75 nm is deposited on the N-type doped amorphous silicon layer, and a second transparent conductive layer with a thickness of 75 nm is deposited on the P-type doped amorphous silicon layer. Both the first and second transparent conductive layers are ITO transparent conductive films, wherein the mass percentage of indium in the ITO is 90% and the mass percentage of tin is 10%. The PVD apparatus is filled with Ar and O2 at a flow rate ratio of O2 to Ar of 0.025, at a pressure of 0.5 Pa, and the substrate temperature is room temperature.

[0069] In step 5, a mask plate is placed on the surface of the first transparent conductive layer and the second transparent conductive layer respectively, and the opening pattern of the mask plate is consistent with the metal electrode pattern. The transparent conductive layer is locally cleaned and reduced by hydrogen plasma treatment to obtain a local reduction area with a relatively increased local carrier concentration. The width of the local reduction area is 30 μm; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and the second transparent conductive layer.

[0070] Step six, forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask plate, and the first metal electrode and the second metal electrode are located directly above the local reduction area.

[0071] Example 2:

[0072] A method for preparing a heterojunction battery includes the following steps.

[0073] Step 1: providing a crystalline silicon layer; using an N-type Czochralski-type single crystal silicon wafer with a thickness of 100 μm, a resistivity of 3 Ω·cm, and a minority carrier lifetime of 2000 μs.

[0074] Step 2: Texturing and cleaning the crystalline silicon surface. A mixture of NaOH and a texturing additive is used to texturize the wafer. The wafer is then cleaned using standard RCA cleaning methods to remove surface contaminants. Next, a hydrofluoric acid solution is used to remove the surface oxide layer.

[0075] Step 3: Use PECVD process to deposit a first intrinsic amorphous silicon with a thickness of 5nm on the front of the crystalline silicon layer. The reaction gases are SiH4 and H2, where the flow ratio of H2 to SiH4 is 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure 70Pa, substrate temperature 200℃; then deposit an 8nm thick N-type doped amorphous silicon layer on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, with a flow ratio of H2 to SiH4 of 5 and a flow ratio of PH3 to SiH4 of 0.02. The power density of the PECVD equipment is 15mW / cm 2 , the pressure is 80Pa, and the substrate temperature is 200℃.

[0076] A second intrinsic amorphous silicon layer with a thickness of 7nm is deposited on the front of the crystalline silicon layer using the PECVD process. The reaction gases are SiH4 and H2, with a flow ratio of H2 to SiH4 of 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure of 70Pa, substrate temperature of 200℃; then, a 10nm thick P-type doped amorphous silicon layer was deposited on the second intrinsic amorphous silicon. The reaction gases were SiH4, B2H6, and H2, with a flow ratio of H2 to SiH4 of 4 and a flow ratio of B2H6 to SiH4 of 0.04. The power density of the PECVD equipment was 15mW / cm 2 , the pressure is 60Pa, and the substrate temperature is 200℃.

[0077] Step 4: Using PVD, a first transparent conductive layer with a thickness of 100 nm is deposited on the N-type doped amorphous silicon layer, and a second transparent conductive layer with a thickness of 100 nm is deposited on the P-type doped amorphous silicon layer. Both the first and second transparent conductive layers are ITO transparent conductive films, wherein the mass percentage of indium in the ITO is 90% and the mass percentage of tin is 10%. The PVD apparatus is filled with Ar and O2 at a flow rate ratio of O2 to Ar of 0.025, at a pressure of 0.5 Pa, and the substrate temperature is room temperature.

[0078] In step five, a mask plate is placed on the surface of the first transparent conductive layer, the opening pattern of the mask plate is consistent with the metal electrode pattern, and hydrogen plasma treatment is used to locally clean and reduce the transparent conductive layer to obtain a local reduction area with a relatively increased local carrier concentration. The width of the local reduction area is 30 μm; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer.

[0079] Step six, forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode pattern of the first metal electrode is consistent with the opening pattern of the mask plate, and the first metal electrode is located directly above the local reduction area.

[0080] Example 3:

[0081] A method for preparing a heterojunction battery includes the following steps.

[0082] Step 1: Provide a crystalline silicon layer; use a P-type Czochralski single crystal silicon wafer with a thickness of 150 μm, a resistivity of 3 Ω·cm, and a minority carrier lifetime of 2000 μs.

[0083] Step 2: Texturing and cleaning the crystalline silicon surface. A mixture of NaOH and a texturing additive is used to texturize the wafer. The wafer is then cleaned using standard RCA cleaning methods to remove surface contaminants. Next, a hydrofluoric acid solution is used to remove the surface oxide layer.

[0084] Step 3: Use PECVD process to deposit a first intrinsic amorphous silicon with a thickness of 5nm on the front of the crystalline silicon layer. The reaction gases are SiH4 and H2, where the flow ratio of H2 to SiH4 is 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure 70Pa, substrate temperature 200℃; then deposit an 8nm thick N-type doped amorphous silicon layer on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, with a flow ratio of H2 to SiH4 of 5 and a flow ratio of PH3 to SiH4 of 0.02. The power density of the PECVD equipment is 15mW / cm 2 , the pressure is 80Pa, and the substrate temperature is 200℃.

[0085] A second intrinsic amorphous silicon layer with a thickness of 7nm is deposited on the front of the crystalline silicon layer using the PECVD process. The reaction gases are SiH4 and H2, with a flow ratio of H2 to SiH4 of 5. The power density of the PECVD equipment is 20mW / cm 2 , pressure 70Pa, substrate temperature 200℃; then deposit a 10nm thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, the reaction gases are SiH4, B2H6 and H2, where the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of the PECVD equipment is 15mW / cm 2 , the pressure is 60Pa, and the substrate temperature is 200℃.

[0086] Step 4: Using PVD, a first transparent conductive layer with a thickness of 100 nm is deposited on the N-type doped amorphous silicon layer, and a second transparent conductive layer with a thickness of 100 nm is deposited on the P-type doped amorphous silicon layer. Both the first and second transparent conductive layers are ITO transparent conductive films, wherein the mass percentage of indium in the ITO is 90% and the mass percentage of tin is 10%. The PVD apparatus is filled with Ar and O2 at a flow rate ratio of O2 to Ar of 0.025, at a pressure of 0.5 Pa, and the substrate temperature is room temperature.

[0087] Step 5: Place a mask plate on the surface of the second transparent conductive layer. The opening pattern of the mask plate is consistent with the metal electrode pattern. Use hydrogen plasma treatment to locally clean and reduce the transparent conductive layer to obtain a local reduction area with a relatively increased local carrier concentration. The width of the local reduction area is 30 μm; the carrier concentration of the local reduction layer is higher than that of the second transparent conductive layer.

[0088] Step six, forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode pattern of the second metal electrode is consistent with the mask plate opening pattern, and the second metal electrode is located directly above the local reduction area.

[0089] The use of this application has the following beneficial effects.

[0090] (1) By forming a local reduction zone on the surface of the transparent conductive layer below the low-temperature metal paste electrode, the local carrier concentration of the transparent conductive layer is increased, and the interface barrier height between the transparent conductive layer and the low-temperature metal paste electrode is reduced, thereby obtaining a lower contact resistance; in addition, the surface after local treatment is cleaner and will not be affected by the adsorption of water vapor, oxygen, and organic matter.

[0091] (2) A mask plate is placed on the surface of the transparent conductive layer, the opening pattern of the mask plate is consistent with the metal electrode pattern, and then hydrogen plasma treatment is used to locally clean and reduce the transparent conductive layer to obtain a local reduction layer with a relatively increased local carrier concentration.

[0092] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A heterojunction battery, characterized in that: including a crystalline silicon layer, The front surface of the crystalline silicon layer is provided with a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer and a first metal electrode in sequence from the inside to the outside, and, The back side of the crystalline silicon layer is provided with a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conductive layer and a second metal electrode in sequence from the inside to the outside, wherein: A local reduction layer is formed on the surface of the first transparent conductive layer located below the first metal electrode and / or on the surface of the second transparent conductive layer located below the second metal electrode, and, The carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and / or the second transparent conductive layer.

2. A heterojunction battery according to claim 1, wherein: The width of the local reduction layer is 5 μm-50 μm.

3. A heterojunction battery according to claim 1, wherein: The crystalline silicon layer is selected from N-type doped single crystal silicon, N-type doped analog single crystal silicon, P-type doped single crystal silicon or P-type doped analog single crystal silicon, and the thickness of the crystalline silicon layer is 50 μm-250 μm.

4. A heterojunction battery according to claim 1, wherein: The first intrinsic amorphous silicon layer is a composite thin film layer formed by stacking undoped amorphous silicon semiconductor film, amorphous silicon oxide semiconductor film, amorphous silicon carbide semiconductor film or a combination thereof. The thickness of the first intrinsic amorphous silicon layer is 2nm-8nm.

5. The heterojunction battery according to claim 1, wherein: The N-type doped amorphous silicon layer is a composite thin film layer of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor thin films or a combination thereof, and the thickness of the N-type doped amorphous silicon layer is 4nm-30nm.

6. The heterojunction battery according to claim 1, wherein: The P-type doped amorphous silicon layer is a composite thin film layer of P-type doped amorphous silicon semiconductor film, amorphous silicon oxide semiconductor film, amorphous silicon carbide semiconductor film, microcrystalline silicon semiconductor film, microcrystalline silicon oxide semiconductor film, microcrystalline silicon carbide semiconductor film or a combination thereof, and the thickness of the P-type doped amorphous silicon layer is 4nm-30nm.

7. The heterojunction battery according to claim 1, wherein: The first transparent conductive layer is a composite thin film layer of doped indium oxide, zinc oxide or tin oxide or a combination thereof, and the thickness of the first transparent conductive layer is 70 nm-120 nm.

8. The heterojunction battery according to claim 1, wherein: The second transparent conductive layer is a composite thin film layer of doped indium oxide, zinc oxide or tin oxide or a combination thereof, and the thickness of the second transparent conductive layer is 70 nm-120 nm.

9. The heterojunction battery according to claim 7, wherein: The first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films, the mass percentage of indium element in the first transparent conductive layer and the second transparent conductive layer is 90%, and the mass percentage of tin element in the first transparent conductive layer and the second transparent conductive layer is 10%.

10. The heterojunction battery according to claim 1, wherein: The first metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof. The thickness of the first metal electrode is 10 μm-50 μm, and the width of the first metal electrode is 5 μm-50 μm.

11. The heterojunction battery according to claim 1, wherein: The second metal electrode is a low-temperature metal paste electrode composed of Ag, Cu, Al, Ni or a combination thereof. The thickness of the second metal electrode is 10 μm-50 μm, and the width of the second metal electrode is 5 μm-50 μm.

12. A method for preparing a heterojunction battery, characterized in that: The steps include: Step 1, providing a crystalline silicon layer; Step 2: texturing the surface of the crystalline silicon layer and cleaning the surface of the crystalline silicon layer; Step 3: depositing a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer in sequence on the front surface of the crystalline silicon layer obtained in step 2, and depositing a second intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer in sequence on the back surface of the crystalline silicon layer obtained in step 2; Step 4: depositing a first transparent conductive layer on the N-type doped amorphous silicon layer obtained in step 3, and depositing a second transparent conductive layer on the P-type doped amorphous silicon layer obtained in step 3; Step 5: placing a mask on the surface of the first transparent conductive layer and / or the second transparent conductive layer, and locally cleaning and reducing the transparent conductive layer using hydrogen plasma treatment to obtain a local reduced area with a relatively increased local carrier concentration, wherein the width of the local reduced area is within a range of 5 μm to 50 μm; and Step six, forming a first metal electrode on the first transparent conductive layer by screen printing, and forming a second metal electrode on the second transparent conductive layer by screen printing; wherein the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask plate, and the first metal electrode and / or the second metal electrode are located directly above the local reduction area.

13. The method for preparing a heterojunction battery according to claim 12, wherein: The width of the local reduction zone is in the range of 30 μm to 50 μm.

14. The method for preparing a heterojunction battery according to claim 12, wherein: Depositing the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer in sequence on the front surface of the crystalline silicon layer obtained in step 2 by a PECVD method, and depositing the second intrinsic amorphous silicon layer and the P-type doped amorphous silicon layer in sequence on the back surface of the crystalline silicon layer obtained in step 2; and A first transparent conductive layer is deposited on the N-type doped amorphous silicon layer obtained in step three by using a PVD method, and a second transparent conductive layer is deposited on the P-type doped amorphous silicon layer obtained in step three.

15. A photovoltaic module, characterized in that: Comprising a heterojunction battery as described in any one of claims 1 to 11.

Images