Built-in Synchronizer Clock Gating for Low Power Consumption

Abstract

A digital circuit includes a first digital system operating in a first domain, a second digital system operating in a second domain, and a synchronizer for synchronizing data transfer operations across a domain boundary between the first and second domains. The synchronizer generates a synchronous output signal for the second digital system from an asynchronous input signal. The synchronizer includes a clock gating logic and a synchronizer flop bank comprising multiple synchronization flip flops. The clock gating logic receives the asynchronous input signal, the synchronous output signal, and a clock signal, and adaptively gates the clock signal according to the synchronous input signal and the synchronous output signal. The synchronizer flop bank receives the asynchronous input signal and the clock signal to generate the synchronous output signal, where the clock signal is adaptively gated by the clock gating logic. 20 25 21 74 12 18 A ug 2 02 5 A u g 2 0 2 5 A B S T R A C T 2 0 2 5 2 1 7 4 1 2 1 8 FIG. 1 1 / 4 Q CLK D Q CLK D Q CLK CG Latch en clk out D RSTN CLK LEVEL_ASYNC LEVEL_SYNC FIG. 2 Q CLK D Q CLK D Q CLK CG Latch en clk out D RST_ASYNC CLK RST_SYNC 0 10 20 102 104 106 108 110 112 202 204 206 208 210 1 / 4 10 108 110 112 / / / D Q D Q D Q LEVEL_SYNC 102 106 104 / CLK CLK CLK LEVEL_ASYNC en CG out Latchclk CLK RSTN FIG. 1 20 206 208 210 / / 0 D Q D Q D Q RST_SYNC 202 204 / CLK CLK CLK en CG out Latch CLK clk RST_ASYNC FIG. 2 20 25 21 74 12 18 A ug 2 02 5 1 / 4 1 0 2 0 2 5 2 1 7 4 1 2 1 8 A u g 2 0 2 5 1 0 8 1 1 0 1 1 2 D Q Q D Q 1 0 2 1 0 6 C G c l k R S T N 2 0 6 2 0 8 2 1 0 / / 0 D Q D Q 2 0 2 2 0 4 / C L K e n C G c l k C L K F I G . 2

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