Solar cell manufacturing method, solar cell, and photovoltaic module

Abstract

Disclosed are a solar cell manufacturing method, a solar cell, and a photovoltaic module. The manufacturing method comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface which are oppositely arranged, and the second surface comprises first regions and second regions which are distributed at intervals; forming a tunneling layer and a second doping layer, which are stacked, on the first regions; preparing a second passivation layer on the second regions and the second doping layer, wherein the second passivation layer is in contact with the silicon substrate on the second regions; and preparing, on the first regions, second electrodes in contact with the second doping layer.

Description

Solar cell manufacturing method, solar cell and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application with application number 202411841552.5, entitled “Solar cells and photovoltaic modules”, filed with the State Intellectual Property Office of China on December 13, 2024, the Chinese patent application with application number 202410377188.5, entitled “Method for preparing solar cells”, filed with the State Intellectual Property Office of China on March 29, 2024, the Chinese patent application with application number 202411841551.0, entitled “Method for preparing solar cells”, filed with the State Intellectual Property Office of China on December 13, 2024, and the Chinese patent application with application number 202410522507.7, entitled “Method for preparing solar cells”, filed with the State Intellectual Property Office of China on April 28, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure belongs to the technical field of solar cells, and particularly relates to a method for preparing a solar cell, a solar cell, and a photovoltaic module. Background Art

[0004] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international markets are constantly increasing, leading industry manufacturers to focus on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells, by sequentially depositing an ultra-thin tunnel oxide layer and a doped polysilicon layer on the back of a silicon substrate, improve the cell's surface passivation performance, reduce the metal contact recombination current, and effectively increase the cell's open-circuit voltage and short-circuit current. In recent years, TOPCon cells have rapidly increased their market share, gradually surpassing PERC (Passivated Emitter Rear Cell) cells to become the mainstream technology for solar cells.

[0005] TOPCon cells have excellent passivation and conductivity properties for both n+ and p+ polarities, are compatible with traditional industrial production, and have broad development prospects. With the continuous optimization of TOPCon cells, parasitic absorption of the rear polysilicon layer (poly) has become the primary factor limiting the improvement of TOPCon cell efficiency and bifaciality.

[0006] In TOPCon cells, the back polysilicon layer is doped with phosphorus to form a doped polysilicon layer (N+Poly), which has three main functions: 1. Providing a field passivation effect; 2. As a phosphorus-rich layer, it greatly improves the contact on the back; 3. It isolates the direct contact between the Ag metal and the silicon substrate, reducing metal recombination. In addition to the above advantages, the parasitic absorption of the polysilicon layer is its biggest disadvantage. Parasitic absorption refers to an optical absorption mechanism that does not generate electron-hole pairs in the silicon body, thereby reducing the utilization rate of light. In order to reduce the recombination of the Ag metal area on the back, the thickness of the polysilicon layer is generally greater than 100nm. Reducing the thickness of the polysilicon layer while ensuring that the passivation of the metal area is not lost has become the main optimization direction of TOPCon cells.

[0007] Therefore, in order to solve the above technical problems, it is necessary to provide a method for preparing a solar cell, a solar cell and a photovoltaic module.

[0008] Public content

[0009] The first object of the present disclosure is to provide a method for preparing a solar cell to improve the conversion efficiency and bifaciality of the cell.

[0010] A second objective of the present disclosure is to provide a solar cell.

[0011] A third objective of the present disclosure is to provide a photovoltaic module.

[0012] According to an embodiment of the first aspect of the present disclosure, a method for preparing a solar cell includes the following steps: providing a silicon substrate, wherein the silicon substrate includes a first surface and a second surface arranged opposite to each other, and the second surface includes a first region and a second region distributed at intervals; forming a stacked tunneling layer and a second doping layer on the first region; preparing a second passivation layer on the second region and the second doping layer, wherein the second passivation layer is in contact with the silicon substrate on the second region; and preparing a second electrode in contact with the second doping layer on the first region.

[0013] In one embodiment, a stacked tunneling layer and a second doping layer are formed on the first region, including: sequentially preparing the tunneling layer, the second doping layer and a mask on the second surface; removing the mask on the second region; and removing the second doping layer and the tunneling layer on the second region, and retaining the tunneling layer and the second doping layer on the first region.

[0014] In one embodiment, a laser opening process is used to remove the mask on the second region; and a chemical etching process is used to remove the second doping layer and the tunneling layer on the second region.

[0015] In one embodiment, the tunneling layer, the second doping layer and the mask are prepared in sequence on the second surface, including: depositing the tunneling layer, the doped amorphous silicon layer and the mask in sequence on the second surface of the silicon substrate; annealing the silicon substrate on which the tunneling layer, the doped amorphous silicon layer and the mask are deposited to transform the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0016] In one embodiment, the preparation method further includes: preparing a light trapping structure on the first surface and the second surface of the silicon substrate through a texturing process; and / or polishing the second surface of the silicon substrate before preparing the tunneling layer, the second doping layer and the mask.

[0017] In one embodiment, a stacked tunneling layer and a second doping layer are formed on the first region, including: sequentially preparing the tunneling layer and the second doping layer on the second surface; processing the second doping layer on the first region to crystallize the second doping layer on the first region, and forming an oxide layer on the surface of the second doping layer on the first region, wherein the oxide layer is used as a mask; and removing the second doping layer and the tunneling layer on the second region, and removing the oxide layer on the first region, retaining the tunneling layer and the second doping layer on the first region.

[0018] In one embodiment, the second doped layer on the first region is processed by a laser process, and the second doped layer and the tunneling layer on the second region and the oxide layer on the first region are removed by a chemical etching process.

[0019] In one embodiment, the second doped layer before the laser process is a doped amorphous silicon layer. The laser process crystallizes the doped amorphous silicon layer on the first region, converting the doped amorphous silicon layer into a doped polycrystalline silicon layer. At the same time, a silicon oxide layer is formed on the surface of the second doped layer on the first region, and the silicon oxide layer is used as the mask.

[0020] In one embodiment, the chemical etching process includes: using the silicon oxide layer as the mask to remove the entire doped amorphous silicon layer on the second region, and then removing the tunneling layer on the second region and the silicon oxide layer on the first region.

[0021] In one embodiment, the preparation method further includes: preparing a light trapping structure on the first surface and the second surface of the silicon substrate through a texturing process; and / or polishing the second surface of the silicon substrate before preparing the tunneling layer and the second doping layer.

[0022] According to the solar cell embodiment of the second aspect of the present disclosure, the solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface arranged opposite to each other, the second surface includes a first region and a second region distributed at intervals, the first region is provided with a tunneling layer directly in contact with the silicon substrate, a second doping layer arranged on the tunneling layer, and a second electrode, the second region is provided with a second passivation layer in contact with the second surface of the silicon substrate, and the second electrode is in contact with the second doping layer.

[0023] In one embodiment, the second passivation layer extends onto the first region and covers the tunneling layer and the second doped layer.

[0024] In one embodiment, the second passivation layer is an aluminum oxide passivation layer with a thickness of 2 nm to 7 nm, 3 nm to 6 nm, or 3 nm to 5 nm.

[0025] In one embodiment, a second anti-reflection layer is stacked on the second passivation layer. The second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

[0026] In one embodiment, the doping type of the second doping layer is the same as the doping type of the silicon substrate, the silicon substrate is an N-type silicon substrate, and the second doping layer is an N-type doped polysilicon layer; and / or the surface doping concentration of the second doping layer is 1E20cm -3 ~1E21cm -3 , the thickness is 1nm~150nm or 50nm~100nm or 80nm~100nm.

[0027] In one embodiment, the tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0028] In one embodiment, a first doping layer and a first electrode are formed on the first surface of the silicon substrate. The doping type of the first doping layer is opposite to that of the silicon substrate. The first electrode is in contact with the first doping layer.

[0029] In one embodiment, a first passivation layer and / or a first anti-reflection layer is stacked on the first doped layer; the first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; and / or the first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0030] In one embodiment, the first region includes a plurality of first sub-regions distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

[0031] The photovoltaic assembly according to the embodiment of the third aspect of the present disclosure includes a solar cell prepared by the preparation method described above or the solar cell described above.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention prepares a mask on the back of a silicon substrate and uses a laser to pattern the film, and then uses chemical etching to remove the polysilicon layer in the non-metallic area on the back, thereby improving the short-circuit current of the battery and thus improving the conversion efficiency and bifaciality of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some of the embodiments described in the present disclosure. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0036] FIG1 is a schematic structural diagram of a solar cell in Example 1 of the present disclosure;

[0037] FIG2 is a schematic diagram of the local structure of point A in FIG1 ;

[0038] FIG3 is a schematic plan view of the second surface of the silicon substrate in Example 1 of the present disclosure;

[0039] FIG4 is a plan view of the second surface and the second electrode in Example 1 of the present disclosure;

[0040] 5a to 5j are flow charts of a manufacturing process of a solar cell in Example 1 of the present disclosure;

[0041] FIG6 is a schematic diagram of a laser pattern in the laser film opening process in Example 1 of the present disclosure;

[0042] FIG7 is a surface topography image of the second region on the silicon substrate after the chemical etching process in Example 1 of the present disclosure;

[0043] 8a to 8c are process flow charts for preparing a first doping layer on the first surface of a silicon substrate in Example 2 of the present disclosure;

[0044] 9a to 9j are flow charts of another process for preparing a solar cell in Example 3 of the present disclosure;

[0045] FIG10 is a schematic diagram of a laser scanning pattern in the laser process in Example 3 of the present disclosure;

[0046] FIG11 is a schematic structural diagram of a solar cell in Example 5 of the present disclosure;

[0047] FIG12 is a schematic diagram of the local structure of point B in FIG11 .

[0048] Explanation of main figure marks: 10. Substrate, 11. First doped layer, 11', boron-doped amorphous silicon layer, 21. First passivation layer, 31. First anti-reflection layer, 12. Tunneling layer, 13. Second doped layer, 131. Oxide layer, 22. Second passivation layer, 32. Second anti-reflection layer, 41. First electrode, 42. Second electrode, 421. Auxiliary gate line, 50. Mask, S1. First surface, S2. Second surface, S21. First region, S22. Second region, 101. First sub-region, 102. Second sub-region. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0050] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0051] The first aspect of the present disclosure discloses a method for preparing a solar cell, comprising the following steps:

[0052] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface disposed opposite to each other, the second surface comprising a first region and a second region spaced apart;

[0053] forming a stacked tunneling layer and a second doping layer on the first region;

[0054] forming a second passivation layer on the second region and the second doped layer, wherein the second passivation layer contacts the silicon substrate on the second region; and

[0055] A second electrode is formed on the first region and contacts the second doping layer.

[0056] In one embodiment, a stacked tunneling layer and a second doping layer are formed on a first region, including: sequentially preparing a tunneling layer, a second doping layer, and a mask on the second surface; removing the mask on the second region; and removing the second doping layer and the tunneling layer on the second region, while retaining the tunneling layer and the second doping layer on the first region.

[0057] In one embodiment, a laser opening process is used to remove the mask on the second region; and a chemical etching process is used to remove the second doping layer and the tunneling layer on the second region.

[0058] In one embodiment, a tunneling layer, a second doped layer, and a mask are sequentially prepared on the second surface, including: sequentially depositing a tunneling layer, a doped amorphous silicon layer, and a mask on the second surface of a silicon substrate; and annealing the silicon substrate on which the tunneling layer, the doped amorphous silicon layer, and the mask are deposited to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer.

[0059] In one embodiment, the preparation method further includes: preparing a light trapping structure on the first surface and the second surface of the silicon substrate through a texturing process; and / or polishing the second surface of the silicon substrate before preparing the tunneling layer, the second doping layer and the mask.

[0060] In one embodiment, a stacked tunneling layer and a second doping layer are formed on a first region, including: sequentially preparing a tunneling layer and a second doping layer on a second surface; processing the second doping layer on the first region to crystallize the second doping layer on the first region, and forming an oxide layer on the surface of the second doping layer on the first region, wherein the oxide layer is used as a mask; and removing the second doping layer and the tunneling layer on the second region, and removing the oxide layer on the first region, retaining the tunneling layer and the second doping layer on the first region.

[0061] In one embodiment, the second doped layer on the first region is processed by a laser process, and the second doped layer and the tunneling layer on the second region and the oxide layer on the first region are removed by a chemical etching process.

[0062] In one embodiment, the second doped layer before laser processing is a doped amorphous silicon layer. The laser process crystallizes the doped amorphous silicon layer on the first region, converting the doped amorphous silicon layer into a doped polycrystalline silicon layer. At the same time, a silicon oxide layer is formed on the surface of the second doped layer on the first region, and the silicon oxide layer is used as a mask.

[0063] In one embodiment, the chemical etching process includes: using the silicon oxide layer as a mask to remove the entire doped amorphous silicon layer on the second region, and then removing the tunneling layer on the second region and the silicon oxide layer on the first region.

[0064] In one embodiment, the preparation method further includes: preparing a light trapping structure on the first surface and the second surface of the silicon substrate by a texturing process; and / or polishing the second surface of the silicon substrate before preparing the tunneling layer and the second doping layer.

[0065] Specifically, a method for preparing a solar cell is as follows:

[0066] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the second surface comprising a first region and a second region;

[0067] Prepare a tunneling layer, a second doping layer and a mask stacked in sequence on the second surface;

[0068] Using a laser film opening process to remove the mask on the second area;

[0069] Using a chemical etching process, the second doping layer on the second region is removed, and the tunneling layer and the second doping layer on the first region are retained;

[0070] A second electrode is formed on the first region and contacts the second doping layer.

[0071] Furthermore, the preparation method further comprises:

[0072] forming a first doping layer on the first surface, the first doping layer having a doping type opposite to that of the second doping layer; and

[0073] A first electrode is prepared on the first surface and in contact with the first doping layer.

[0074] Therefore, the present invention can improve the short-circuit current of the battery by preparing a mask on the back of the silicon substrate and patterning the film with a laser, and then using chemical etching to remove the polysilicon layer in the non-metallic area on the back, thereby improving the conversion efficiency and bifaciality of the battery.

[0075] Another method for preparing a solar cell is:

[0076] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the second surface comprising a first region and a second region;

[0077] preparing a tunneling layer and a second doping layer stacked in sequence on the second surface;

[0078] The second doped layer on the first region is processed by a laser process to crystallize the second doped layer on the first region and form an oxide layer on the surface of the second doped layer on the first region;

[0079] Using a chemical etching process, remove at least a portion of the second doped layer on the second region and the oxide layer on the first region, and retain the tunneling layer and the second doped layer on the first region;

[0080] A second electrode is formed on the first region and contacts the second doping layer.

[0081] Furthermore, the preparation method further comprises:

[0082] forming a first doping layer on the first surface, wherein the doping type of the first doping layer is opposite to the doping type of the silicon substrate; and

[0083] A first electrode in contact with the first dopant is formed on the first surface.

[0084] Therefore, the present invention uses a laser process to oxidize the back metal area to form an oxide layer, and uses the instantaneous high temperature of the laser to crystallize the doped layer, and then uses a chemical etching process to remove the doped layer in the back non-metallic area using the oxide layer as a mask. This can take into account both the passivation effect and the reduction of parasitic absorption, significantly improving the cell efficiency and bifaciality while improving the process window.

[0085] The second aspect of the present disclosure discloses a solar cell, including a silicon substrate, the silicon substrate including a first surface and a second surface arranged opposite to each other, the second surface including a first region and a second region distributed at intervals, a tunneling layer directly in contact with the silicon substrate and a second doping layer and a second electrode arranged on the tunneling layer are provided on the first region, and a second passivation layer in contact with the second surface of the silicon substrate is provided on the second region.

[0086] A third aspect of the present disclosure discloses a photovoltaic module, comprising a solar cell prepared according to the preparation method of any embodiment of the first aspect or a solar cell of any embodiment of the second aspect.

[0087] The non-metallic area on the back of the solar cell disclosed in the present invention is not protected by the tunneling layer and the second doping layer. The passivation performance of the back of the cell can be guaranteed by the second passivation layer. In addition, the second passivation layer has a certain blocking effect on the back slurry, preventing the slurry from burning through the second doping layer, thereby allowing the second doping layer to be further thinned, thereby improving the short-circuit current density of the cell without affecting the metallization contact performance, and significantly improving the cell efficiency and bifaciality.

[0088] The present disclosure is further described below with reference to specific embodiments.

[0089] Example 1:

[0090] Figure 1 is a schematic structural diagram of the solar cell in this embodiment, which is a TOPCon cell, including a silicon substrate 10. As shown in Figure 5a, the silicon substrate 10 includes a first surface S1 and a second surface S2 arranged opposite to each other, and the second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first region S21 is a back metal region, and the second region S22 is a back non-metal region.

[0091] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and has a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0092] Furthermore, a light-trapping structure is formed on the first surface S1 of the silicon substrate 10. For example, a pyramid velvet structure can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, and the pyramid size is 0.5μm to 3μm. The second surface S2 of the silicon substrate 10 is a polished surface. The polished surface can be the surface of the light-trapping structure after chemical polishing, or the surface of the back side of the original silicon substrate after direct chemical polishing. For example, in this embodiment, a pyramid velvet structure can be formed on the second surface S2 of the silicon substrate 10 by alkali texturing, and the pyramid size is 0.5μm to 3μm. The back side is then subjected to alkali polishing to obtain a polished surface. Compared with the back side of a conventional silicon substrate, a plurality of tower bases will be formed on the polished surface (the tower base is the base left after the pyramid velvet structure is polished).

[0093] In this embodiment, a first doped layer 11 is formed on the first surface S1 of the silicon substrate 10 by a diffusion process, thereby forming a PN junction, which generates minority carrier-hole pairs after exposure to light. Exemplarily, the first doped layer 11 is a P-type doped layer (i.e., a P+ emitter) formed by a boron doping process. For example, it is formed below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) by a boron doping process, and the surface doping concentration is 3E18cm -3 ~3E19cm -3 , square resistance is 250Ω / sq~300Ω / sq, preferably 250Ω / sq~280Ω / sq.

[0094] As shown in FIG1 and in conjunction with FIG2 , in this embodiment, the tunneling layer 12 and the second doped layer 13 are provided only in the first region S21 on the second surface S2 of the silicon substrate 10, while no tunneling layer or second doped layer is provided in the second region S22. In other words, the tunneling layer 12, which is in direct contact with the silicon substrate 10, and the second doped layer 13 provided on the tunneling layer 12 are formed only in the first region S21.

[0095] As shown in FIG2 , in this embodiment, a tunneling layer 12 and a second doped layer 13 are sequentially stacked on a first region S21 on the second surface S2 of the silicon substrate 10. For example, the projections of the tunneling layer 12 and the second doped layer 13 on the second surface S2 of the silicon substrate 10 are located within the first region S21. The tunneling layer 12 directly contacts the second surface S2 of the silicon substrate 10 in the first region S21. The tunneling layer 12 can provide good interface passivation in the first region S21, while the second doped layer 13 can provide field passivation. Furthermore, due to the high doping concentration of these layers, they can improve contact and reduce resistance.

[0096] The tunneling layer 12 is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1 nm to 3 nm, and more preferably 1.5 nm to 2.5 nm; the second doping layer 13 is a phosphorus-doped N-type doped polysilicon layer with a surface doping concentration of 1E20 cm -3 ~1E21cm -3 , preferably 2E20cm -3 ~3E21cm -3 , more preferably 5E20cm -3 ~2E21cm -3 The thickness of the second doping layer 13 is 1 nm to 120 nm, preferably 1 nm to 150 nm, more preferably 50 nm to 100 nm, and even more preferably 80 nm to 100 nm. The thickness of the second doping layer 13 of this embodiment is further reduced, which can reduce parasitic absorption without affecting the metallization contact performance, increase the short-circuit current density of the battery, and significantly improve the battery efficiency and bifaciality.

[0097] Preferably, in this embodiment, a first passivation layer 21 and a first anti-reflection layer 31 are sequentially stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second anti-reflection layer 32 are sequentially stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second anti-reflection layer 32 cover the second doped layer 13 and extend into the second region S22. In the second region S22, the second passivation layer 22 is in direct contact with the silicon substrate 10. The first passivation layer 21 can provide excellent field passivation and chemical passivation effects, the second passivation layer 22 can provide a chemical passivation effect, and the first anti-reflection layer 31 can reduce reflectivity and increase light utilization.

[0098] Exemplarily, the first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm, and the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 5nm; the first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm, preferably a silicon nitride layer. Silicon nitride is chemically inactive and has strong resistance to acid and alkali corrosion, which can reduce the battery's sensitivity to the environment.

[0099] In addition, the first electrode 41 in this embodiment is located on the first surface S1 of the silicon substrate 10 and contacts the first doped layer 11, and the second electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically on the first area S21 in the second surface S2, and contacts the second doped layer 13.

[0100] As shown in FIG3 , the first region S21 in this embodiment includes a plurality of parallel, evenly spaced first sub-regions 101, and the second region S22 includes a plurality of parallel, evenly spaced second sub-regions 102, with the first sub-regions 101 and the second sub-regions 102 being arranged alternately. The width of the first sub-regions 101 is smaller than the width of the second sub-regions 102; for example, the ratio of the widths of the first sub-regions 101 to the width of the second sub-regions 102 can be 1:(5-20). Preferably, the first region S21 occupies approximately 10% of the area of ​​the entire second surface S2.

[0101] 4 , the second electrode 42 is a gate line electrode, which includes at least a plurality of parallel secondary gate lines 421, and the width of the first sub-region 101 is greater than or equal to the width of the secondary gate lines 421. Optionally, the second electrode 42 may further include a plurality of main gate lines (not shown) that are perpendicular to the secondary gate lines 421.

[0102] In this embodiment, taking a 210TOPCon cell as an example, the size is 203.396±15mm, there are 230 secondary grid lines 421, the width is 15μm to 100μm, and the spacing between adjacent secondary grid lines 421 is 0.907±0.015mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent secondary grid lines 421. Each first sub-region 101 is distributed with a secondary grid line 421, and the width of the first sub-region 101 is greater than the width of the secondary grid lines 421. The width of the first sub-region 101 is 50μm to 150μm. For example, if the width of the secondary grid line 421 is 40μm, the width of the first sub-region 101 is 80μm.

[0103] In this embodiment, the tunneling layer and doped polysilicon layer on the first region S21 can ensure a passivation effect, while the second passivation layer is formed in the second region S22, thereby ensuring a good passivation effect in the second region S22. In addition, the second passivation layer 22 has a certain barrier effect on the back surface paste, so the thickness of the second doped layer 13 is further reduced, thereby improving the short-circuit current density of the battery.

[0104] It should be understood that the second passivation layer 22 in this embodiment covers the entire second surface S2 of the silicon substrate 10, and is directly stacked on the silicon substrate surface in the second region S22, and is also stacked on the second doped layer 13 in the first region S21. In other embodiments, the second passivation layer 22 on the first region S21 and the second region S22 can also be passivation layers of different materials, that is, the passivation layers are separately deposited on the first region S21 and the second region S22; in addition, since the first region S21 has the tunneling layer 12 in direct contact with the silicon substrate 10 and the second doped layer 13 provided on the tunneling layer 12, the second passivation layer 22 can be stacked only on the second region S22.

[0105] The method for preparing a solar cell in this embodiment specifically includes the following steps:

[0106] 1. Double-sided velveting

[0107] As shown in Figure 5a, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 arranged opposite to each other. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first region S21 is a back metal region, and the second region S22 is a back non-metal region.

[0108] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. Referring to FIG. 5 b , a pyramid texture structure (not shown) is formed on the first surface S1 and the second surface S2 of the silicon substrate 10 by an alkali texturing process. The pyramid size is 0.5 μm to 3 μm.

[0109] 2. Boron Diffusion

[0110] As shown in FIG5c, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process, for example, by using a boron source (e.g., BCl3 or BBr3) for deposition and propulsion in a high-temperature furnace tube, and forming a layer of silicon oxide on the outer layer. After diffusion, the surface doping concentration of the first doping layer 11 is 3E18cm -3 ~3E19cm -3The square resistance is 250Ω / sq to 300Ω / sq, preferably 250Ω / sq to 280Ω / sq. During the boron diffusion process, a BSG (Buried Contact Solar Cell) (not shown) is formed on the second surface S2 of the silicon substrate 10 .

[0111] For example, in this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is converted into a boron diffusion layer. The total thickness of the silicon substrate 10 and the first doped layer 11 after boron diffusion in FIG5c is equal to the thickness of the silicon substrate 10 before boron diffusion in FIG5b.

[0112] 3. Back polishing

[0113] As shown in FIG5d, the silicon substrate 10 after boron diffusion is first passed through a single-sided chain device to remove the back silicon oxide using a hydrofluoric acid solution, and then the back side is alkaline polished to remove the edge junction and back side wrap (BSG), and finally cleaned.

[0114] 4. Preparation of back-side tunneling passivation structure

[0115] As shown in FIG. 5 e , a tunneling layer 12 , a second doping layer 13 and a mask 50 stacked in sequence are prepared on the second surface S2 .

[0116] For example, in this embodiment, the PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used to first deposit a silicon oxide tunneling layer with a thickness of 1nm to 3nm on the back side, and then deposit a phosphorus-doped amorphous silicon layer or multiple phosphorus-doped amorphous silicon layers with different doping concentrations, with a total thickness of 1nm to 120nm, preferably 80nm to 100nm, and finally deposit a silicon oxide mask with a mask thickness of 2nm to 50nm, preferably 15nm to 20nm.

[0117] 5. Annealing activation

[0118] Annealing treatment is performed in a high-temperature annealing furnace at a temperature of 880°C to 980°C, preferably 900°C to 950°C. After annealing, the phosphorus-doped amorphous silicon layer is transformed into a phosphorus-doped polysilicon layer. Phosphorus is activated by annealing to form a tunneling layer 12 and a second doped layer 13 on the back side.

[0119] 6. Laser film opening

[0120] As shown in FIG. 5 f , the mask 50 on the second region S22 is removed by using a laser opening process.

[0121] After annealing, the back structure of the silicon substrate 10 is a tunneling layer (SiO2) + doped polysilicon layer (N+poly) + mask (SiO2). The laser processing mainly acts on the mask (SiO2) 50. For a silicon oxide mask with a thickness of 15nm to 20nm, the laser power in the laser opening process is 45W to 55W, preferably 50W, the scanning speed is 40000mm / s to 60000mm / s, preferably 50000mm / s, and the laser frequency is 500KHz to 600KHz, preferably 500KHz.

[0122] Figure 6 shows the laser pattern during the laser film opening process in this embodiment. The black lines correspond to the metal area, namely the first area S21, and the blank area is the laser scanning area, namely the second area S22. In conjunction with Figure 3, the laser scanning area is the second area S22 (i.e., the non-metallic area on the back). The laser film opening process removes the mask 50 on the second area S22, exposing the doped polysilicon layer underneath.

[0123] It should be understood that the laser patterns in the present disclosure can be designed according to different electrode structures, so that the mask in the laser scanning area (i.e., the non-metallic area on the back) is removed and the mask in the metal area on the back is retained. The laser patterns for other electrode structures will not be given one by one here.

[0124] 7. De-plating and chemical etching

[0125] As shown in FIG5g , this step specifically includes:

[0126] Pickling 1: For example, an acid solution is used in an acid pickling tank to remove the mask 50 formed around the edge of the silicon substrate 10. The mass fraction of the acid solution is 5% to 30%, and the treatment time is 30s to 100s, preferably 60s. For example, in this step, the front side of the silicon substrate 10 is passed through a chain hydrofluoric acid tank to remove the silicon oxide mask formed around the edge of the silicon substrate 10 on a single side.

[0127] Alkali etching: For example, an alkaline solution is used in an alkaline cleaning tank to remove the second doping layer 13 on the second region S22 . The mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s.

[0128] Pickling 2: For example, using an acid solution in an acid pickling tank to remove the tunneling layer 12 on the second region S22 and the mask 50 on the first region S21 , the mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s;

[0129] Finally, RCA cleaning is performed. RCA cleaning is an existing technology and will not be described in detail here.

[0130] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0131] After the laser film opening process, the mask 50 on the second area S22 has been removed by laser. In the alkaline etching step, the doped polysilicon in the second area S22 will be etched by the alkaline solution. After 350s, the doped polysilicon in the second area S22 has been completely etched. Since the first area S21 is protected by the mask, the doped polysilicon on the first area S21 is not affected.

[0132] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped polysilicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back of the battery and significantly improve the current; while the mask 50 exists in the first region S21 to block the corrosion of the alkaline solution, thereby not affecting the contact performance between the back electrode and the second doped layer.

[0133] It should be noted that during the acid-washing process to remove the tunneling layer 12 on the second region S22 and the mask 50 on the first region S21, the silicon substrate 10 on the second region S22 is also slightly etched away. Therefore, the silicon substrate 10 in the second region S22 is slightly thinner than the silicon substrate 10 in the first region S21. In other words, after the acid-washing step, the silicon substrate 10 in the second region S22 is recessed toward the first surface S1 compared to the silicon substrate 10 in the first region S21.

[0134] 8. Preparation of passivation layer

[0135] As shown in Figure 5h, the ALD process is used to prepare a first passivation layer 21 and a second passivation layer 22 on the first surface S1 and the second surface S2 of the silicon substrate, respectively. The first passivation layer 21 is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm, and the second passivation layer 22 is an aluminum oxide passivation layer with a thickness of 3nm to 5nm.

[0136] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer on the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer on the front, it is necessary to prepare the second passivation layer on the back at the same time to ensure a good interface passivation effect on the second area S22.

[0137] In addition, under high-temperature sintering conditions that ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0138] 9. Preparation of anti-reflection layer

[0139] As shown in Figure 5i, a PECVD process is used to prepare a first anti-reflection layer 31 and a second anti-reflection layer 32 on the first surface S1 and the second surface S2 of the silicon substrate, respectively. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0140] 10. Printing metal electrodes

[0141] As shown in FIG5 j , the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing, and then sintered and subjected to light injection or electrical injection treatment to form ohmic contacts.

[0142] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, which generally include a main gate line and a secondary gate line. It is worth noting that since the secondary gate line 421 in the second electrode 42 needs to be printed on the first area S21, the width of the first sub-area 101 needs to be greater than the width of the secondary gate line 421 in the second electrode 42, so that the secondary gate line 421 can be aligned.

[0143] The process flow in this embodiment is texturing → boron diffusion → back polishing → PE-poly → annealing → laser film opening → de-coating → ALD → PECVD → screen printing. TOPCon batteries can be prepared through the above steps, and finally the battery cells are tested, sorted, and put into storage.

[0144] Comparative Example 1:

[0145] The process flow in this comparative example is texturing → boron diffusion → back polishing → PE-poly → annealing → de-coating → ALD → PECVD → screen printing, which is a mass production process flow in the prior art.

[0146] Compared with Example 1, in this comparative example, no mask is deposited in the step of preparing the back tunneling passivation structure, and no laser film opening process is performed. The entire back surface of the silicon substrate has a tunneling layer + doped polysilicon layer, and the rest is the same as Example 1.

[0147] Comparative Example 2:

[0148] The process flow in this comparative example is texturing → boron diffusion → back polishing → LP-poly + phosphorus diffusion → annealing → laser → de-coating → ALD → PECVD → screen printing.

[0149] Compared with Example 1, in this comparative example, laser is used to remove the PSG (phosphosilicate glass), polysilicon (poly) and SiO2 tunneling layer generated after LP-poly+ phosphorus diffusion (~870°C) in the non-metallic area in one step, and then chemical etching is used to remove the remaining polysilicon.

[0150] Compared with Comparative Example 1, Example 1 only requires one additional laser film opening process, and the preparation method is simple. The TOPCon cells prepared in Example 1 and Comparative Example 1 were tested, and the performance parameters shown in Table 1 were obtained.

[0151] Table 1: TOPCon battery performance parameter comparison table

[0152] It can be seen that the battery performance of Example 1 is greatly improved compared with that of Comparative Example 1, the short-circuit current Isc can be increased by about 1%, the battery conversion efficiency Eta can be increased by about 0.4%, the back side parasitic absorption can be greatly reduced, and the bifaciality can be increased by about 6% at most.

[0153] Compared with Comparative Example 2, Example 1 uses a laser to open the silicon oxide mask and removes polysilicon and tunneling silicon oxide by a chemical etching process, while Comparative Example 2 uses a laser to remove PSG, polysilicon, and tunneling silicon oxide in one step. Example 1 has at least the following advantages:

[0154] 1. Adjust the laser parameters for the silicon oxide mask and use the laser film opening process to remove only the silicon oxide mask in the non-metallic area without affecting the passivation performance of the metal area on the back;

[0155] 2. Compared with PSG, the silicon oxide mask has a higher crystallization temperature and better density, which can better prevent laser damage to the amorphous silicon layer on the silicon substrate;

[0156] 3. The chemical etching process is used to remove polysilicon and tunnel silicon oxide, which is gentler and less damaging than the laser removal process. At the same time, the chemical etching process will form a tower base as shown in Figure 7 in the non-metallic area (the tower base is the base left after the pyramid velvet structure is polished). The tower base structure can further increase the photoelectric conversion efficiency and improve the bifaciality.

[0157] Example 2:

[0158] The solar cell and the preparation method in this embodiment are substantially the same as those in Example 1, except that the first doping layer 11 in Example 1 is prepared by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared by a PECVD process.

[0159] Specifically, in this embodiment, a boron-doped amorphous silicon layer 11 ′ is first deposited on the first surface S1 using a PECVD process, and then subjected to high-temperature oxidation annealing to form the first doped layer 11 , ie, a P-type doped polysilicon layer.

[0160] As shown in FIG8 a , first, double-sided texturing is performed on the silicon substrate 10 . The texturing process is exactly the same as that in Example 1 and will not be described in detail here.

[0161] As shown in FIG8b , a boron-doped amorphous silicon layer 11′ is first deposited on the first surface S1 using a PECVD process. For example, during the PECVD process, N2O is first introduced to form a silicon oxide layer (not shown) on the first surface S1. SiH4 and trimethylboron are then introduced to form a boron-doped amorphous silicon layer on the silicon oxide layer. Finally, N2O is introduced to form a silicon oxynitride mask (not shown).

[0162] As shown in FIG8 c , a first doped layer 11 is finally formed by a high-temperature oxidation annealing process. The high-temperature oxidation annealing process can transform the P-type doped amorphous silicon layer into a P-type doped polysilicon layer.

[0163] Different from Example 1, in this embodiment, a P-type doped polycrystalline silicon layer is prepared on the surface of the silicon substrate 10 by a PECVD process and annealing. During this process, the thickness of the silicon substrate 10 is constant. The total thickness of the silicon substrate 10 and the first doped layer 11 after annealing in Figure 8c is equal to the total thickness of the silicon substrate 10 and the boron-doped amorphous silicon layer 11' before annealing in Figure 8b, and is greater than the thickness of the silicon substrate 10 before the PECVD process in Figure 8a.

[0164] Example 3:

[0165] The structure of the solar cell in this embodiment is exactly the same as that in Example 1, but the preparation method is different. The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0166] 1. Double-sided velveting

[0167] As shown in Figure 9a, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 arranged opposite to each other. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front side (i.e., the light-receiving side) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlight side) of the silicon substrate 10. The first region S21 is a back metal region, and the second region S22 is a back non-metal region.

[0168] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and has a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0169] As shown in FIG9 b , in this embodiment, a pyramid texture structure is formed on the first surface S1 and the second surface S2 of the silicon substrate 10 by an alkali texturing process, and the size of the pyramid is 0.5 μm to 3 μm.

[0170] 2. Boron Diffusion

[0171] As shown in FIG9c, a P-type doped first doping layer (i.e., a P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, a boron source (e.g., BCl3 or BBr3, etc.) is used in a high-temperature furnace tube for diffusion. Optionally, a layer of silicon oxide is formed on the outer layer. After diffusion, the surface doping concentration of the first doping layer 11 is 3E18 cm -3 ~3E19cm -3 The square resistance is 40Ω / sq to 300Ω / sq, preferably 150Ω / sq to 250Ω / sq. During the boron diffusion process, BSG (not shown) is formed on the second surface S2 of the silicon substrate 10 .

[0172] In this embodiment, the outer silicon layer of the first surface S1 of the silicon substrate 10 is converted into a boron diffusion layer. The total thickness of the silicon substrate 10 and the first doped layer 11 after boron diffusion in FIG9c is equal to the thickness of the silicon substrate 10 before boron diffusion in FIG9b.

[0173] 3. Back polishing

[0174] As shown in FIG9d, the silicon substrate 10 after boron diffusion is first passed through a single-sided chain device to remove the back silicon oxide using a hydrofluoric acid solution, and then the back is alkaline polished to remove the edge junction and back side plating (BSG), and finally cleaned.

[0175] 4. Preparation of back-side tunneling passivation structure

[0176] As shown in FIG. 9 e , a tunneling layer 12 and a second doping layer 13 stacked in sequence are prepared on the second surface S2 .

[0177] For example, in this embodiment, a PECVD process is used to first deposit a silicon oxide tunneling layer with a thickness of 1nm to 3nm on the back side, and then deposit a layer of phosphorus-doped amorphous silicon or multiple layers of phosphorus-doped amorphous silicon with different doping concentrations, with a total thickness of 1nm to 150nm, preferably 50nm to 100nm.

[0178] 5. Laser oxidation

[0179] As shown in FIG9f , the second doped layer 13 on the first region S21 is processed by laser technology to crystallize the second doped layer 13 on the first region S21 and form an oxide layer 131 (or mask) on the surface of the second doped layer 13 on the first region S21 .

[0180] In this embodiment, the second doped layer 13 before the laser process is a phosphorus-doped amorphous silicon layer. The laser process can crystallize the phosphorus-doped amorphous silicon layer on the first region S21, activate phosphorus, and transform the phosphorus-doped amorphous silicon layer into a phosphorus-doped polysilicon layer; at the same time, the instantaneous high temperature of the laser is used to form silicon oxide (SiOX ) layer, the silicon oxide layer serves as a mask for subsequent processes.

[0181] Specifically, the laser process is carried out in an atmosphere containing oxygen, with a volume concentration of oxygen of 20% to 80%; the laser power is 1W to 100W, preferably 30W to 60W; the laser frequency is 1kHz to 1000kHz, preferably 300kHz to 600kHz; the laser scanning rate is 10000mm / s to 100000mm / s, preferably 30000mm / s to 60000mm / s; the number of laser processing times is 1 to 100 times, preferably 1 to 10 times. The surface doping concentration of the second doping layer 13 after laser processing is 2E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~2E21cm -3 The thickness of the formed oxide layer 131 is 1 nm to 50 nm.

[0182] For example, in a specific embodiment, the volume concentration of oxygen in the laser process is 50%, the laser power is 50W, the laser frequency is 500kHz, the laser scanning rate is 50000mm / s, the number of laser processing times is 2, and the surface doping concentration of the phosphorus-doped amorphous silicon layer is 9E20cm -3 The thickness of the silicon oxide layer formed by oxidation of the surface of the phosphorus-doped amorphous silicon layer is 0.01 nm to 10 nm.

[0183] Figure 10 shows the laser scanning pattern during the laser process of this embodiment. The black lines correspond to the laser scanning area, namely the first area S21 (i.e., the metal area), and the blank areas correspond to the second area S22 (i.e., the non-metal area). After the laser process, the first area S21 has a tunneling layer + phosphorus-doped polysilicon layer + silicon oxide layer structure, while the second area has a tunneling layer + phosphorus-doped amorphous silicon layer structure.

[0184] It should be understood that the laser scanning pattern in the present disclosure can be designed according to different electrode structures, so as to crystallize the amorphous silicon layer under the laser scanning area (i.e., the back metal area) and form a patterned silicon oxide mask. The laser scanning patterns for other electrode structures will not be illustrated one by one here.

[0185] In the prior art, high-temperature annealing is typically used to convert a doped amorphous silicon layer into a doped polysilicon layer. This requires the deposition of a separate mask layer using processes such as PECVD and subsequent patterning. However, the present invention utilizes a single laser process to achieve the conversion of doped amorphous silicon to doped polysilicon and the preparation of the patterned mask, significantly simplifying the process.

[0186] 6. De-plating and chemical etching

[0187] 9g, a chemical etching process is used to remove all the tunneling layer 12 and the second doping layer 13 on the second region S22 and the oxide layer 131 on the first region S21, and the tunneling layer 12 and the second doping layer 13 on the first region S21 are retained.

[0188] This step specifically includes:

[0189] Alkali etching: For example, in an alkaline cleaning tank, an alkaline solution is used to remove the entire second doping layer 13 on the second region S22 and simultaneously remove the front surface and edge plating. The mass fraction of the alkaline solution is 3% to 15%, and the processing time is 100s to 500s, preferably 350s.

[0190] Pickling: For example, in an acid pickling tank, an acid solution is used to remove the tunneling layer 12 on the second region S22 and the oxide layer 131 on the first region S21, and the PSG on the front surface is removed at the same time. The mass fraction of the acid solution is 5% to 20%, and the processing time is 100s to 500s, preferably 300s.

[0191] Finally, RCA cleaning is performed. RCA cleaning is an existing technology and will not be described in detail here.

[0192] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain proportion.

[0193] In the prior art, a front chain process (pickling) is usually required before the alkaline etching step, passing through a chain hydrofluoric acid tank to remove the silicon oxide mask that is plated around the edge. However, in the present disclosure, the silicon oxide mask is not prepared by the PECVD process, and no plating will be formed on the edge, so there is no need to go through the front chain process.

[0194] During the alkaline etching process, the second doped layer 13 (i.e., the phosphorus-doped amorphous silicon layer) on the second region S22 is corroded, which can reduce the parasitic absorption on the back of the battery and significantly improve the current; while the first region S21 has silicon oxide, which blocks the corrosion of the alkaline solution and thus does not affect the contact performance between the back electrode and the second doped layer.

[0195] It should be noted that during the acid-washing process to remove the tunneling layer 12 on the second region S22 and the oxide layer 131 on the first region S21, the silicon substrate 10 on the second region S22 is also slightly etched away. Therefore, the silicon substrate 10 in the second region S22 is slightly thinner than the silicon substrate 10 in the first region S21. In other words, after the acid-washing step, the silicon substrate 10 in the second region S22 is recessed toward the first surface S1 compared to the silicon substrate 10 in the first region S21.

[0196] 7. Preparation of passivation layer

[0197] As shown in FIG9h , the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 using the ALD process. The first passivation layer 21 and the second passivation layer 22 are both aluminum oxide passivation layers with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0198] After the de-plating and chemical etching steps, the tunneling layer and the doped polysilicon layer in the first area S21 can still ensure the passivation effect, while there is no passivation layer protection on the second area S22. Therefore, while preparing the first passivation layer 21 on the front, it is necessary to prepare the second passivation layer 22 on the back at the same time to ensure a good interface passivation effect on the second area S22.

[0199] In addition, under high-temperature sintering conditions that ensure good front contact, the second passivation layer 22 has a certain barrier effect on the back paste, so the second doping layer 13 can be further thinned, thereby improving the short-circuit current density of the battery.

[0200] 8. Preparation of anti-reflection layer

[0201] As shown in Figure 9i, a PECVD process is used to prepare a first anti-reflection layer 31 and a second anti-reflection layer 32 on the first surface S1 and the second surface S2 of the silicon substrate 10, respectively. The first anti-reflection layer 31 and the second anti-reflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60nm to 130nm.

[0202] 9. Printing metal electrodes

[0203] As shown in FIG9j, the first electrode 41 and the second electrode 42 are printed on the front and back surfaces respectively by screen printing, and then sintered and subjected to light injection or electric injection treatment to form ohmic contacts.

[0204] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, which generally include main gate lines and fine gate lines. It is worth noting that since the fine gate lines in the second electrode 42 need to be printed on the first region, the width of the first sub-region 101 needs to be greater than the width of the fine gate lines in the second electrode 42, so that the fine gate lines can be aligned.

[0205] TOPCon batteries can be prepared through the above steps, and finally the battery cells are tested, sorted and stored.

[0206] Example 4:

[0207] The structure and preparation method of the solar cell in this embodiment are roughly the same as those in Example 3, except that the first doping layer 11 in Example 3 is prepared below the first surface S1 of the silicon substrate (i.e., inside the silicon substrate) by a boron diffusion process, while the first doping layer 11 in this embodiment is prepared above the first surface S1 of the silicon substrate (i.e., outside the silicon substrate) by a PECVD process.

[0208] In this embodiment, the specific PECVD process is exactly the same as the PECVD process in Example 2, and will not be repeated here.

[0209] It should be understood that, in other embodiments, the first doped layer 11 can also be prepared by using a PECVD process. The specific PECVD process is exactly the same as the PECVD process in Example 2 and will not be described again here.

[0210] Example 5:

[0211] Figure 11 is a schematic diagram of the structure of the solar cell in this embodiment, which is a TOPCon cell. Combined with Figure 12, the solar cell in this embodiment has a different backside structure from the solar cells in Examples 1 to 4. Specifically, the structure in the first region S21 (metal region) is the same, while the structure in the second region S22 (non-metal region) includes a tunneling layer 12, a second doped layer 13, a second passivation layer 22, and a second anti-reflection layer 32 stacked in sequence. However, the thickness of the second doped layer 13 in the second region S22 is less than that in the first region S21.

[0212] The method for preparing the solar cell in this embodiment is similar to that in Example 3, except that the de-coating and chemical etching processes are different in step 6. In this embodiment, a chemical etching process is used to remove a portion of the second doped layer 13 on the second region S22 and the oxide layer 131 on the first region S21, while retaining the tunneling layer 12 and the second doped layer 13 on the first region S21, and retaining the tunneling layer 12 and a portion of the second doped layer 13 on the second region S22.

[0213] This step specifically includes:

[0214] Alkali etching: an alkaline solution is used to remove a portion of the second doped layer 13 on the second region S22, and the front surface and edge plating are removed at the same time. The alkaline etching can achieve the removal of a portion of the second doped layer 13 by adjusting the process parameters, such as shortening the alkaline etching time or reducing the mass fraction of the alkaline solution, which will not be described in detail here;

[0215] Pickling: using an acid solution to remove the oxide layer 131 of S21 on the first region and remove the PSG on the front side;

[0216] Finally, RCA cleaning is performed.

[0217] It should be understood that in this embodiment, the second doped layer 13 on the first region S21 is a doped polysilicon layer processed by laser technology, while the portion of the second doped layer 13 retained on the second region S21 is a doped amorphous silicon layer not processed by laser technology.

[0218] It can be seen from the above technical solutions that the present disclosure has the following beneficial effects:

[0219] The SE (Selective Emitter) structure fabrication process for the back side of the cell disclosed in this disclosure is simple. The oxidation and crystallization of the first region (metal region) can be completed in a single laser process, eliminating the mask making process, annealing process, and the front chain process before de-coating in the polysilicon process.

[0220] In addition, the present invention completely removes the doping layer in the second area (non-metal area) on the back of the battery, while the doping layer in the first area (metal area) is not affected. Without changing the slurry, it can take into account both the passivation effect and the reduction of parasitic absorption, thereby significantly improving the battery efficiency and bifaciality while increasing the process window.

[0221] It will be apparent to those skilled in the art that the present disclosure is not limited to the details of the exemplary embodiments described above and that the present disclosure can be implemented in other specific forms without departing from the spirit or essential characteristics of the present disclosure. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present disclosure is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0222] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, comprising the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface disposed opposite to each other, the second surface comprising a first region and a second region spaced apart from each other; forming a stacked tunneling layer and a second doping layer on the first region; forming a second passivation layer on the second region and the second doped layer, wherein the second passivation layer contacts the silicon substrate on the second region; as well as A second electrode is prepared on the first region and is in contact with the second doping layer.

2. The preparation method according to claim 1, wherein forming a stacked tunneling layer and a second doping layer on the first region, comprising: sequentially preparing the tunneling layer, the second doping layer and the mask on the second surface; removing the mask on the second area; and The second doping layer and the tunneling layer on the second region are removed, and the tunneling layer and the second doping layer on the first region are retained.

3. The preparation method according to claim 2, wherein removing the mask on the second area using a laser film opening process; as well as The second doping layer and the tunneling layer on the second region are removed by a chemical etching process.

4. The preparation method according to claim 2 or 3, wherein The tunneling layer, the second doping layer and the mask are sequentially prepared on the second surface, comprising: Depositing the tunneling layer, the doped amorphous silicon layer and the mask in sequence on the second surface of the silicon substrate; Annealing the silicon substrate on which the tunneling layer, the doped amorphous silicon layer, and the mask are deposited to transform the doped amorphous silicon layer into a doped polysilicon layer.

5. The preparation method according to any one of claims 2 to 4, wherein The preparation method further comprises: preparing light trapping structures on the first surface and the second surface of the silicon substrate by a texturing process; and / or The second surface of the silicon substrate is polished before the tunneling layer, the second doping layer and the mask are prepared.

6. The preparation method according to claim 1, wherein forming a stacked tunneling layer and a second doping layer on the first region, comprising: sequentially preparing the tunneling layer and the second doping layer on the second surface; processing the second doped layer on the first region to crystallize the second doped layer on the first region, and forming an oxide layer on a surface of the second doped layer on the first region, wherein the oxide layer serves as a mask; and The second doping layer and the tunneling layer on the second region are removed, and the oxide layer on the first region is removed, while the tunneling layer and the second doping layer on the first region are retained.

7. The preparation method according to claim 6, wherein The second doping layer on the first region is processed by a laser process, and the second doping layer and the tunneling layer on the second region and the oxide layer on the first region are removed by a chemical etching process.

8. The preparation method according to claim 7, wherein The second doped layer before the laser process is a doped amorphous silicon layer. The laser process crystallizes the doped amorphous silicon layer on the first region, converting the doped amorphous silicon layer into a doped polycrystalline silicon layer. At the same time, a silicon oxide layer is formed on the surface of the second doped layer on the first region, and the silicon oxide layer is used as the mask.

9. The preparation method according to claim 8, wherein The chemical etching process includes: Using the silicon oxide layer as the mask, the entire doped amorphous silicon layer on the second region is removed, and then the tunneling layer on the second region and the silicon oxide layer on the first region are removed.

10. The preparation method according to any one of claims 6 to 9, wherein The preparation method further comprises: preparing light trapping structures on the first surface and the second surface of the silicon substrate by a texturing process; and / or, The second surface of the silicon substrate is polished before forming the tunneling layer and the second doping layer.

11. A solar cell comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the second surface comprising a first region and a second region distributed at intervals, the first region being provided with a tunneling layer directly in contact with the silicon substrate, a second doped layer arranged on the tunneling layer, and a second electrode, the second region being provided with a second passivation layer in contact with the second surface of the silicon substrate, and the second electrode being in contact with the second doped layer.

12. The solar cell according to claim 11, wherein The second passivation layer extends onto the first region and covers the tunneling layer and the second doping layer.

13. The solar cell according to claim 11 or 12, wherein: The second passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm, 3nm to 6nm, or 3nm to 5nm.

14. The solar cell according to any one of claims 11 to 13, wherein: A second anti-reflection layer is stacked on the second passivation layer. The second anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

15. The solar cell according to any one of claims 11 to 14, wherein: The doping type of the second doping layer is the same as the doping type of the silicon substrate, the silicon substrate is an N-type silicon substrate, and the second doping layer is an N-type doped polysilicon layer; and / or, The surface doping concentration of the second doping layer is 1E20cm -3 ~1E21cm -3 , the thickness is 1nm~150nm or 50nm~100nm or 80nm~100nm.

16. The solar cell according to any one of claims 11 to 15, wherein: The tunneling layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of the two, and has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

17. The solar cell according to any one of claims 11 to 16, wherein: A first doping layer and a first electrode are formed on the first surface of the silicon substrate. The doping type of the first doping layer is opposite to the doping type of the silicon substrate. The first electrode is in contact with the first doping layer.

18. The solar cell according to claim 17, wherein A first passivation layer and / or a first anti-reflection layer is stacked on the first doped layer; The first passivation layer is an aluminum oxide passivation layer with a thickness of 2nm to 7nm or 3nm to 6nm; and / or, The first anti-reflection layer is a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and has a thickness of 60 nm to 130 nm.

19. The solar cell according to any one of claims 11 to 18, wherein The first region includes a plurality of first sub-regions distributed in parallel and at equal intervals, the second electrode includes a plurality of gate lines distributed in parallel, and the width of the first sub-region is greater than or equal to the width of the gate line.

20. A photovoltaic module, wherein: The photovoltaic module includes a solar cell prepared according to the preparation method according to any one of claims 1 to 10, or a solar cell according to any one of claims 11 to 19.

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