A streaming decoder for a quantum error correction code

Abstract

The present disclosure relates to apparatuses, classical modular processor units and methods for providing a decoder for finding a correction, C, to an error, E, detected in measurements of a qubit register received at intervals over time in a stream of successive measurement rounds. The decoder is implemented by a lattice or grid of identical classical modular processor units providing a viewing window of nodes and edges corresponding to a decoding graph for the quantum error correction code. Each classical modular processor unit independently and locally carries out a decoding cycle comprising a sequence of drop operation, a grow operation and a merge operation, by which a correction can be found to all errors arising in the qubit register within the viewing window in a computationally efficient, scalable manner that can clean the quantum computer faster than the error rate.

Description

A STREAMING DECODER FOR A QUANTUM ERROR CORRECTION CODE

[0001] TECHNICAL FIELD

[0002] The present disclosure relates to apparatuses, classical modular processor units and methods for finding a correction, C, to an error, E, detected in measurements of a qubit register received at intervals over time in a stream of successive measurement rounds.BACKGROUND

[0003] Decoders are crucial to the quantum error correction that enables fault-tolerant quantum computing. These classical algorithms must decode, i.e. infer errors from measurements and fix them. Further, measurements will in practice be typically received from a qubit register as a stream of measurement rounds. Viable decoders must find accurate solutions extremely quickly to clean the quantum computer faster than it corrupts.

[0004] It is difficult to design a decoder sufficiently accurate, fast, and practical to implement in hardware.

[0005] It is in this context the present disclosure is devised.SUMMARY OF THE DISCLOSURE

[0006] Viewed from one aspect, the disclosure provides apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register received at intervals over time in a stream of successive measurement rounds.

[0007] The apparatus comprises a plurality of identical classical modular processor units coupled by communication links, configured to provide a set of nodes, V, joined by a set of edges, E, together representing a viewing window, W= (V, E), corresponding to a subgraph of successive layers of a decoding graph, G, each layer of the decoding graph being for encapsulating faults that can occur in a measurement round of a quantum error correction code used for encoding at least one logical qubit across plural physical qubits in the qubit register;

[0008] The nodes comprise a subset of detector nodes, VD, configured to, in use, for a first, top layer of the viewing window, receive at each detector node one of a set of measurement bits of a stabilizer code (which is the error correction code) for a given ancilla qubit in the qubit register in the most recent measurement round, and flag defects where a measurement bit flips relative to the previous measurement round, a defect being flagged when an odd number of edges, E, incident on a node experience faults, each edge representing the set of faults that each cause a flip in the measurement bit of the or each detector node on whichthe edge is incident, the set of defects in the viewing window defining a syndrome, S, caused by an error, E, of the subset of edges suffering faults.

[0009] The nodes further comprise a subset of boundary nodes, VB, arranged along one or more walls of the viewing window, each boundary node communicatively coupled to a detector node such that an edge is provided in the viewing window to represent all faults that can each cause a flip in the measurement bit of the detector node incident on the edge.

[0010] The processor units are configured to store between them information on: the location of defects; clusters of edges grown around defects within which a correction to the errors causing the defects is sought; and a tentative correction, T, to the error for each cluster to be determined by the processors units as the clusters stream through the viewing window.

[0011] The processor units are further configured for performing a decoding cycle including, in turn, in each measurement round, a drop operation, a grow operation and a merge operation.

[0012] In performing the drop operation, the processor units are configured to drop the stored information on defects, clusters and tentative correction down one layer of the viewing window to receive a new measurement round for detector nodes in the top layer of the viewing window.

[0013] In performing the grow operation, the processor units are configured to grow active clusters along all available edges by a positive fraction of an edge, the fraction being less than one, such that clusters grow at a slower rate than they fall through the viewing window. The fraction may be different for different edges. In embodiments, the fraction is a half for all edges.

[0014] In performing the merge operation, the processor units are configured to: nucleate new active clusters at defects that are received in for the current measurement round at the top layer of the viewing window, W = (V, E) merge together clusters that have become joined by a fully grown edge; within active clusters, pass defects along fully grown edges towards any boundary node fully connected to the active cluster, or otherwise towards the highest node fully connected to the active cluster; store any edges along which defects are passed in a tentative correction, T, for the cluster; annihilate defects at nodes at which two defects are received; and mark any clusters inactive that no longer contain any defects or if the defect has been passed to a boundary node, such that the inactive cluster no longer grows in the next decoding cycle (and in subsequent timesteps unless it becomes active again).

[0015] The processor units are further configured such that, in a commit region of c layers comprising at least the last, bottom layer of the viewing window, W = (V, E), the edges flagged in the tentative correction, T, are committed to form part of a correction, C, of a set of edges to be bitflipped to correct for the error, E, such that the syndrome, S, is the null set in the commit region.

[0016] In this way, a streaming decoder is provided that can be local i.e. running on a grid of identical classical modular processor units, each communicating only with their nearest neighbours. In this way, the decoder benefit from parallelism, hardware practicality and robustness when used with local (requiring no long-range qubit-qubit interactions) codes. For this, the apparatus uses a Union-Find decoder (UF), which is a relatively new decoder candidate, implemented in the apparatus for streaming measurements in a computationally efficient manner. Recent literature has explored UF implementations of varying levels of locality. However, these decoders tackled only the batch decoding problem: a simplification of the stream decoding problem that actually happens in practice. Since 2002, only two methods have been proposed allowing most batch decoders to be used as stream decoders. These are the “forward method” and the “sandwich method”. In contrast, the present disclosure provides an apparatus implementing a local decoder in the fully streaming case.

[0017] As will become apparent from the present disclosure, the apparatus and method disclosed herein implements the decoder using a simple set of local rules with very little central management, and works for any error-correcting code with a decoding graph embeddable in R3without Tong-range’ edges. Examples include the repetition code and the surface code under circuit-level noise. The apparatus and method disclosed herein relies on a “frugal” method for general stream decoding, which is different to the forward method, in that it discards none of the computation, and so it is more frugal with resources.

[0018] For the surface code under circuit-level noise, the apparatus and method disclosed herein, specifically in relation to the implementation described in relation to FIG. 7 to FIG. 12 and FIG. 14, has a threshold roughly 2 / 3 that of UF adapted with the forward method. Despite its slightly reduced accuracy, the apparatus and method disclosed herein boasts a straightforward distributed implementation that is modular and scalable by building a 2D or 3D lattice of processors. Using a processor that can operate the decoder in a ‘flattened’ 2D lattice, provides an even more practical implementation given current chip design capabilities, at a marginal cost in speed. For the surface code under circuit-level noise, the apparatus and method disclosed herein, specifically in relation to the implementation described in relation to FIG. 16 to FIG. 21, is roughly as accurate as UF adapted with the forward method.

[0019] In examples, for each edge that represents the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident, the set of faults may be based on a noise model that includes at least the faults that can arise in: a data qubit in the qubit register; and a measurement outcome of a stabilizer code in a given ancilla qubit. In examples, the set of faults may be based on a noise model that further includes the faults that can arise in: a quantum circuit performed during a measurement round. In examples, the quantum error correction code may be a repetition code or a surface code. In examples, the topology of the decoding graph, G, and the set of nodes, V, joined by a set of edges, E, together representing a viewing window, W= (V, E), provided by the plurality of identical classical modular processor units coupled by communication links, may be based on the quantum error correction code and the noise model.

[0020] In this way, the apparatus and method disclosed herein may be configured to decode errors in streaming measurement rounds from a qubit register encoding logical qubits using a range of quantum error correction codes under a phenomenological noise model and under a circuit level noise model, while also accounting for the capacity of the quantum error correction code.

[0021] In examples, the viewing window, W = (V, E), may consist of the commit region and a buffer region of b layers above and consecutive with the commit region, wherein the buffer region may include 2*floor(t / / 2) layers. In examples, d may be the code distance of the quantum error correction code, such that the edges in the tentative correction, T, committed to the correction, C, in the commit region, is always complete in that all defects in the commit region are annihilated. In examples, the commit region may consist of c layers. In examples, c = 1, such that W consists of a minimised number of 2*floor(t / / 2) + 1 layers.

[0022] In this way, the size of the buffer, and the complexity of the architecture, can be minimised while ensuring all errors accounted for in the noise model are decoded, allowing fast and efficient decoding.

[0023] In examples, the apparatus may further comprise one or more processor units configured to: provide a measurement queue for storing measurement bits from measurement rounds of the qubit register; receive and store in a queue measurement bits from consecutive measurement rounds completed for the qubit register; and responsive to the completion of a decoding cycle, pass to the top layer of the detector nodes in the viewing window, W = (V, E), the measurement bits from the oldest measurement round stored in the queue to provide the new measurement round for the next decoding cycle. Inexamples, the one or more processor units may be configured such that the average time taken to complete a decoding cycle is shorter than the average time between measurement rounds of the qubit register.

[0024] In this way, the apparatus can store a queue of measurement rounds before being passed to the decoder, allowing each decoding cycle to take a variable time to complete, while also ensuring the errors can be sufficiently removed from the system provided the average decoding cycle is shorter than the average time between measurement rounds of the qubit register.

[0025] In examples, the viewing window, W = (V, E), may be raised by one layer each decoding cycle. In examples, the computed tentative correction, T, may be retained between decoding cycles.

[0026] In this way, no computation is discarded between decoding cycles, and the decoding is computationally efficient.

[0027] In examples, the processor units may be further configured to, in the decoding cycle, bitflip all edges added to the tentative correction, T, such that the syndrome, S, is modified even in layers above the commit region.

[0028] In this way, the edges in the correction are bitflipped before they arrive in the commit region.

[0029] In examples, the plurality of identical classical modular processor units may each be coupled by communication links to one or more of the other modular processor units to perform communication only with their nearest neighbours. In examples, each processor unit may further comprise circuitry configured to perform the decoding cycle by carrying out the drop, grow and merge operations local to that processor based only on the information stored thereat and only by communication with its nearest neighbour processor nodes only.

[0030] In this way the apparatus of the present disclosure implements a decoder using truly local architecture with parallel operations being performed independently and simultaneously by an array of identical classical modular processor units. This provides a fast and scalable streaming decoder.

[0031] In examples, the apparatus may be configured such that the processor units independently perform the drop, grow and merge operations in turn and synchrony. In examples, the processor units may be configured to independently perform the drop, grow and merge operations in successive, discrete and synchronised timesteps, the drop and grow operations each taking one timestep, the merge operation taking an undetermined number oftimesteps. In examples, the apparatus may further comprise a controller coupled to the processor units and configured to send an instruction to the processor units to cause the nodes to perform a drop operation after three timesteps unless any of the nodes are still busy merging.

[0032] In this way, the independent, locally operating, identical classical modular processor units may be coordinated in their operation of the decoding cycle.

[0033] In examples, one processor unit may be provided for each node in the viewing window, such that the processor units and communication links together form a plurality of stacked layers arranged as the decoding graph within the viewing window.

[0034] In this way, the decoder apparatus is of a simple “3D” architecture allowing fast and local operation.

[0035] In examples, one processor unit may be provided for each set of nodes representing the same ancilla qubit across plural layers in the viewing window, such that the layers of the viewing window are flattened into a single layer of processor units, the processor units and communication links together being arranged to provide the decoding graph in the viewing window.

[0036] In this way, the decoder apparatus is of a flattened “2D” architecture which may facilitate implementation in current processor design, and may also avoid some interprocessor communication.

[0037] In examples, each processor unit may comprise memory configured to store local to each node the information on defects, clusters and the tentative correction as attributes including: whether the node has a defect; whether the node is in an active cluster; which cluster the node belongs to based on a unique cluster identifier, CID; and, for each edge owned by the node: a growth value; and whether the edge belongs in the tentative correction, T.

[0038] In examples, the processor units may be configured such that, in the drop operation, each node communicates in one timestep its stored attributes down to the corresponding node in the next layer corresponding to the next oldest measurement round.

[0039] In examples, the processor units may be configured such that, in the grow operation, each node in an active cluster causes in one timestep the growth value of edges incident on that node to increase by Yi (or another positive fraction less than one) for all edges having a growth value of less than 1, such that clusters nucleate and become active at nodes flagging defects and grow along edges at a slower rate than the rate the nodes droptheir attributes, and by which separate clusters can become fully connected by edges having a growth value of 1, allowing clusters to be merged.

[0040] In examples, the processor units may be configured such that, in the merge operation, each node in an active cluster is configured to iteratively perform in successive timesteps until completion: firstly, syncing, by which the defects are passed along fully grown edges towards any boundary node fully connected to the active cluster, or otherwise towards the highest node fully connected to the active cluster, by which, for any edges along which defects are passed during syncing, attributes indicating whether those edges belong in the tentative correction, T, are flipped, by which any nodes receiving two defects causes the defects to annihilate, and by which the cluster is marked inactive and no longer grows in the next decoding cycle if it no longer contains any defects or if a defect has been passed to a boundary node (although it may grow again if an active cluster later merges with it to render it active again); and secondly, flooding, by which the cluster identifier of the node is updated to indicate a node identifier of the highest node fully within the cluster.

[0041] In examples, each node may store a unique node identifier, wherein the detector nodes higher in the viewing window may have a lower ordinal node identifier than detector nodes lower in the viewing window, and wherein the boundary nodes may have lower ordinal node identifiers than the detector nodes, and wherein the node identifiers may be used by the nodes as a basis for passing defects towards the highest node fully connected to an active cluster, and for flooding so that each node in an active cluster knows, through its cluster identifier, the ordinal node identifier of its root.

[0042] In this way, the apparatus allows the operations making up the decoding cycle to find the correction to the error to be performed independently and in parallel by local operations at each classical modular processor unit.

[0043] In embodiments, the processor units may have circuitry to be configured to perform each decoding cycle by carrying out, in turn: a drop operation; a first grow operation in which active whole-edge clusters that have been grown an even number of times to have ungrown or half-grown edges available for growth are grown along those edges by a positive fraction of an edge, the fraction being half an edge; a merge operation; a second grow operation in which active half-edge clusters that have been grown an odd number of times to have only half-grown edges available for growth are grown along those edges by a positive fraction of an edge, the fraction being half an edge; and a further merge operation.

[0044] That is, the processor units may be configured such that, in each decoding cycle, following the drop operation, a first grow operation may be performed for available edges in“whole-edge” clusters only, and a following second grow operation may be performed for available edges in “half-edge” clusters only. A merge operation is performed following each of the first and second grow operations. By configuring the processor units to implement a two stage grow-then-merge operation in each decoding cycle in a “2: 1 cluster growth schedule” in this way, the “overgrowth” of active clusters half an edge apart into each other is avoided, resulting in a further reduced logical error rate which is comparable to the error rate achieved with union find adapted with the forward method.

[0045] Viewed from another aspect, the present disclosure provides a classical modular processor unit for use in an apparatus disclosed in examples herein.

[0046] In this way, multiple identical classical modular processor units can be produced that can be easily and scaleably assembled to implement a streaming decoder.

[0047] Viewed from another aspect, the present disclosure provides a method of finding a correction, C, to an error, E, detected in measurements of a qubit register. The method is performed in a plurality of identical classical modular processor units coupled by communication links configured to provide a set of nodes, V, joined by a set of edges, E, together representing a viewing window, W= (V, E), corresponding to a subgraph of successive layers of a decoding graph, G, each layer of the decoding graph being for encapsulating faults that can occur in a measurement round of a quantum error correction code used for encoding at least one logical qubit across plural physical qubits in the qubit register.

[0048] The method includes, for each of a stream of measurement rounds, performing a decoding cycle comprising receiving, a set of measurement bits of a stabilizer code (which is the error correction code) for the most recent measurement round, each measurement bit for a given ancilla qubit in the qubit register being received at one of a subset of detector nodes, VD, and stored in a first, top layer of the viewing window.

[0049] The decoding cycle also comprises flagging defects at detector nodes, VD, where a measurement bit flips relative to the previous measurement round, a defect being flagged when an odd number of edges, E, incident on a node experience faults in that measurement round, each edge representing the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident, the set of defects in the viewing window defining a syndrome, S, caused by an error, E, of the subset of edges suffering faults. It should be noted that a syndrome, S, may be produced by a number of different errors, E, and so a specific error creating the syndrome, S, cannot be reliably inferred from the syndrome, S.

[0050] The decoding cycle also comprises a drop operation including dropping down one layer of the viewing window, to receive the new measurement round for detector nodes in the top layer of the viewing window, stored information on: the locations of any defects; any clusters of edges grown around defects within which a correction to the errors causing the defects is sought; and a tentative correction, T, to the error for each cluster to be determined by the processor units as the clusters stream through the viewing window.

[0051] The decoding cycle also comprises a grow operation including growing active clusters along all available edges by a positive fraction of an edge, the fraction being less than one, such that clusters grow at a slower rate than they fall through the viewing window.

[0052] The decoding cycle also comprises a merge operation including: nucleating new active clusters at defects as they are received in new measurement rounds at the top layer of the viewing window, W= (V, E) and merging together clusters that become joined by a fully grown edge;

[0053] The merge operation also includes, within active clusters, passing defects along fully grown edges towards: any of a subset of boundary nodes, VB, fully connected to the active cluster, the boundary nodes, VB, being arranged along one or more walls of the viewing window, each boundary node communicatively coupled to a detector node such that an edge is provided in the viewing window to represent all faults than can each cause a flip in the measurement bit of the detector node incident on the edge; or otherwise towards the highest node fully connected to the active cluster.

[0054] The merge operation also includes storing any edges along which defects are passed in a tentative correction, T, for the cluster; and annihilating defects at nodes at which two defects meet.

[0055] The merge operation also includes marking any clusters inactive that no longer contain any defects or if the defect has been passed to a boundary node, such that the inactive cluster no longer grows in the next decoding cycle (and in subsequent timesteps unless it becomes active again).

[0056] The method also includes, for a commit region of layers comprising at least the last, bottom layer of the viewing window, W = (V, E), committing the edges flagged in the tentative correction, T, to form part of a correction, C, of a set of edges to be bitflipped to correct for the error, E, such that the syndrome, S, is the null set in the commit region.

[0057] It will be appreciated from the foregoing disclosure and the following detailed description of the examples that certain features and implementations described as being optional in relation to any given aspect of the disclosure set out above should be understoodby the reader as being disclosed also in combination with the other aspects of the present disclosure, where applicable. Similarly, it will be appreciated that any attendant advantages described in relation to any given aspect of the disclosure set out above should be understood by the reader as being disclosed as advantages of the other aspects of the present disclosure, where applicable. That is, the description of optional features and advantages in relation to a specific aspect of the disclosure above is not limiting, and it should be understood that the disclosures of these optional features and advantages are intended to relate to all aspects of the disclosure in combination, where such combination is applicable.BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Certain examples of the present disclosure will now be described, with reference to the accompanying drawings, in which:

[0059] FIG. 1 shows a schematic illustration of an example apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure;

[0060] FIG. 2A shows a schematic illustration of an example decoder apparatus used in the example apparatus of FIG. 1 for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure;

[0061] FIG. 2B shows a schematic illustration of the example decoder apparatus shown in FIG. 2A flagging defects at detector nodes, the defects being caused by an error, E, in the qubit register over successive measurement rounds;

[0062] FIG. 2C shows a schematic illustration of an example correction, C, for the error, E , in the example decoder apparatus shown in FIG. 2B;

[0063] FIG. 2D shows a schematic illustration the leftover, L, after combining the bitflipped edges of the error, E, and the example correction, C, for the error, E, in the example decoder apparatus as shown in FIG. 2B and FIG. 2C;

[0064] FIG. 3 shows a schematic illustration of an example classical modular processor unit in accordance with aspects of the present invention, for use in the example apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register as shown in FIG. 1;

[0065] FIG. 4 shows a flowchart representing an example method for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure;

[0066] FIG. 5 A shows a schematic illustration of the operation of the apparatus of FIG. 1 for decoding, over receipt of successive measurements rounds over time, an error, E, resulting in a single defect in a qubit register encoding a repetition code;

[0067] FIG. 5B shows a schematic illustration of the operation of the apparatus of FIG. 1 for decoding, over receipt of successive measurements rounds over time, an error, E, resulting in two defects in a qubit register encoding a repetition code;

[0068] FIG. 6 shows a flowchart representing, in more detail than FIG. 4, a further example method for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure;

[0069] FIG. 7A shows example pseudocode for operating the controller to control the classical modular processor units to coordinate the progress of the decoding cycle of the methods shown in FIG. 4 and FIG. 6;

[0070] FIG. 7B shows example pseudocode for operation locally at each node by the classical modular processor units for progressing the decoding cycle of the methods shown in FIG. 4 and FIG. 6;

[0071] FIG. 7C shows example pseudocode for operation locally at each node by the classical modular processor units for implementing the drop operation, grow operation and merge operation of the methods shown in FIG. 4 and FIG. 6;

[0072] FIG. 7D shows example pseudocode for operation locally at each node by the classical modular processor units for implementing the syncing and flooding subroutines of the merge operation of the methods shown in FIG. 4 and FIG. 6

[0073] FIG. 8A shows a sequence of panes (A)-(I) illustrating the progress of an example operation of the apparatus of FIG. 1 to decode an error, E, resulting in two defects in a qubit register encoding a repetition code having a code distance of five;

[0074] FIG. 8B shows a sequence of panes (J)-(Q) illustrating the further progress of the example operation of the apparatus as shown in FIG. 8A;

[0075] FIG. 9A shows a sequence of panes (A)-(I) illustrating the progress of an example operation of the apparatus of FIG. 1 to decode an error, E, resulting in a single defect in a qubit register encoding a repetition code having a code distance of four;

[0076] FIG. 9B shows a sequence of panes (J)-(Q) illustrating the further progress of the example operation of the apparatus as shown in FIG. 8A;

[0077] FIG. 9C shows a sequence of panes (R)-(X) illustrating the further progress of the example operation of the apparatus as shown in FIG. 8A and FIG. 8B;

[0078] FIG. 10 shows a schematic illustration of an example cluster grown in a viewing window arranged as a subgraph of a decoding graph for a decoder for a surface code of distance-3 under a circuit-level noise model;

[0079] FIG. 11 shows plots for the logical error rate for (a) a streaming decoder implementing the forward method and (b) the streaming decoder of the present disclosure, applied to the surface code of distance d under circuit-level noise of different physical error probabilities;

[0080] FIG. 12 shows plots of the count of timesteps per d measurement rounds against surface code distance d, under circuit level noise for different physical error probabilities p below threshold on (a) a linear-linear scale and (b) a log-log scale;

[0081] FIG. 13 shows a schematic illustration of another example apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register using a flattened classical modular processor units in accordance with aspects of the present disclosure;

[0082] FIG. 14 shows example pseudocode describing the general, abstract global implementation by the classical modular processor units for implementing a 1 : 1 cluster growth schedule;

[0083] FIG. 15 shows a sequence of panes illustrating the progress of an example operation of the apparatus of FIG. 1 implementing a 1 : 1 cluster growth schedule in which two active clusters half an edge apart are “overgrown” into each other, resulting in a merged cluster of unnecessarily large size;

[0084] FIG. 16 shows a flowchart representing another example method for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure in which a 2: 1 cluster growth schedule is implemented;

[0085] FIG. 17 shows a sequence of panes illustrating the progress of an example operation of the apparatus of FIG. 1 implementing a 2: 1 cluster growth schedule in which “overgrowth” into each other of two active clusters half an edge apart is avoided;

[0086] FIG. 18A shows example pseudocode for operation locally at each node by the classical modular processor units for implementing a 2: 1 cluster growth schedule;

[0087] FIG. 18B shows example further pseudocode for operation locally at each node by the classical modular processor units for implementing a 2: 1 cluster growth schedule;

[0088] FIG. 18C shows example further pseudocode for operation locally at each node by the classical modular processor units for implementing a 2: 1 cluster growth schedule;

[0089] FIG. 19 shows a plot comparing the logical error rate for the streaming decoder of the present disclosure, applied to the surface code of distance d under circuit-level noise of different physical error probabilities p, where the classical modular processor units are configured for implementing a 1 : 1 cluster growth schedule and a 2: 1 cluster growth schedule;

[0090] FIG. 20 shows a plot comparing the logical error rate for the streaming decoder of the present disclosure where the classical modular processor units are configured for implementing a 2:1 cluster growth schedule and a streaming decoder implementing the forward method; and

[0091] FIG. 21 shows plots of the count of timesteps per d measurement rounds against surface code distance d. under circuit level noise for different physical error probabilities p below threshold on a log-log scale for (a) a streaming decoder implementing the forward method, (b) the streaming decoder of the present disclosure where the classical modular processor units are configured for implementing a 2: 1 cluster growth schedule.DETAILED DESCRIPTION

[0092] Hereinafter, examples of the disclosure are described with reference to the accompanying drawings. However, it should be appreciated that the disclosure is not limited to the described examples, and all changes and / or equivalents or replacements thereto also belong to the scope of the disclosure. The same or similar reference denotations may be used to refer to the same or similar elements throughout the specification and the drawings.

[0093] As used herein, the terms “have,” “may have,” “include,” or “may include” a feature (e.g., a number, function, operation, or a component such as a part) indicate the existence of the feature and do not exclude the existence of other features. Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of them mean “including but not limited to”, and they are not intended to (and do not) exclude other components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

[0094] As used herein, the terms “A or B,” “at least one of A and / or B,” or “one or more of A and / or B” may include all possible combinations of A and B. For example, “A or B,” “at least one of A and B,” “at least one of A or B” may indicate all of (1) including at least one A, (2) including at least one B, or (3) including at least one A and at least one B.

[0095] As used herein, the terms “first” and “second” may modify various components regardless of importance and do not limit the components. These terms are only used to distinguish one component from another. For example, reference to a first component and a second component may indicate different components from each other regardless of the order or importance of the components.

[0096] It will be understood that when an element (e.g., a first element) is referred to as being (physically, operatively or communicatively) “coupled with / to,” or “connected with / to” another element (e.g., a second element), it can be coupled or connected with / to the other element directly or via a third element. In contrast, it will be understood that when an element (e.g., a first element) is referred to as being “directly coupled with / to” or “directly connected with / to” another element (e.g., a second element), no other element (e.g., a third element) intervenes between the element and the other element.

[0097] The terms as used herein are provided merely to describe some embodiments thereof, but not to limit the scope of other embodiments of the disclosure. It is to be understood that the singular forms “a,” “'an,” and “the” include plural references unless the context clearly dictates otherwise. All terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the disclosure belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0098] Reference will now be made to FIG. 1, which shows a schematic illustration of an example apparatus 100 in accordance with aspects of the present disclosure.

[0099] The apparatus 100 comprises a decoder apparatus 110 and in certain examples, a controller 102. In FIG. 1, the use of the broken lines indicates that the features are not necessarily provided in accordance with aspects of the disclosure, and may be optional in the that they are provided in conjunction with the apparatus 100 in an implementation and in use. In this respect, the apparatus may also include a controller 102. When implemented and in use, the apparatus 100 may be provided to operate in conjunction with a qubit register 104 comprising a plurality of qubits 106, and a syndrome measurement circuit 108.

[0100] That is, in use, the apparatus 100 is provided for carrying out a decoding cycle to decode a correction, C, to an error, E, detected in measurements of a qubit register 104 received from a syndrome measurement circuit 108 at intervals over time in a stream of successive measurement rounds.

[0101] A quantum error correction code, such as a surface code or a repetition code, is used to encode at least one logical qubit into entangled states across the plural physical qubits 106 suitably arranged in the qubit register 104. It should be noted here that any suitable form of physical qubit may be provided in the qubit register 104 that can be used to encode logical qubits using a quantum error correction code, including but not limited to superconducting qubits, trapped ion qubits, quantum dots, photonic qubits, topological qubits, neutral atom qubits, and semiconductor-based qubits.

[0102] The quantum error correction code effectively de-localises the information in a single qubit across a plurality of qubits in the qubit register 104. This creates an encoding of the logical states of the qubit into a subspace (a codespace) of the expanded Hilbert space achieved through the entanglement. Faults that occur in the qubit register 104, such as a bit flip or a phase flip, cause the logical state to be rotated onto an orthogonal error space in the expanded Hilbert space. These faults can be detected by carrying out a series of stabiliser code measurements, which are effectively a series of Pauli operators performed as a sequence of quantum circuits in the qubit register 104, to extract a syndrome from the qubit register 104. Thus the syndrome measurement circuit 108 is configured to, in use, perform a series of measurements of stabilizer codes across the physical qubits 106, the set of stabilizer codes being selected so as to be enable faults to be detected without disturbing the encoded information.

[0103] In this way, the quantum error correction code may cause the plurality of physical qubits 106 to be divided into a set of code, data or information qubits, in which the quantum information is encoded, and a set of ancilla qubits on which the series of quantum circuits can be performed by the syndrome measurement circuit 108 to carry out the detection of faults in the qubit register 104. The operation of the syndrome measurement circuit 108 produces a set of measurement bits for a measurement round of the qubit register 104, which are passed to the decoder apparatus 110. Normally, when no errors occur, the stabilizer codes operated by the syndrome measurement circuit 108 return a set of measurement bits that are all zeroes. However, where a fault occurs in the qubit register 104 or the syndrome measurement circuit 108 (which is accounted for in a circuit-level noise model), this can cause a bitflip in the measurement bits returned by the syndrome measurement circuit 108, the bitflips indicating a syndrome, S, of defects flagged in the ancilla qubits of the qubit register 104, and being usable to infer the nature of the set of faults occurring in the qubit register 104. This will be explained in more detail in relation to FIG. 2A to FIG. 2D.

[0104] The decoder apparatus 110 is provided to determine a correction, C, to the error, E , detected in measurements of a qubit register 104 received from a syndrome measurement circuit 108 at intervals over time in a stream of successive measurement rounds. For this, the decoder apparatus 110 comprises a plurality of identical classical modular processor units 112 (indicated in the Figures by both the circles and the octagons) coupled by communication links 114 (indicated by solid the lines joining to one or more of the other classical modular processor units 112. The classical modular processor units 112 and communication links 114 may be such that the classical modular processor units 112 may perform communication only with their nearest neighbours, allowing the decoder apparatus 110 to be truly local in architecture with operations in the decoding cycle being performed in parallel independently and simultaneously by the array of identical classical modular processor units 112. The structure and operation of the classical modular processor units 112 will be described in more detail in FIG. 3, FIG. 4 and FIG. 6.

[0105] The plurality of identical classical modular processor units 112 coupled by communication links 114 are configured to provide a set of nodes, V, joined by a set of edges, E, together representing a viewing window, W= (V, E), corresponding to a subgraph of successive layers of a decoding graph, G, each layer of the decoding graph being for encapsulating faults that can occur in a measurement round of the quantum error correction code. Since the stream decoding problem is defined for only phenomenological and circuitlevel noise, the viewing window, W, is used to physically represent the decoding graph, G, for the quantum error correction code under these two models. In the example in FIG. 1, a viewing window arranged as a decoding graph for a distance-3 quantum error correction code is shown for visual clarity, but this is not intended to be limiting and the present disclosure can be applied to a quantum error correction code having any suitable code distance.

[0106] That is, the classical modular processor units 112 and communication links 114 are arranged to provide a set of nodes, F, and edges, E, to match a decoding graph for the quantum error correction code used to encode logical qubits in the qubit register, adapted for according to noise model for which faults are to be detected. As each layer of the decoding graph, G, is for encapsulating faults that can occur in a measurement round of the quantum error correction code, the arrangement of multiple layers allows for successive measurement rounds received as a stream of measurement bits from the syndrome measurement circuit 108 to be represented as a viewing window, W, of the stream of syndrome measurement rounds received over time. The viewing window, W, provides a buffer within which the plurality of classical modular processor units 112 of the decoderapparatus 110 individually operate the methods described herein to together find a correction for the faults detected in the measurement rounds from the qubit register 104. By applying the correction, the errors can be mitigated, allowing fault tolerant operation of the qubit register 104 under the noise model and the quantum error correction code.

[0107] It should be noted that, in the description and accompanying drawings, the ‘top’ layer of the viewing window is taken to store the measurement bits and other decoding operation information for the most recent measurement round, and that this information is said to be passed ‘downwards’ to lower layers as new measurement rounds are received as the decoding cycles are completed, such that ‘arrow of time’ in the viewing window, W, points 'up', to more recent measurement rounds. Of course, this arrangement of ‘top’ to ‘bottom’ progression of information is purely indicative and is not intended to be limiting, and it encompasses any analogous arrangement of layers and progression of the measurement rounds through those layers (e.g. from ‘bottom’ to ‘top’ or any other arrangement).

[0108] The classical modular processor units 112 are arranged such that the nodes, V, comprise a subset of detector nodes, VD (indicated by the circles in the viewing window, W) and a subset of boundary nodes, VB, (indicated by the octagons in the viewing window, W). It should be noted that the classical modular processor unit 112 that are used to provide the detector nodes, VD, and the boundary nodes, VB, can be identical, in that they are configured identically to carry out the same operations in the decoding cycle.

[0109] The difference is that the classical modular processor units 112 representing the detector nodes, VD, are configured to, in use, for a first, top layer of the viewing window, receive at each detector node one of a set of measurement bits of a stabilizer code (which is the error correction code) for a given ancilla qubit in the qubit register in the most recent measurement round. That is, essentially, the detector nodes, VD, are associated with the measurement of the stabilizer code at a single ancilla qubit in the qubit register 104.

[0110] Specifically, since the stream decoding problem is defined for only phenomenological and circuit-level noise, each detector node, VD, represents the difference between two consecutive measurements of an ancilla qubit at a given point in time. That is, each detector node, VD, flags a defect where a measurement bit flips relative to the previous measurement round.[OHl] The classical modular processor units 112 representing the boundary nodes, VB, are configured such that the boundary nodes, VB, are arranged along one or more walls of the viewing window, W, and such that each boundary node, VB, is communicatively coupled to adetector node, VD, by a communication link 114. Unlike detector nodes, VD, boundary nodes, VB, represent nothing physical.

[0112] Generally, in the viewing window, W, detector nodes can be defects, and boundary nodes cannot.

[0113] The set of edges, E, represented by communication links 114, corresponds to a set of two joined nodes in the viewing window, V. The set of edges, E, includes a set of bulk edges, Ebu, which each connect two detector nodes, and a set of boundary edges, Ebo, which eah join a detector node to a boundary node.

[0114] Edges represent the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident. That is, each bulk edges, Ebu, represents a possible pair of defects that could have resulted from one fault. That is, one fault associated with a bulk edge causes the measurement bit received at the pair of detector nodes adjoining a bulk edge to flip. Thus a possible pair of defects may arise at those detector nodes.

[0115] Each boundary edge, Ebo, represents a possible defect that could have resulted from one fault. That is, a fault in a boundary edge causes the measurement bit received at the detector node adjoining a boundary edge to flip. Thus a possible defect may arise at the incident detector node.

[0116] However, if any detector nodes experience a fault from one adjoining edge has incident on in another edge (be it a bulk edge or a boundary edge) that itself also suffers a fault, that further fault will also cause the measurement bit to flip again for that detector node, cancelling out the bitflip from the fault in the first edge. In this way, the detector nodes that receive flipped measurement bits in a measurement round (in particular a change relative to the previous round) flag defects, which indicate faults occurring in an odd number or parity of incident edges to that detector node.

[0117] That is, a defect is a detector node touching an odd number of bitflipped edges (i.e. edges suffering faults). Each edge can, at any given time, be either bitflipped or not bitflipped. In a decoding cycle, each edge bitflips with some potentially unique probability that is a function of a universal noise level p.

[0118] The subset of detector nodes flagging defects for a measurement round, and for the viewing window as a whole, is the syndrome, S, caused by an error, E, of the subset of edges suffering faults.

[0119] The set of faults may be based on a noise model that includes at least the faults that can arise in:• a data qubit in the qubit register (i.e. a fault associated with the code capacity, such as a bit flip or a phase flip in the data qubit associated with the edge); and• a measurement outcome of a stabilizer code in a given ancilla qubit (i.e. a fault in the ancilla qubit measurement outcome associated with phenomenological noise, which is represented by 'vertical' edges in the viewing window spanning layers of successive measurement rounds); and / or• a quantum circuit performed during a measurement round (i.e. a fault in the process in the syndrome extraction circuit associated with circuit level noise, which is represented by the addition of certain ‘diagonal’ edges spanning different nodes across layers of successive measurement rounds).

[0120] The viewing window, W, used by the decoder apparatus 110 may thus be configured as a decoding graph, G, to include edges for use in decoding errors in streaming measurement rounds under a phenomenological noise model and under a circuit level noise model, while also accounting for the capacity of the quantum error correction code.

[0121] In the example decoder apparatus 110 arrangement shown in FIG. 1, one classical modular processor unit is provided for each node, F, in the viewing window, such that the processor units and communication links together form a 3D lattice including plurality of stacked layers arranged as the decoding graph within the viewing window. In this way, the decoder apparatus is of a simple “3D” architecture allowing fast and local operation.

[0122] In some optional implementations, the apparatus 100 includes controller 102 to control the classical modular processor units 112 of the decoder apparatus 110 to coordinate the progress of the decoding cycle.

[0123] Reference will now be made to FIG. 2A, which shows a detailed schematic illustration of an example of the nodes and edges of a viewing window provided by the classical modular processor units 112 and communication links 114 of the decoder apparatus 110 used in the example apparatus of FIG. 1. As can be seen, the viewing window, W, is constructed based on the decoding graph, G, defined by the quantum error correction code used in the qubit register 104 and the noise model. As can be seen, in the example, the nodes are each associated with an identifier (nodelD), following an ordinal sequence, so as to help the nodes ‘know’ where they are in the viewing window. In the example shown, the nodelDs increase in order with the boundary edges having the lowest values (201 to 218) in the ordinal sequence, followed by the detector nodes having the highest values (219 to 237). Generally also the boundary nodes and detector nodes in higher layers have lower nodelD values than the boundary nodes and detector nodes inlayers lower down, where the higher layers represent more recent measurement rounds. Thus the flow of measurement rounds from more recent to increasingly less recent goes down from the top to the bottom layers in the viewing window. In this way, a node looking at the nodelD of its neighbours, or being aware of a nodelD of another node, will know whether that node represents a later measurement round (if it has a higher nodelD), or a more recent measurement round or a boundary node (if it has a lower nodelD). This example ordering and the use of nodelDs is not in any way limiting. Any suitable mechanism to facilitate nodes in determining relative position in relation to more or less recent measurement rounds, and to prefer boundary nodes over detector nodes, may be helpful in the present disclosure.

[0124] Reference will now be made to FIG. 2B, FIG. 2C and FIG. 2D to illustrate an example syndrome, S, error, E, and correction, C, in the context of the viewing window. It is important to note that this is provided to aid understanding only, and it is not presented in the context of a streaming decoder finding the correction for measurements received in a stream of successive measurement rounds. Instead, FIG. 2B, FIG. 2C and FIG. 2D illustrate an example of the determination of a correction, C, for an error, E, in a batch of measurement rounds (i.e. a collection of measurement rounds corrected together).

[0125] FIG. 2B shows a schematic illustration of the example decoder apparatus 110 flagging defects at detector nodes 222, 226, 229, 231, 232 and 236, as indicated in bold outline. These defects represent an example syndrome, S, for the detector nodes in the viewing window flagging changes in a received measurement bit relative to the previous measurement round, for a series of three successive measurement rounds.

[0126] A possible error, E, that could have given rise to the syndrome, S, is shown by the subset of thick bulk edges and boundary edges. It should be noted that different errors made up of different edges suffering faults, can give rise to the same syndrome, §. As the decoder only ever sees the syndrome, S, and not the error, it cannot reliably infer the error that would have led to the detected syndrome, S. Further, it is not necessary for the decoder apparatus 110 to infer the error, E, (or even any possible error, E) to be able to determine a correction, C, to compensate for the error, E.

[0127] It should also be noted that the boundary nodes 204, 210, 212 and 214 are not defects. Furthermore it should be noted that the detector node 233 is not flagged as a defect. This is because it has two incident edges suffering faults, causing the measurement bit received thereat to flip twice in one measurement round.

[0128] Turning now to FIG. 2C this shows a schematic illustration of an example correction, C, for the error, E, shown in FIG. 2B to be determined by a decoder (using the batch method in this case).

[0129] As noted above, the decoder apparatus 110 (whether a batch decoder, or the streaming decoder apparatus disclosed herein) sees only the syndrome, S. It does not see the error, E.

[0130] Given only the syndrome, S, the task of the decoder is to determine a correction, C, of a subset of edges to be bitflipped in addition to the error, E, that modifies the syndrome, S, until no defects remain (in the detector nodes). That is, until S = 0, the empty or null set. Formally, in the streaming decoder sense, the correction C is the final set of edges the decoder chooses to bitflip; then C must annihilate all defects. It should be noted that the syndrome made by the final correction, C, is always the same as the syndrome made by the error, E. It should also be noted that the correction, C, can include bulk edges that span different layers in the viewing window, W.

[0131] Generally, a decoder will seek to find a correction C, for an error, E, that constitutes paths that pair each defect with either another defect or a boundary node.

[0132] That is when the correction is applied to combine it with the error, E, by bitflipping the edges in the correction, C, the defects due to the error, E, are annihilated or pushed to the boundary.

[0133] In this respect FIG. 2D shows a schematic illustration the leftover, L, after combining the bitflipped edges of the error, E, and the example correction, C, for the error, E, in the example decoder apparatus as shown in FIG. 2B and FIG. 2C. As can be seen, the leftover includes bitflipped edges (suffering faults in the error, and being bitflipped by the correction) but the leftover produces no defects.

[0134] By definition, the leftover, L, always comprises only cycles (i.e. closed loops of bulk edges) or paths of edges between distinct boundary nodes (as shown). A path in the leftover caused by applying the correction that forms a cycle or joins boundary nodes on the same boundary or wall, causes no logical errors in the quantum error correction code.However, a path in the leftover caused by applying the correction that joins boundary nodes on opposite boundaries or walls, such as that between boundary node 212 and boundary node 214, represents a logical bitflip. Where an odd number of logical bitflips occur, or where a single decoding cycle ends with an odd number of logical bitflips leftover, this can indicate that the logical qubit encoded by the quantum error correction code has picked up a logical error. The accuracy of any given batch decoder can be evaluated by the probability asingle batch fails i.e. a single decoding cycle ends with an odd number of logical bitflips leftover.

[0135] Recall that FIG. 2B, FIG. 2C and FIG. 2D illustrate the decoding of a batch of measurement rounds statically captured in a viewing window (i.e. they are not moving constantly through the viewing window as new measurement rounds are received, with the decoders determining a correction on the fly). For a streaming decoder such as the ‘Forward Method’ or the method of the present disclosure implemented in the decoder apparatus 110 described in more detail below in in relation to FIG. 4 and FIG. 6, the decoding problem is defined only two noise models: i.e. phenomenological noise and circuit-level noise. Streaming decoders are not defined for a code capacity noise model alone.

[0136] In this context, unlike in the batch decoding case, a sheet is a subset of nodes of G (or W) with the same t coordinate. A layer is the periodic unit subgraph of G (or W), in that it includes the subset of nodes and edges (including edges joining detector nodes which correspond to a more recent measurement round). For the stream decoding problem, there are an indefinite number of measurement rounds, which means new layers are constantly being added to the top of G (which pass into the viewing window, W, when a buffer is provided).

[0137] In general, some edges in the new layer are bitflipped (specifically, the bitflip probability for each edge equals that of the analogous edge in the layer below), creating defects in the new layer. Unlike the batch decoder, the streaming decoder must constantly add to the correction, C, to annihilate these new defects. Streaming decoder accuracy can be assessed by determining the logical error rate, which is the logical bitflip count per d measurement rounds. This is a reasonable streaming analogue to the batch failure probability.

[0138] Before proceeding to the detailed description of the streaming decoding method disclosed herein, a brief explanation will be made of the so-called ‘Forward Method’ which is known as a decoder for the streaming case. This method was first proposed as the ‘overlapping recovery method’ but it is also referred to as ‘sliding window decoding’. The Forward Method reduces the stream decoding problem to batch decoding by chunking the syndrome, decoding each chunk, then stitching together all the corrections. In this respect, it is effectively a batch decoder that looks at chunks of measurement rounds received over time in isolation, to find a correction therein, and it is not strictly a streaming decoder at all (in the sense that it does not determine a correction by solving for a changing syndromeover time as new measurement rounds get added and existing measurement rounds get increasingly old).

[0139] In the Forward Method, the chunks must overlap, else a small defect pair could straddle two consecutive chunks and hence be decoded inaccurately. More concretely, assume that G already comprises many layers, the Forward Method uses a ‘viewing window’ W that is at any given time a subgraph comprising c+b consecutive layers of G. The lowest c layers of W is always defined as the commit region; the rest defined by b, the buffer region. W starts at the bottom, i.e. as the lowest c + b layers, of G. The method then indefinitely repeats the decoding cycle, defined as the following:1. Use any batch decoder to find a tentative correction, T, that annihilates all defects seen in W.2. Add to the committed correction, C, the part of T in the commit region, and forget the rest.3. Raise IF by c layers i.e. redefine it as the subgraph in G that is c layers higher.

[0140] Since, in the Forward Method, b ‘layers of computation’ are forgotten per decoding cycle, decoding r sheets of syndrome data throws away a total of ~br / c layers of computation. If the bitflip probabilities of all edges of G are of the same order, the chunk overlap b needs to bed (e.g. an arrangement of W in which c = b = d is practical). Thus in the Forward Method, a considerable amount of computation is thrown away leading to a very poor computational efficiency of this ‘chunking batch’ decoder for streaming measurements.

[0141] The structure and methods of operation of the classical modular processor units 112 in accordance with aspects of the present disclosure, for decoding a stream of measurement rounds from qubit register 104 received on the fly, as opposed to decoding a static batch of measurement rounds in the batch decoding or Forward Method, will now be described with reference to FIG. 3, FIG. 4 and FIG. 6.

[0142] FIG. 3 shows a schematic illustration of an example classical modular processor unit 112 in accordance with aspects of the present invention, for use in the example decoder apparatus 110 shown in FIG. 1. In the context of quantum computing, a "classical processor" refers to a conventional computing device or system that uses classical bits for information processing. Unlike quantum processors, which perform operations using quantum bits (qubits) that exhibit quantum mechanical properties such as superposition and entanglement, classical processors operate on binary data, executing instructions based on classical computing principles. The use of the term modular processor unit is intended toindicate that the processor units are able to operate independently and perform local operations, but can work in conjunction with each other in a modular fashion, to provide a scalable architecture, to bring about a desired overall effect. In this respect, the classical modular processor units 112 used in the decoder apparatus 110 may be identical.

[0143] The classical modular processor unit 112 comprises circuitry 112c, memory 112s, and a communications interface 112io each coupled by an internal communications bus (as indicated by the solid line) allowing data and information to be exchanged between them. The nominal outline of the classical modular processor unit 112 as having both a circular outline and an octagonal outline is merely intended to represent that the classical modular processor unit 112 can equally be used as a detector node or a boundary node.

[0144] Broadly, the memory 112s may store data and information for use by the circuitry 112c in carrying out the decoding cycle operations locally to the classical modular processor unit 112. The memory 112s may also store instructions for configuring the circuitry 112c, or for causing the classical modular processor unit 112 to carry out the decoding cycle operations as described in relation to FIG. 4 and FIG. 6.

[0145] The circuitry 112c may be configured to carry out the decoding cycle operations, and in doing so, obtain and store data in the memory 112s, and send and receive information and instructions via the communications interface 112io to the neighbouring classical modular processor units in the viewing window via the communication links 114 (indicated by the dotted lines).

[0146] The communications interface 112io acts as an interface between the communication links 114 and the circuitry 112c and is operable by the circuitry 112c to send and receive data and information to connected neighbour classical modular processor units. Any suitable communication links 114 and point to point communications protocols may be implemented by the communications interface 112io that is efficient and provides low latency.

[0147] The circuitry 112c of example embodiments may comprise: general purpose processing circuitry configurable by program code to perform specified processing function; special purpose processing circuitry configured to perform a specific function via custom design or modification of processing hardware; or both general purpose and special purpose processing circuitry. Configuration of the processing circuitry to perform a specified function may be entirely in hardware, entirely in software or using a combination of hardware design and software execution. Program instructions may be used to configure logic gates of general purpose or special-purpose processing circuitry to perform any givenprocessing function. In the example the circuitry may be configured to perform the decoding cycle operations as described in relation to FIG. 4 and FIG. 6. The program instructions for configuring the circuitry 112c may be stored in the memory 112s.

[0148] The circuitry 112c may be implemented, for example, as a hardware circuit comprising an integrated circuit (IC) such as a custom Very Large Scale Integrated, VLSI, circuit or an Application Specific Integrated Circuit (ASIC) or as gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. The circuitry 112c may also be implemented in programmable hardware devices such as field programmable Gate Arrays, FPGA, programmable array logic, programmable logic devices, a System on Chip, SoC, or the like. The circuitry 112c may alternatively be implemented using optical or photonic components.

[0149] The internal memory 112s may be implemented as an on-chip memory, for example, in part as a cache memory. On-chip memory (e.g. Static Random Access Memory) is relatively small and rapidly accessible to the circuitry 112c.

[0150] As the classical modular processor unit 112 may be provided as a chip that comprises processor circuitry 112c and other components such as the an on-chip memory 112s, the bus, and the communications interface 112io, and so it may be provided as a System on Chip (SoC) or a microcontroller. Both may be designed, manufactured and implemented at scale.

[0151] When arranged as a node in the viewing window W, connected to neighbouring nodes by communication links 114, and assigned an appropriate nodelD to order the viewing window, the circuitry 112c may cause the classical modular processor unit 112 to carry out the methods shown in FIG. 4, FIG. 5A, FIG. 5B, FIG. 6, FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D as described below to implement the streaming decoder disclosed herein.

[0152] Broadly, FIG. 4, FIG. 5A, FIG. 5B, FIG. 6, FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D may be understood to show the frugal method as described herein, which differs from the so-called Forward Method in three key aspects:1. The tentative correction, T, evaluated over time as the decoder apparatus 110 operates decoding cycles as the defects are dropped down layers with each measurement round, need only satisfy the following condition, that T is complete, i.e. annihilates all defects, within the commit region denoted c in FIG. 5A. This is as opposed to being complete in all of W in the batch decoding method or the Forward Method.2. The frugal method decoder apparatus 110 bitflips all edges in the tentative correction, T, modifying the syndrome, S, even in the buffer region denoted b in FIG.5A. This has no physical effect on qubits as C is ultimately only tracked by classical electronics in the so-called Pauli frame.3. The computation associated with the buffer region is not forgotten after the completion of a decoding cycle, but used as a starting point for, and further developed in, the next decoding cycle.

[0153] FIG. 4 shows a flowchart representing an example method 400 for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure. To carry out the method 400, the circuitry 112c of the classical modular processor units 112 is configured for performing a decoding cycle comprising a drop operation 402, a grow operation 404, and a merge operation 406. However, a while loop indicated by decision block 408 returns the process to repeatedly perform the merge operation 406 until it is completed. The method 400 is a cycle in the sense that the method 400 returns to the start again after a merge 406 step is completed, and the viewing window is ‘moved up’ in a drop 402 step to receive the measurement bits from the next measurement round.

[0154] The drop 402, grow 404 and merge 406 operations are performed by all the classical modular processor units 112 in each measurement round, in turn, and in synchrony, the classical modular processor units 112 all progressing to the next operation in the same timestep. In that regard, the classical modular processor units 112 may operate on incremental timesteps. Their synchronisation in these timesteps, and their progression through the operations, may be governed by the classical modular processor units 112 themselves, or in conjunction with the controller 102.

[0155] In particular, the drop 402 and grow 404 operations each take one timestep, but the merge 406 operation may take an undefined number of timesteps to complete, and so the while loop indicated by decision block 408 returns the process to repeatedly perform merging until completion. In this regard, the controller 102 may be configured to communicate with all of the classical modular processor units 112 to monitor when they are in a busy state when the merge 406 operation is still being carried out and is not yet complete, and the controller 102 may communicate with the classical modular processor units 112 to keep performing the merge operation 406 and only allow the decoding cycle to finish, and progress from the merge 406 step back to the drop 402 step when all of the classical modular processor units 112 are no longer busy merging. This coordination of the progression of the decoding cycle from the merge 406 step by the controller 102 may maintain synchrony of each of the classical modular processor units 112 in performing the decoding cycle.

[0156] Broadly, as can be seen from FIG. 5A and FIG. 5B (which show the progress of the streaming decoder apparatus 110 in finding a tentative correction from one decoding cycle to the next, from left to right), and as will be explained in more detail below, the decoding cycle proceeds as follows.

[0157] In a drop 402 operation, the defects (shown as dots), clusters grown around defects (shown as diamonds or ‘snowflakes’ of edges grown at a positive fraction of an edge, the fraction being less than one, per drop around each defect), and the edges in the tentative correction shown as the lines along which the defects are ‘pushed’, are dropped down one layer in the subgraph of G that is the viewing window, W, to add the measurement bits from the next measurement round to the top layer of the buffer region, and to move the last tentative correction and clusters in the last layer of the buffer region into the commit region (which may be a single layer). This has the apparent effect of sliding the viewing window, W, up one layer as shown in FIG. 5A. Indeed, where a queue of more-recent measurement rounds is provided above the buffer region, it may be abstractedly considered as moving a viewing window along the time axis of a queue of measurement rounds to decode a correction for defects flagged therein.

[0158] In a grow 404 operation, all edges in active clusters (i.e. those that contain an odd number of defects that have either not been annihilated, or pushed to a boundary node) are grown by a positive fraction of an edge, the fraction being less than one. In the embodiments described in detail herein, the growth per round is half an edge, but it could have a lower or a higher value. Although each edge may have a growth value of up to only a whole edge, in embodiments the remainder of the growth value may be carried over to the next node when it becomes fully connected. In this way, clusters may be grown more quickly. Edges that are in inactive clusters are no longer grown, although if a cluster that becomes inactive later merges with an active cluster in a merge 406 operation, the inactive cluster can become part of an active cluster again and its edges can begin growing.

[0159] In a merge 406 operation, new active clusters are nucleated around defects in the top layer of the viewing window (although the edges around these may not be grown until the next grow 404 operation), and clusters joined by fully grown edges are merged. It should be noted that a cluster that has become inactive (e.g. one that has been previously grown and become inactive through annihilation of defects or pushing of a defect to a boundary) can become active again if a growing active cluster subsequently merges with it. Then, defects in active clusters are passed along edges to a boundary node joined by a fully connected edge, or otherwise to the 'root', i.e. to the highest point in the cluster joined by a fully connected edge. Where two defects meet (e.g. at the root) they annihilate, to render thecluster marked inactive. Similarly where defects are pushed to boundary nodes (which cannot be defects), the cluster no longer contains any defects and so is marked inactive. The edges along which defects are passed are added to the tentative correction and bitflipped.

[0160] By making the buffer region have sufficient layers (i.e. equal to the code distance), the decoder will always find a correction to remove all defects (by annihilation or passing them to a boundary node) by the time the commit region is reached (which may thus include only a single layer).

[0161] Reference will now be made to the simple examples shown in FIG. 5A and FIG. 5B to illustrate the operation of the frugal method across successive decoding cycles, shown from left to right, for, in the case of FIG. 5 A, a single defect falling through the viewing window, and, in the case of FIG. 5B, two defects falling through the viewing window.

[0162] For visual clarity, the example decoding cycles shown in FIG. 5A, FIG. 5B, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B and FIG. 9C, use a decoding graph G for the repetition code under phenomenological noise (i.e. each ‘layer’ including a ID array of nodes, and the layers being joined by only vertical edges).

[0163] Further, in the case of FIG. 5 A and FIG. 5B, the nodes and the edges are not shown, with only the upper and lower temporal boundaries of the viewing window and the walls (where the boundary nodes are located) being illustrated. The defects are shown as dots.The clusters grown around defects are shown as diamonds or ‘snowflakes’ enveloping edges grown at a positive fraction of an edge, the fraction being less than one, per drop around each defect. The edges in the tentative correction are shown as the lines along which the defects are ‘pushed’.

[0164] In this respect, FIG. 5A shows a schematic illustration of the operation of the apparatus 100 of FIG. 1 for decoding by the decoder apparatus 110, over receipt from the syndrome measurement circuit 108 of successive measurements rounds over time, an error, E, resulting in a single defect in a qubit register 104 encoding a repetition code.

[0165] As can be seen in the lefthand, first viewing window shown in FIG. 5 A, a defect indicated by the dot is shown as entering the buffer region, b, of the viewing window flagged by detector node in the centre of the top layer of the viewing window.

[0166] To the right of that, in the next two viewing windows shown in FIG. 5 A for the next two decoding cycles (n.b. for brevity and ease of understanding, some decoding cycles, may have been skipped in the illustration) a cluster grows around the defect, and the defect is pushed upwards towards the root along fully grown edges, away from the commit region, c, at broadly half the rate at which new measurement rounds are progressed through theviewing window. N.B. the rate may be different if the clusters are grown along edges at a rate different to half an edge per growth round.

[0167] To the right of that, in the next, fourth viewing window shown in FIG. 5 A, it can be seen that the cluster has dropped further and has grown more so that it now touches the walls and boundary nodes on each side at the level of the commit region. The defect is now pushed to the boundary node, rendering the cluster inactive and giving a correction, C, for the defect of bitflipped edges that, in the last viewing window shown to the right of that in FIG. 5A, pass through the commit region, c, and out of the viewing window to be committed to the correction for the measurement rounds.

[0168] The buffer region b includes only 2*floor(t / / 2) layers where d is the code distance of the quantum error correction code. In this arrangement, the edges in the tentative correction, T, committed to the correction, C, in the commit region, are always complete in that all defects in the commit region are annihilated (or pushed to boundary nodes). In examples, c = 1, such that W consists of a minimised number of 2*floor(t / / 2) + 1 layers. In this way, the size of the buffer, and the complexity of the architecture, can be minimised while ensuring all errors accounted for in the noise model are decoded, allowing fast and efficient decoding.

[0169] For the examples shown herein, the number of layers in the commit region is set as c = 1, which can be done for free as the computation in the buffer region is never thrown away. Here the commit region is a commit layer, and references to both may be used interchangeably herein. In this case the method becomes local (provided the decoder itself is local) as, from the perspective of IF, data shifts down by one layer when W is raised. The commit region is also one layer thick, so the part of C here can be offloaded from the bottom of IF locally. Conceptually, this makes the method much more granular in nature.

[0170] It should be noted that, in FIG. 5A, the viewing window is shown as moving along the measurement rounds in the time axis, to illustrate the concept. However, in practice, as shown in FIG. 5B, it is the measurement rounds and the related data that is passed down through the layers of the viewing window provided by the classical modular processor units 112.

[0171] Thus, FIG. 5B shows a schematic illustration of the operation of the apparatus 100 of FIG. 1 for decoding by the decoder apparatus 110, over receipt from syndrome measurement circuit 108 of successive measurements rounds over time, an error, E, resulting in two defects in a qubit register 104 encoding a repetition code.

[0172] As can be seen in the lefthand two viewing windows shown in FIG. 5B, two defects indicated by dots are shown as entering the buffer region, Z>, from the top layer of the viewing window one after the other in successive measurement rounds. In the decoding cycles, clusters are grown around the two defects, and the defects are pushed to the root (highest point joined by a fully connected edge) of each cluster.

[0173] Then, to the right of that, in the third viewing window shown in FIG. 5B, it can be seen that the two clusters have grown to become connected by fully grown edges, and so they merge. At this point the defect from the first (lowest) cluster that was merged is pushed (albeit, in examples, in the decoding cycle after the clusters are merged) to the node at the root of the merged cluster, at which point it annihilates the other defect. It should be noted that the topmost vertical edge, along which the defect is passed en route to annihilation, is no longer in the tentative correction, T, as it has had two defects passed along it, and so it is bitflipped twice.

[0174] The operation of the decoding cycle will now be described in more detail in relation to FIG. 6. Reference will also be made to example implementations of the decoding cycle shown in FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D.

[0175] FIG. 6 shows a flowchart representing, in more detail than FIG. 4, a further example method implemented by the example decoder apparatus 110 under coordination control by the controller 102 for finding a correction, C, to an error, E, detected in measurements of a qubit register 104 in accordance with aspects of the present disclosure. Although the example method 600 depicts a particular sequence of operations, the sequence may be altered without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different sequence that does not materially affect the function of the method 600. In other examples, different components of an example device or system that implements the method 600 may perform functions at substantially the same time or in a specific sequence.

[0176] To implement this broad frugal method, the classical modular processor units 112 are configured to store between them (for example using each memory 112s local to each classical modular processor unit 112 storing relevant local and global attributes) information on: the location of defects; clusters of edges grown around defects within which a correction to the errors causing the defects is sought; and a tentative correction, T, to the error for each cluster to be determined by the processors units as the clusters stream through the viewing window.

[0177] Thus, in more detail, in the method 600 implemented in decoder apparatus 110 includes, in the drop 402 operation, at step 602, dropping stored information down one layer of the viewing window, to receive the new measurement round in the top layer of the viewing in step 604. The dropped information from a node in one layer to the corresponding node in the next layer down may be the information stored locally in the memory 112s on: the location of defects (i.e. whether the node is a defect); clusters of edges grown around defects within which a correction to the errors causing the defects is sought (i.e. the stage of growth of the edges around the node); and a tentative correction, T, to the error (i.e. whether the edges around the node are in the tentative correction). As will be explained in more detail below, in examples, the dropped information may also include other relevant information such as the status of whether or not the node is in an active cluster may also be dropped, the identity of the cluster the node is in (e.g. identified by the nodelD of the lowest order node at which the root is located), and pointer information indicating the direction along which the node should push a defect. The classical modular processor units 112 may also store in relation to each nodes information on which edges are ‘owned’ by the node, for which the node stores information. The storage and dropping of this additional information may enable a local operation of the method 600.

[0178] The method 600 then includes, in the drop 402 operation (shown in a dotted outline in FIG. 6), at step 604, receiving a set of measurement bits for the most recent measurement round. The set of measurement bits is derived from measurements of a stabilizer code (which is the error correction code) for the most recent measurement round. Each measurement bit in the measurement round is for a given ancilla qubit in the qubit register being received and stored at one of the subset of detector nodes, VD, in a first, top layer of the viewing window.

[0179] The method 600 then includes, in the drop 402 operation, at step 606, the classical modular processor units 112 flagging defects at detector nodes, VD, where a measurement bit flips relative to the previous measurement round. A defect is flagged at a detector node in the top layer of the viewing window by a classical modular processor unit when an odd number of edges, E, incident on a node experience faults in that measurement round (or are otherwise bitflipped by a tentative correction or committed correction).

[0180]

[0181] The performance of step 602 and step 604 may be simultaneous by each of the classical modular processor units 112 locally performing a ‘drop’ operation in synchrony tomove the viewing window ‘up’ and forward in time to include the next newest measurement round. The step 606 flags new defects, in particular arriving in the top layer.

[0182] The method 600 then includes, in the grow 404 operation, at step 608, growing active clusters along all available edges by a positive fraction of an edge, the fraction being less than one at step 608. In step 608 in particular, the edges are grown by half an edge each decoding cycle. However, in other embodiments, a different rate of growth may be chosen, and the growth rate may vary for different edges. The method 600 performs one growth round per decoding cycle. The result of this is that, in the method shown, clusters grow at half the rate they fall through the viewing window. This information may be stored by the classical modular processor units 112 at each node in relation to its owned edges as a growth value which may be 0, ’A, or 1. The growth value for owned edges may increase by ’A in each growth step up to a maximum of 1. This occurs only where the node is indicated as being in an active cluster. Where the node is not in an active cluster (either through not being in a cluster, or being in an ‘inactive cluster’), the growth value is not grown in step 608. Strictly speaking, each node may be technically considered to be always in a cluster, in that, even if a node has all its incident edges ungrown, then it can be considered to be just in its own cluster. The growth value for owned edges (whether or not the node is in an active cluster) may be dropped by each node in step 606 to cause the grown cluster or ‘snowflake’ to fall down the viewing window. It should be noted that, in FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B and FIG. 9C, half-grown edges having a growth value of ’A, are shown as dotted lines, fully grown edges having a growth value of 1 are shown in unbroken, unbolded lines (where the arrowhead indicates a stored pointer direction), and edges having a growth value of 0 are not shown. It should be noted that the growth value of an edge is not indicative of whether or not that edge is in the error, E, and has suffered a fault that has led to a defect, nor that it is in the tentative correction, T. Instead, the edges along which defects have been pushed and so which are bitflipped and in the tentative correction, T, are indicated in FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B and FIG. 9C by the unbroken, bolded lines (where the arrowhead indicates a stored pointer direction).

[0183] The method 600 then includes, in the merge 406 operation, at step 610 nucleating new active clusters at defects in the top layer of the viewing window. This marking of flagged defects in the top layer of the viewing window as being ‘active’ (i.e. to nucleate new active clusters thereat) can occur after the drop 402 operation and the grow 404 operation, such that the edges around the newly active clusters flagged in the top layer in a decoding cycle are not grown in that decoding cycle.

[0184] The method 600 then includes, in the merge 406 operation, at step 612, merging together clusters (which may include clusters that have become inactive) that become joined by a fully grown edge at step 612. This may be achieved by the nodes in the merged cluster updating their clusterlD to match the nodelD of the highest node in the cluster (i.e. the node having the lowest order nodelD), or the nodelD of a boundary node (which generally have lower order nodelDs than detector nodes). This may be achieved by propagation along fully grown edges in the merged cluster, based on pointer directions.

[0185] The method 600 then includes, in the merge 406 operation, at step 614, passing defects along fully grown edges towards boundary node or otherwise highest detector node. This passing of defects can be based on locally stored information about edge growth values and pointer directions along which defects should be passed in a cluster.

[0186] The method 600 then includes, in the merge 406 operation, at step 616, storing / removing any edges along which defects are passed in a tentative correction, T. That is, for any edges along which defects are passed during syncing, attributes indicating whether those edges belong in the tentative correction, T, are flipped. Thus, in this way, the edges added to the tentative correction, T, may be bitflipped. An edge having a defect passed along it once is bitflipped and added to the tentative correction, T. If an edge has had a defect passed along it twice, and so it has been bitflipped twice, it is no longer in the tentative correction. This way, the tentative correction, T, is the symmetric difference of all the paths traced by defects and moreover is guaranteed to be complete within any inactive cluster.

[0187] The method 600 then includes, in the merge 406 operation, at step 618, annihilating defects at nodes at which two defects meet at step 618. That is, a detector node flagging a defect, (i.e. storing a defect attribute of TRUE) that is passed another defect, may update its defect attribute to FALSE. Similarly, defects passed to boundary nodes cease to exist as boundary nodes cannot be defects.

[0188] The method 600 then includes, in the merge 406 operation, at step 620, marking any clusters inactive that no longer contain any defects. This has the result that, the inactive cluster no longer grows in the next decoding cycle (and in subsequent timesteps unless it becomes active again). The decoder apparatus 110 is configured such that all clusters are inactivated once they have fallen far enough, and such that a correction to all defects arising in the cluster is found before the edges in the tentative correction, T, reach the commit region.

[0189] That is, the height of the buffer region, b, is lower-bounded by the condition that the tentative correction, T, must be complete (i.e. with the effect that all defects are annihilated by being combined or passed to a boundary node) within the commit region. The minimum layer count, b, of the buffer region that guarantees this condition, is 2*floor(t / / 2), i.e.: bmin 2|_d / 2j

[0190] The reason for this lower bound is that, as defects are annihilated by either meeting another defect or being pushed to a boundary node, the longest-living defect is one like that in FIG. 5A never meets another defect, and is created as far as possible from any boundary node. The decoder apparatus 110 operating method 600 will find a correction for this defect in the time taken for the cluster grown around this defect to touch the boundary and form a fully grown edge with a boundary node, allowing the defect to be passed to the boundary node. As the cluster containing this defect grows outward by half an edge per growth round, it will touch a boundary after Z>min growth rounds, i.e. at the (Z>min + l)thlayer from the top. So the tentative correction, T, is always complete in this layer and below, but not above. In a local implementation the height of the buffer region b can be set to Z>min, and the height of the commit region, c, can be set to 1. Where the growth rate is different to a half an edge, the minimum size of the buffer region may be different.

[0191] It should be noted that step 610 can be omitted if, in step 620 clusters that contain a defect and do not contain a boundary node are also marked active. This is because each node in the viewing window is always part of a cluster (even if it strictly has no grown edges). The addition of marking active clusters to the step 620 means that step 610 is performed in the next decoding cycle.

[0192] The method 600 then includes, in the merge 406 operation, at step 622, in the commit region, committing edges flagged in the tentative correction, T, to be (permanently) bitflipped to form part of correction, C. That is, edges already bitflipped in the tentative correction, T, are frozen in the committed correction, C, to decode the error, E, in the measurement rounds that have passed through the viewing window, W.

[0193] It should be noted that, as indicated by the circular looped arrow behind the steps 610 to 622, each classical modular processor unit 112 carries out these steps in the merge 406 operation effectively in a while loop until completed for each node and no node is busy. That is, the passing of a defect from one node to the next throughout a cluster means that thesyncing procedure can take a number of timesteps to be performed across the nodes. Similarly, where information needs to be spread throughout a cluster, it is passed from one node to the next through nearest neighbour only communications. Hence it can take multiple timesteps to proceed to completion.

[0194] In this way, the present disclosure provides an apparatus implementing a local decoder in the fully streaming case. By local, it is meant running on the grid or lattice of identical classical modular processor units 112, each communicating only with their nearest neighbours. In this way, the decoder benefits from parallelism, hardware practicality and robustness when used with local (requiring no long-range qubit-qubit interactions) codes.

[0195] Further, as the apparatus and method disclosed herein discards none of the computation, it is more frugal with resources.

[0196] Ideally, each the decoder apparatus 110 would be configured such that each decoding cycle would complete faster than the interval between the measurement rounds of ancilla qubits. This may not always be achievable, as, for example, the merge 406 operation may take a variable number of timesteps. In practice, less can be demanded from the decoder by introducing a measurement queue (acting as a buffer in the conventional sense) between the newest measurement data and the top of W. Where a measurement queue is provided in the decoder apparatus 110 for storing measurement bits from measurement rounds of the qubit register, the decoder apparatus 110 may receive (e.g. at the classical modular processor units 112 providing the top layer of nodes) and store in a queue measurement bits from consecutive measurement rounds completed for the qubit register. Responsive to the completion of a decoding cycle, the decoder apparatus 110 may pass to the top layer of the detector nodes in the viewing window, W= (V, E), the measurement bits from the oldest measurement round stored in the queue to provide the new measurement round for the next decoding cycle. In this way, the apparatus can store a queue of measurement rounds before being passed to the decoder, allowing each decoding cycle to take a variable time to complete, while also ensuring the errors can be sufficiently removed from the system provided the average decoding cycle is shorter than the average time between measurement rounds of the qubit register. That is, where a measurement queue is provided, the decoder apparatus 110 may merely need to be configured such that the average time taken to complete a decoding cycle is shorter than the average time between measurement rounds of the qubit register. If the decoder apparatus 110 operates any slower than this, then the backlog of syndrome data grows indefinitely.

[0197] It should be noted that the steps 610 to 622 making up the merge 406 operation may be performed in an order different to that shown in FIG. 6, in sequence or in parallel. Further, the steps 610 to 622 making up the merge 406 operation may be grouped into subroutines, referred to as ‘syncing’ and ‘flooding’, as described below in relation to FIG. 7D, which may be performed in any order.

[0198] The method 600 may be implemented by algorithms operating locally at each classical modular processor unit. That is, each classical modular processor unit 112 may further comprise circuitry 112c configured to perform the decoding cycle by carrying out the drop, grow and merge operations local to that processor based only on the information stored thereat and only by communication with its nearest neighbour processor nodes only. In this way the apparatus of the present disclosure implements a truly local architecture with operations in the decoding cycle being performed in parallel independently and simultaneously by an array of identical classical modular processor units. This provides a fast and scalable streaming decoder. Further, multiple identical classical modular processor units can be used that can be easily and scaleably produced and assembled to implement a streaming decoder.

[0199] In this regard, detailed algorithms for a local implementation of the method 600 at each classical modular processor unit 112 will now be described with reference to the pseudocode shown in FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D.

[0200] FIG. 7 A shows in Algorithm 1 example pseudocode for operating the controller 102 to control the classical modular processor units 112 to coordinate the progress of the decoding cycle of the methods shown in FIG. 4 and FIG. 6.

[0201] The decoder apparatus 110 may be configured such that the classical modular processor units 112 independently perform the drop, grow and merge operations in turn and synchrony. The classical modular processor units 112 may be configured to independently perform the drop, grow and merge operations in successive, discrete and synchronised timesteps, the drop and grow operations each taking one timestep, the merge operation taking an undetermined number of timesteps. To facilitate this, the controller 102 may be coupled to the classical modular processor units 112 and configured perform Algorithm 1 to send an instruction to the classical modular processor units 112 to cause the nodes to perform a drop operation after three timesteps unless any of the nodes are still busy merging.

[0202] Although the decoder apparatus 110 of FIG. 1 uses a local architecture i.e. a processor for each node in the viewing window, with a communication link for each edge,the controller 102 manages the global variables of the algorithm. The controller 102 can broadcast the same boolean to, and receive (without knowing the sender) booleans from, every node. The apparatus 100 is compatible with any choice of network for communication between the controller 102 and the classical modular processor units 112, be it a hierarchical tree or a strictly local staging and signalling tree, with synchronous or asynchronous logic. The local implementation described herein is such that the controller 102 and the classical modular processor units 112 follow discrete timesteps with each component in the network performing one operation, and messages travelling one link, per timestep.

[0203] Specifically, by Algorithm 1, in each timestep the controller 102 tells all nodes to start a new decoding cycle if none of them are busy during perfoming a merge 406 operation. This is the only time the controller 102 needs to communicate with the nodes, as the merge 406 operation is the only stage to last a variable number of timesteps; while the other two drop 402 and grow 404 operations last exactly one timestep. In this way, the independent, locally operating, identical classical modular processor units 112 may be coordinated in their operation of the decoding cycle.

[0204] FIG. 7B shows in Algorithm 2 example pseudocode for operation locally at each node by the classical modular processor units 112 for progressing the decoding cycle of the methods shown in FIG. 4 and FIG. 6.

[0205] At the same time, each classical modular processor unit 112 runs Algorithm 2 for each node, v, which calls procedures in the correct staging from Algorithm 3 shown in FIG. 7C. As can be seen, Algorithm 2 effectively provides that, unless the controller 102 commands the classical modular processor units 112 to proceed to the drop 402 operation and grow 404 operation, each classical modular processor unit 112 repeatedly performs a merge 406 operation each timestep. Together with Algorithm 1, this implements the while loop in decision block 408 for each classical modular processor unit 112.

[0206] FIG. 7C shows example pseudocode for operation locally at each node by the classical modular processor units for implementing the drop operation, grow operation and merge operation procedures of the methods shown in FIG. 4 and FIG. 6.

[0207] For local operation, each classical modular processor unit 112 may comprise memory configured to store local to each node the information on defects, clusters and the tentative correction as attributes including: whether the node has a defect; whether the node is in an active cluster; which cluster the node belongs to based on a unique cluster identifier, CID; and, for each edge owned by the node: a growth value; and whether the edge belongs in the tentative correction, T. Further, each node may store a unique node identifier,wherein the detector nodes higher in the viewing window may have a lower ordinal node identifier than detector nodes lower in the viewing window, and wherein the boundary nodes may have lower ordinal node identifiers than the detector nodes, and wherein the node identifiers may be used by the nodes as a basis for passing defects towards the highest node fully connected to an active cluster, and for flooding so that each node in an active cluster knows, through its cluster identifier, the ordinal node identifier of its root.

[0208] In detail, as shown in FIG. 2A, FIG. 8A and FIG. 9A, each node v G Vw is assigned a unique integer nodelD (v.ID) according ordered to the scheme outlined above, and stores the following variables as attributes of the node: activeThis is a boolean indicating whether the cluster that the node v is in is active. If v. active = true, v is said to be active.CIDThis is an integer indicating the cluster that v belongs to. Clusters are identified by the lowest ID of all its nodes. The node of this ID is the root. CID can also adopt the value reset to indicate v should “unroot” (as described below) in the next timestep. de fectThis is a boolean indicating whether v has a defect. This can be thought of as a particle which is passed between nodes. When a node receives two defects in a timestep, they annihilate. pointerThis is the direction v should push the defect (by bitflipping the corresponding edge). Possible values (under circuit-level noise) are C, N, W, E, S, D, U, NU, WD, EU, SD, NWD, SEU, representing respectively centre, north, west, east, south, down, up, and combinations thereof. Following the pointers starting from v should eventually lead to the root of the cluster that v is in (whether it is the highest fully connected detector node or a boundary node). Only roots have pointer = C as they do not push defects but accumulate them. unrootedThis is a boolean indicating whether v has unrooted in the current decoding cycle. busyThis is a boolean indicating whether v is busy. stageThis is the current stage of operation of the node in the decoding cycle: drop, grow, and merging, which repeat in that order once per decoding cycle.The first four variables (active, CID, defect, and pointer) as relative variables and the last three variables (unrooted, busy, and stage) as absolute.

[0209] Each edge e E Ew has the following variables: growthThis is the growth value of the which is in {0, ’ , 1 }. Two clusters touch when they become connected via a fully grown edge. correctionThis is a boolean indicating if e E T (the tentative correction).

[0210] These edge-related variables are stored as additional relative variables at the endpoint node of the edge with the lower nodelD. In this regard, the owned edges can be defined as those edges whose variables a node stores: i.e. v.owned := {uv : uv E Ew and v.ID < M.ID}

[0211] Now, given these stored variables in the local implementation, and referring to the procedures for Algorithm 2 shown in Algorithm 3 in FIG. 7C, it can be seen that the procedure for the drop 402 operation adds to the correction, C, (although this is shown in FIG. 6 as happening at the end of the merge 406 operation, it can similarly happen at the start of the drop 402 operation) and raises IF by one layer. Each node, v, in the top sheet of the viewing window, IF, starts in its own cluster, thus sets its relative variables to reflect this (see Lines 10 and 11 of Algorithm 3). v.CID and v. pointer need not be explicitly reset as they never change from their correct values of v.ID and C, respectively.

[0212] It can be seen that, in Algorithm 3, the procedure for the grow 404 operation grows all edges around each active cluster by A.

[0213] It can be seen that, in Algorithm 3, the procedure for the merge 406 operation comprises two processes, syncing and flooding, which occur independently and can in principle occur in either order. However, in Algorithm 3, the merge 406 operation includes a syncing procedure, then a flooding procedure, which will be described in relation to Fig.7D /

[0214] FIG. 7D shows example pseudocode for operation locally at each node by the classical modular processor units for implementing the syncing and flooding subroutines of the merge operation of the methods shown in FIG. 4 and FIG. 6

[0215] In the procedure for the flooding subroutine, newly touching clusters adopt the lowest CID among them (effecting the merging of touching clusters in step 612). This CID propagates as a flood starting from where they touched: each node looks at its neighbours along fully grown edges. If it sees a lower CID than its own, it adopts that CID and updates its pointer to point toward that neighbour (see lines 28 to 31 of Algorithm 4).

[0216] After this process, all nodes in a given cluster will have the same CID, and following the pointers will always lead to the root promised by CID.

[0217] As noted above, the classical modular processor units 112 are configured such that the boundary nodes are of lower nodelD v.ID than detector nodes. Each root can thus determine if its cluster touches a boundary by checking if itself is a boundary node.

[0218] In the procedure for the syncing subroutine, all defects are pushed along pointers toward roots, one edge per timestep (see lines 8 to 10 of Algorithm 4, effecting the step 614 in method 600). Eventually, each root will know whether its cluster is active or inactive, a cluster being inactive if and only if its root has an even defect count or if it is a boundary node (see line 4 of Algorithm 4). At the same time, this activity knowledge propagates in the opposite direction from root to the rest of the cluster (see line 7 of Algorithm 4). After this process, a node is in an active cluster if and only if it is active.

[0219] Note that it is possible to swap the order of the two subroutines in merging to perform flooding first, before syncing, which speeds up the merge operation overall, as pointers are updated before being used to push defects and backpropagate activity. However, the order presented in Algorithm 3 is technically more straightforward to implement in hardware, and so in the ordering of the merging subroutines in Algorithm 3, syncing is performed using pointers from the previous timestep.

[0220] In accordance with the local implementation, for example as set out in the algorithms in FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D, the apparatus allows the operations making up the decoding cycle to find the correction to the error to be performed independently and in parallel by local operations at each classical modular processor unit.

[0221] Algorithms 3 and 4 shown in FIG. 7C and FIG. 7D also incorporate unrooting, a process unique to the decoder apparatus 110 in this local implementation. Unrooting is a technique used when a downward pointer is dropped to the bottom sheet of W (which can happen while a cluster falls out of view). This breaks the pointer tree structure established inthe previous decoding cycle, as 3 nonempty S c Vw from which following the pointers will lead past the bottom of W. The unrooting fixes this, by which each node in S resets its CID and pointer so that the pointer tree structure can be rebuilt from scratch, via further merging timesteps.

[0222] When unrooting occurs, the breaking point in the tree structure is found before merging (see Algorithm 3 Line 17) whence the signal to unroot, i.e. CID = reset, propagates during merging as a flood through the cluster. In this way, each node in the cluster unroots itself as soon as it receives this signal (see Algorithm 4 Lines 20 to 27). It takes two timesteps for a node to unroot, after which it cannot unroot again in the same decoding cycle (see Algorithm 4 Line 22). This ensures the flood does not backpropagate. The memory of whether a node has unrooted resets after each merging stage (see Algorithm 3 Line 2).

[0223] The higher up a node is in W, the lower its ID; this is for two reasons. First, it makes unrooting less likely as pointer paths tend to lead upward rather than downward. Second, it ensures defects in active clusters are pushed to a highest point so they can annihilate with defects in newer, smaller clusters as early as possible.

[0224] Thus, in examples, the processor units may be configured such that, in the merge operation, each node in an active cluster is configured to iteratively perform in successive timesteps until completion: firstly, syncing, by which the defects are passed along fully grown edges towards any boundary node fully connected to the active cluster, or otherwise towards the highest node fully connected to the active cluster, by which, for any edges along which defects are passed during syncing, attributes indicating whether those edges belong in the tentative correction, T, are flipped, by which any nodes receiving two defects causes the defects to annihilate, and by which the cluster is marked inactive and no longer grows in the next decoding cycle (and in subsequent timesteps unless it becomes active again) if it no longer contains any defects or if a defect has been passed to a boundary node; and secondly, flooding, by which the cluster identifier of the node is updated to indicate a node identifier of the highest node fully within the cluster.

[0225] As the syncing and flooding subroutines, and the unrooting, can each take a variable number of timesteps, the duration of the merge 406 operation is undefined and the decoding cycle cannot be progressed by the controller 102 if any nodes are indicated as busy merging.

[0226] To illustrate the operation of the Algorithms for local operation set out in FIG. 7 A, FIG. 7B, FIG. 7C and FIG. 7D, a detailed illustration of the progression of the operation ofthe different stages of the decoding cycle will now be shown in FIG. 8A and FIG. 8B for decoding two defects, and in FIG. 9A, FIG. 9B, and FIG. 9C for decoding a single defect. This is similar to the cases illustrated in FIG. 5A and FIG. 5B.

[0227] It should be noted that, in FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, and FIG. 9C, boundary nodes are indicated by circles along the walls and have the lowest nodelDs (in this code, detectors are provided above the top layer of detector nodes), the remainder of the nodes being detector nodes also indicated by circles containing increasing nodelDs for lower layers. Defects are indicated by dark shaded detector nodes, and active nodes are squares. Half-grown edges having a growth value of ’A, are shown as dotted lines, fully grown edges having a growth value of 1 are shown in unbroken, unbolded lines (where the arrowhead indicates a stored pointer direction), and edges having a growth value of 0 are not shown. The edges along which defects have been pushed and so which are bitflipped and in the tentative correction, T, are indicated by the unbroken, bolded lines (where the arrowhead indicates a stored pointer direction).

[0228] FIG. 8A shows a sequence of panes (A)-(I) illustrating the progress of an example operation of the apparatus 100 of FIG. 1 to decode an error, E, resulting in two defects in a qubit register 104 encoding a repetition code having a code distance of five. FIG. 8B shows a sequence of panes (J)-(Q) illustrating the further progress of the example operation of the apparatus 100 as shown in FIG. 8 A. It should be noted that, in this example, in the merge operation, flooding is shown as occurring before syncing. Further, it should be noted that, in this example, the top layer of detector nodes has boundary nodes above it.

[0229] In the first decoding cycle shown in panes (A) to (C), in the drop operation a first defect enters the viewing window, IF, at the detector node having nodelD 15, but it is not yet marked as active until the merge operation, and so no edges are grown around it in the grow operation.

[0230] In the second decoding cycle shown in panes (D) to (F), the first defect is dropped down to the node having nodelD 19 in the second layer, and the edges incident on it are grown to have a growth value of ’A, to form the beginnings of a grown cluster. Nothing happens to the cluster in the merge stage because it only includes nodelD 19 and half-grown edges that do not connect to any other node. At the same time, a second defect enters the viewing window, W, at the detector node having nodelD 16, but it is not yet marked as active until the merge operation, and so no edges are grown around it in the grow operation.

[0231] In the third decoding cycle, shown in panes (G) to (K) the first defect is dropped down to the node having nodelD 23 in the third layer, and the edges incident on it are grownto have a growth value of 1, to form a cluster having fully grown edges connected to nodes having nodelDs 19, 22, 24 and 27. Through the successive stepping through of the merge operation, the nodes having nodelDs 19, 22, 23, 24 and 27 direct their pointers to nodes to which they are fully connected that have the lowest nodelD, and copy that nodelD to CID for the cluster (shown replacing the CID for each node in the cluster), such that, by pane (J), each node in the cluster has been flooded to have a CID of 19 (the nodelD of the root node, 19), and is pointing through a pointer tree structure towards the root node 19. Then, in the next steps of the merge operation, as shown in pane (K), syncing has caused the defect to be pushed upwards along the edge to the node having nodelD 19 (adjacent the second defect at nodelD 20), and that edge is bitflipped and added to the tentative correction, T. At the same time, the second defect is dropped down to the node having nodelD 20 in the second layer, and the edges incident on it are grown to have a growth value of ’A, to form the beginnings of a grown cluster. Nothing happens to the cluster in the merge stage because it only includes nodelD 20 and half-grown edges that do not connect to any other node. Note that, in this decoding cycle, the merge operation has taken more timesteps than in the previous decoding cycles.

[0232] In the fourth decoding cycle, shown in panes (L) to (Q) the first defect at the root of the first cluster is dropped down from the node having nodelD 19, to where it had been passed, to the node having nodelD 23 in the third layer. The first cluster of grown edges is also dropped down one layer (and the CID is updated for all nodes in the cluster to correspond to the nodelD of the new root, i.e. 23). The same happens with the second defect, which is dropped to the node having nodelD 20, and the second cluster. The edges around both the first and second clusters are grown again in the growth operation by ’A, such that the first and second cluster are connected by a fully connected edge, so that they can become merged. In the merge operations in panes (N) to (Q), the pointers are updated and the second defect is pushed (in pane (O)) up to the node that is new highest root having a nodelD 20, adding that upward edge to the tentative correction, T. The CID is updated across the merged clusters, such that by pane (P), the CID for all fully connected nodes in the cluster is 20. Then, as shown in panes (P) and (Q), the first defect is pushed along the pointers in the cluster to the root node having nodelD 20, first bitflipping and adding the horizontal (East) edge to the tentative correction, T. Then, in pane (Q) the first defect is passed up the same upward edge as the second defect to the node having nodelD 20, bitflipping again the edge and removing it from the tentative correction, T. At the node 20, the first and second defects annihilate, causing the cluster to become inactive.

[0233] From there, in subsequent decoding cycles, as the merged cluster falls, it does not grow, but the Up and East edges in the tentative correction, T, are committed to the correction, C, when they reach the fifth, commit layer. Note, that, as the repetition code is distance 5, the commit layer is the fifth layer and the viewing window is 4+1 = 5 layers high.

[0234] FIG. 9A shows a sequence of panes (A)-(I) illustrating the progress of an example operation of the apparatus 100 of FIG. 1 to decode an error, E, resulting in a single defect in a qubit register 104 encoding a repetition code having a code distance of four. FIG. 9B shows a sequence of panes (J)-(Q) illustrating the further progress of the example operation of the apparatus as shown in FIG. 8A. FIG. 9C shows a sequence of panes (R)-(X) illustrating the further progress of the example operation of the apparatus as shown in FIG.8 A and FIG. 8B;

[0235] Like in the previous example, in the first decoding cycle shown in panes (A) to (C), in the drop operation a single defect enters the viewing window, IF, at the detector node having nodelD 11, but it is not yet marked as active until the merge operation, and so no edges are grown around it in the grow operation.

[0236] From there, in the second decoding cycle shown in panes (D) to (F), the defect is dropped down to the node having nodelD 14 in the second layer, and the edges incident on it are grown to have a growth value of U, to form the beginnings of a grown cluster. Nothing happens to the cluster in the merge stage because it only includes nodelD 19 and half-grown edges that do not connect to any other node.

[0237] In the third decoding cycle, shown in panes (G) to (K), the defect is dropped down to the node having nodelD 17 in the third layer, and the edges incident on it are grown to have a growth value of 1, to form a cluster having fully grown edges connected to nodes having nodelDs 14, 16, 18 and 20. Through the successive stepping through of the merge operation, the nodes having nodelDs 14, 16, 17, 18 and 20 direct their pointers to nodes to which they are fully connected that have the lowest nodelD, and copy that nodelD to CID for the cluster (shown replacing the CID for each node in the cluster), such that, by pane (J), each node in the cluster has been flooded to have a CID of 14 (the nodelD of the root node, 14), and is pointing through a pointer tree structure towards the root node 14. Then, in the next steps of the merge operation, as shown in pane (J), syncing has caused the defect to be pushed upwards along the edge to the node having nodelD 14, and that edge is bitflipped and added to the tentative correction, T.

[0238] In the fourth decoding cycle, shown in panes (L) to (N), the defect at the root of the cluster is dropped down from the node having nodelD 14, to where it had been passed, to the node having nodelD 17 in the third layer. The first cluster of grown edges is also dropped down one layer (and the CID is updated for all nodes in the cluster to correspond to the nodelD of the new root, i.e. 17). The edges around the cluster are grown again in the growth operation by U, but no further edges become fully connected. As a result, nothing happens to the cluster in the merge stage.

[0239] In the fifth decoding cycle, shown in panes (O) to (X), the defect is dropped down to the node having nodelD 20 in the fourth layer, and the half-grown edges around the cluster are grown to have a growth value of 1, to form an enlarged cluster having fully grown edges connected to boundary nodes having nodelDs 8 and 9 (see pane (P)). Through the successive stepping through of the merge operation, the nodes within the enlarged cluster begin, step-wise, to update their pointers to direct them to nodes to which they are fully connected that have the lowest nodelD, and begin to update their CID to the lowest nodelD for fully connected edges. As can be seen, this connected leads to some competition as nodes (such as node 20) nearest the highest node having nodelD 17, begin to direct their pointers upwards towards node 17 and pass the defect upward bitflipping and adding that upward edge to the tentative correction, T. At the same time, nodes, nearest the node having the lowest nodelD (i.e. boundary node 8) representing the true root for the cluster at the boundary, begin to point their pointers West in a tree structure towards the boundary node having the nodelD 8. This can be seen to progress in panes (Q) to (S).

[0240] However, by the time of the merge operation shown in pane (T), the highest detector node 17 having the defect, becomes aware of the true root of the boundary node 8, and it points its pointer down, to join the tree structure of pointers pointing West to the boundary node 8. Following this, as shown in panes (U) to (X), the defect is passed back down the edge it was passed up, bitflipping that edge again and removing it from the tentative correction, T, and then it is passed, following the pointer tree structure, West, Down and West again to arrive at the boundary node having nodelD 8 in pane (X), with the West, Down and West edges being bitflipped and added to the tentative correction, T. As boundary nodes cannot be defects, the defect is annihilated.

[0241] From there, in subsequent decoding cycles, as the merged cluster falls, it does not grow, and the Up, West, Down and West edges in the tentative correction, T, are committed to the correction, C, in the bottom commit layer of the viewing window, W. It should be noted that, following these timesteps, as a downward pointer passes to the bottom of theviewing window, W, the unrooting process is triggered to rebuild the tree structure for the cluster even though it is inactive.

[0242] As noted above, for visual clarity, the example decoding cycles shown in FIG. 5A, FIG. 5B, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B and FIG. 9C, use a decoding graph G for the repetition code under phenomenological noise (i.e. each ‘layer’ including a ID array of nodes, and the layers being joined by only vertical edges). However, the same concepts and the streaming decoder apparatus and method disclosed herein apply to other graphs such as for the surface code under circuit-level noise. Indeed, FIG. 10 shows a schematic illustration of an example cluster grown around a defect pushed to boundary node 13 in a viewing window arranged as a subgraph of a decoding graph for a decoder for a surface code of distance-3 under a circuit noise model. This shows the addition of edges that both span layers and join nodes having different locations in adjacent layers. As can be seen, the active clusters are, in this circuit-level noise model and for the surface code, grown along all edges incident on nodes, regardless of the edge direction, the same as shown above for the repetition code.

[0243] Regarding the performance of the streaming decoder as disclosed herein, specifically in relation to the implementation described in relation to FIG. 7 to FIG. 12 and FIG. 14, for the surface code under circuit-level noise, as will be seen below, the decoder has a threshold roughly 2 / 3 that of Union Find adapted with the forward method (as described above as the chunking batch decoder). Despite its slightly reduced accuracy, the apparatus and method disclosed herein boasts a straightforward distributed implementation that is modular and scalable by building a 2D or 3D lattice of processors. Using a processor that can operate the decoder in a ‘flattened’ 2D lattice, provides an even more practical implementation given current chip design capabilities, at a marginal cost in speed.

[0244] To illustrate these results FIG. 11 shows plots for the logical error rate for (a) union find adapted with the forward method and (b) the streaming decoder of the present disclosure, applied to the surface code of distance d under circuit-level noise of different physical error probabilities.

[0245] To generate these results, the memory experiment (preserving a logical qubit) has been emulated for the local implementation of the decoder on the surface code under the circuit-level noise model. Specifically, the decoders were used to decode a syndrome from nd measurement rounds for a large integer n. Then depending on whether accuracy or runtime was being benchmarked, different features were counted.

[0246] To benchmark decoder accuracy, the number m of logical bitflips in the leftover are identified and counted. The logical error rate y >_mjnis estimated as the logical bitflip count per d measurement rounds. FIG. 11 compares the accuracy of UF (adapted with the forward method) and the streaming decoder disclosed herein, for practical noise levels and code distances. The former has a threshold of ~7.3 • 103while Snowflake has a threshold of ~ 4.6 • 103. This discrepancy comes from the difference in relative cluster sizes e.g. were UF used in the two-defect decoding situation as shown in FIG. 8A and FIG. 8B, both clusters would be the same size when they merge.

[0247] To benchmark the decoder runtime, the number of timesteps spent on merging is counted, per d measurement rounds. As noted above, merging is the only stage of the algorithm of variable duration so in this context, the other stages are not of interest. This is normalised by d rounds as each logical operation lasts 0(d) rounds using lattice surgery, the best known technique for surface code computation. This also allows comparison to batch decoders, as each batch usually comprises d measurement rounds. FIG. 12 shows plots of the count of timesteps per d measurement rounds for the decoder method disclosed herein against surface code distance d. under circuit level noise for different physical error probabilities p below threshold on (a) on a linear-linear scale and (b) on a log-log scale.

[0248] This data is used to estimate the scaling m, assuming mean runtime oc tf”, as shown in the following table:4 - IO42.29(8) 10~31.97(6)4 - IO"32.56(4)

[0249] It can be seen that the scaling lies between quadratic and cubic. This is slightly higher than the sublinear or subquadratic scaling which might be achieved with batchwise decoders in which active clusters in the same batch all grow at the same time regardless of their vertical coordinate. In the streaming decoder disclosed herein, this cluster growing process is somewhat serialised: older active clusters start growing before newer ones do, as they enter the viewing window, W, earlier.

[0250] From this serialisation in the vertical direction, an alternative architecture to that shown in FIG. 1 may be viable in which the 3D lattice of classical modular processor units112 representing nodes may be ‘flattened’ down onto a 2D grid so there is one classical modular processor unit for each set of nodes of the same (x, y) coordinate i.e. each ancilla qubit.

[0251] Thus FIG. 13 shows a schematic illustration of another example apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register using a flattened grid of classical modular processor units in accordance with aspects of the present disclosure. Here, each flattened classical modular processor unit 112' represents plural boundary nodes or detector nodes. In this way, a single layer, or grid of flattened classical modular processor units 112' and communication links 114 provides the stacked nodes and edges in the viewing window, W. This is illustrated in FIG. 13 by the nodes and edges of the lower layers of the viewing window, W, being represented in broken lines to illustrate that multiple ‘virtual’ layers of the viewing window, W, are provided by the flattened classical modular processor units 112' and communication links 114 arranged in a single, 2D, layer. Thus, each flattened classical modular processor unit 112' may store in memory variables and attributes for multiple different nodes at different layers in the viewing window, W. When passing ‘down’ the variables and attributes, in the drop operation, from one layer to the next, a flattened classical modular processor unit 112' may perform this step internally, by updating memory, without having to communicate with other flattened classical modular processor units 112'.

[0252] This 'flattening' comes at the cost of serialising the operations within each set of nodes of the same (x, y) coordinate, but if these operations are inherently serial, the runtime cost of this flattening could be marginal. There are two benefits to this flattened architecture. First, it is more practical as a 2D chip is far easier to build than a 3D lattice of processors. Second, messages passed vertically would be instantaneous within a timestep. In this way, the decoder apparatus is of a flattened “2D” architecture which may facilitate implementation in current processor design, and may also speed up some processing by avoiding some inter-processor communication.

[0253] In the foregoing examples, the apparatus is configured to implement a simple decoding cycle in which the growth rate does not vary and all edges are made available for growth at the same time (i.e. in one “growth round”) in each cycle. However, as noted above, embodiments in which the growth varies based on a variety of criteria are considered to be within the scope of the present disclosure. An example is where different cluster growth schedules are provided.

[0254] The examples above implement the most straightforward schedule in which one growth round per decoding cycle, i.e. a “1 : 1” cluster growth schedule is implemented. . A growth round here comprises growing each active cluster in all possible (defined by the edges of G) directions by half an edge (or another fraction), merging touching clusters and pushing defects to roots. For this, FIG. 14 shows example pseudocode describing the general, abstract global implementation by the classical modular processor units for implementing a 1 : 1 cluster growth schedule.

[0255] However, a 1 : 1 growth schedule creates an issue that hinders the accuracy of the algorithm leading to avoidable logical errors. To see the issue with this schedule, note the following lemma for Theorem 1 of the paper “ Almost-linear time decoding algorithm for topological codes” by Nicolas Delfosse and Naomi H. Nickerson, in Quantum 5, 595 (2021) retrievable from (https: / / dx.doi.org / 10.22331 / q-2021-12-02-595), that is satisfied by original Union Find:Whenever a cluster grows, the number of bitflipped edges covered by the union of all clusters increases by >1 / 2.

[0256] The theorem leads to the following corollary for original Union Find:Any combination of s < d / 2 bitflips can be corrected.

[0257] As a proof for this, the lemma guarantees that after 2s growth rounds, all bitflipped edges are covered by the union of all clusters, and no more growth occurs. The largest possible cluster diameter after this many growth rounds is 2s < d so no logical bitflip is possible.

[0258] As can be seen from FIG. 15, which shows a sequence of panes illustrating the progress of an example operation of the apparatus of FIG. 1 implementing a 1 : 1 cluster growth schedule, it is possible for two active clusters to be only half an edge apart. Then, during growth, they will overgrow ‘into each other’ rather than stop growing as soon they touch. That is, FIG. 15 shows the progress of the apparatus implementing a 1 : 1 cluster growth schedule for a distance-5 code for example defects in a first decoding cycle in pane (a), in a second decoding cycle in pane (b) and in a third decoding cycle in pane (c).Ungrown edges are invisible, half-grown edges are dotted, fully grown edges are solid grey, and edges bitflipped by the decoder are in bolded in black. As can be seen, where the defect is one layer and one node apart, it is possible for two active clusters to become only half an edge apart in the second decoding cycle shown in pane (b). Then in pane (c) the twoclusters both grow by a half an edge in the growth step, leading the clusters to overgrow into each other. This violates the above lemma and leads to unnecessarily large clusters. For example, assume the defect pair in FIG. 15 pane (a) resulted from s = 2 bitflipped edges. In pane (c), the two clusters grow but only 1 / 2 more of the bitflipped edges are covered. The resultant cluster has diameter 9 / 2 > 5.

[0259] To fix this, the apparatus can be adapted such that the processors implement a decoding cycle within which clusters are grown more cautiously. It can be noted that in FIG. 15 pane (b) it is enough for just one of the clusters to grow for the two to merge, and the reason they are half an edge apart is that one has grown an even, and the other an odd, number of times. Thus a differential or “2: 1” cluster growth schedule can be implemented.

[0260] For this a whole cluster is defined as one that has grown an even number of times, a half cluster is defined as one that has grown an odd number of times, and a mixed cluster is defined as one that has resulted from merging a whole with a half cluster. Visually, a whole cluster is, when isolated, surrounded by ungrown edges or half grown edges (that is, the cluster has grown to have fully grown edges in its most recent growth round such that is it surrounded by ungrown or half-grown edges (from an adjacent ‘half’ cluster) which are available for growth in the next growth round). Visually, a half cluster is always surrounded by half-grown edges (that is, the cluster has grown to have half-grown edges in its most recent growth round such that is it surrounded by only half-grown edges which are available for growth in the next growth round). A mixed cluster, e.g. as shown in Fig. 15 pane (c), is always surrounded by both types of edge.

[0261] FIG. 16 shows a flowchart representing another example method 1600 for finding a correction, C, to an error, E, detected in measurements of a qubit register in accordance with aspects of the present disclosure in which a 2:1 cluster growth schedule is implemented.

[0262] In this schedule, the apparatus performs two different growth rounds per decoding cycle: first growing the whole clusters, then the half clusters. After each growth round, all clusters reevaluate their activity by a merge step being performed.

[0263] To carry out the method 1600, the circuitry 112c of the classical modular processor units 112 is configured for performing a decoding cycle comprising a drop operation 1602, a first grow operation 1604 growing, a first merge operation 1606 which, by decision block 1608 implementing a while loop continues until the merging is complete, followed by a second grow operation 1610, and a second merge operation 1612, which by decision block 1614 implementing a while loop continues until the merging is complete, after which themethod 1600 returns to the drop 1602 step so the next decoding cycle begins. The method 1600 is a cycle in the sense that the method 1600 returns to the start again after the second merge 1612 step is completed, and the viewing window is ‘moved up’ in a drop 1602 step to receive the measurement bits from the next measurement round.

[0264] The drop 1602, first grow 1604, first merge 1606, second grow 1610 and second merge 1612 operations are performed by all the classical modular processor units 112 in each measurement round, in turn, and in synchrony, the classical modular processor units 112 all progressing to the next operation in the same timestep. In that regard, the classical modular processor units 112 may operate on incremental timesteps. Their synchronisation in these timesteps, and their progression through the operations, may be governed by the classical modular processor units 112 themselves, or in conjunction with the controller 102.

[0265] In particular, the drop 1602, first grow 1604 and second grow 1610 operations each take one timestep, but the first merge 1606 and second merge 1612 operations may take an undefined number of timesteps to complete, and so the while loop indicated by decision block 1608 and decision block 1614 returns the process to repeatedly perform merging until completion. In this regard, the controller 102 may be configured to communicate with all of the classical modular processor units 112 to monitor when they are in a busy state when a merge operation is still being carried out and is not yet complete, and the controller 102 may communicate with the classical modular processor units 112 to keep performing the merge operations and only allow the decoding cycle to progress from the merge steps when all of the classical modular processor units 112 are no longer busy merging. This coordination of the progression of the decoding cycle from the merge steps by the controller 102 may maintain synchrony of each of the classical modular processor units 112 in performing the decoding cycle.

[0266] The method 1600 will be further described with reference to FIG. 17 which shows a sequence of panes illustrating the progress of an example operation of the apparatus of FIG. 1 implementing a 2: 1 cluster growth schedule in which “overgrowth” into each other of two active clusters half an edge apart is avoided. It should be noted that FIG. 17 shows the progress of the decoder for the same defects as FIG. 15 for the 1 :1 schedule, except that the first decoding cycle is not shown as it corresponds to FIG. 15 pane (a).

[0267] The drop operation 1602 corresponds to the drop operation 402 described in relation to FIG. 4 above.

[0268] In the first grow operation 1604, active whole-edge clusters that have been grown an even number of times to have only ungrown or half-grown edges available for growth aregrown along those edges by a positive fraction of an edge, the fraction being half an edge. This is shown in FIG. 17 in pane (bi). As can be seen, only the top-most active “whole” cluster (which previously had zero-growth edges around the defect) has been grown to have half grown edges.

[0269] Thereafter a merge operation 1606 and decision block 1608 operate as the corresponding merge operation 406 and decision block 408 described in relation to FIG. 4 above. In FIG. 17 in pane (bi), no merging occurs as no clusters are joined by a whole edge, and so the method 1600 proceeds.

[0270] Then, in the second grow operation 1610, active half-edge clusters that have been grown an odd number of times to have only half-grown edges available for growth are grown along those edges by a positive fraction of an edge, the fraction being half an edge. This is shown in FIG. 17 in pane (bii). As can be seen, only the bottom-most active “half’ cluster (which previously had half-grown edges around the defect) has been grown to have whole grown edges. It should be noted that the classical modular processor units 112 are configured such that, in the second grow operation 1610, clusters that have already been grown the first growth operation 1606, are not grown a second time in that decoding cycle. That is, whole clusters that grow in the first round (thus becoming half clusters) do not grow again in the same decoding cycle.

[0271] Thereafter a second merge operation 1612 and decision block 1614 operate as the corresponding merge operation 406 and decision block 408 described in relation to FIG. 4 above. In FIG. 17 in pane (bii), no merging occurs as no clusters are joined by a whole edge, and so the method 1600 proceeds to loop around again to the third decoding cycle, the first growth stage of which is shown in pane (ci).

[0272] Here, in the first growth step 1604, the lower-west active cluster (which previously had whole edges grown around the defect) has been grown by all available edges by a further half an edge. As can be seen, this leads to that cluster having half grown edges but also becoming connected to the upper-east cluster by two fully grown whole edges. Then, in the first merge step 1606, the results of which are shown, the defects annihilate and the edges along which the defects are passed are bitflipped and stored in the tentative correction. The merged cluster becomes inactive and grows no further.

[0273] As can be seen, as the growth of the clusters stopped in the first growth step 1606, the two clusters, separated by half an edge at the end of the second decoding cycle in pane (bii), did not grow into each other in the third decoding cycle, but instead stopped in the condition shown in pane (ci), such that the clusters did not “overgrow”. The resultant halfcluster has diameter 4 = 2s and is not overgrown. That is, if two active clusters are half an edge apart, only one of them will grow. Mixed clusters need not be considered because mixed clusters never occur with the 2: 1 schedule.

[0274] FIGs. 18 A, 18B and 18C show example pseudocode for operation locally at each node by the classical modular processor units (and, for algorithm 3, the controller) for implementing a 2: 1 cluster growth schedule. The variables for the 2: 1 growth schedule as the same as for the 1 : 1 growth schedule, with the addition of grown, which is a boolean indicating whether the cluster that the node is in has grown in the first growth round

[0275] of the current decoding cycle, and whole, which is a boolean indicating whether the node is in a whole cluster. In other changes, the merging whole stage is the same as merging half but with two extra processes. That is, the merging half stage comprises the two processes, syncing and flooding, which occur independently. The MergingHalf procedure is split into two subroutines, given in Algorithm 6, effecting each process.

[0276] Operating the apparatus to implement a 2: 1 growth schedule can be shown to be much more accurate with the 1 : 1 growth schedule.

[0277] As with FIG. 11, the plot in FIG. 19 compares the logical error rate for the streaming decoder of the present disclosure, applied to the surface code of distance d under circuit-level noise of different physical error probabilities p, where the classical modular processor units are configured for implementing a 1 : 1 cluster growth schedule (results shown by the lines indicated by 1902) and a 2: 1 cluster growth schedule (results shown by the lines indicated by 1904). As can be seen, the coordinate (p,f)th of the error threshold is around (0.375, 9) 102for the 1 :1 growth schedule (indicated at 1902), and (0.735, 6.8) 102for the 2: 1 growth schedule (indicated at 1904). Thus the 2: 1 growth schedule almost doubles the threshold pth of the 1 : 1 growth schedule, recovering significantly more errors and giving a reduced logical error rate.

[0278] When compared to Union Find adapted with the Forward Method, the present invention implementing the 2: 1 growth schedule compares favourably. Like FIG. 11, the plot in FIG. 20 shows a comparison of the logical error rate for the streaming decoder of the present disclosure where the classical modular processor units are configured for implementing a 2: 1 cluster growth schedule (results shown by the lines indicated in the inset by 2004) and a streaming decoder implementing the forward method (results shown by the lines indicated in the inset by 2002). The inset zooms in on both thresholds whose coordinate (p,f)th is around (0.755, 10.5)- 10'2for UF adapted with the forward method, and(0.735, 6.8)- 102for the present disclosure implementing a 2: 1 cluster growth schedule. Below threshold, we assume the power law fifth = (plpthfi. Analysis shows the subthreshold gradients in m(d) are indistinguishable for the two decoders, so their accuracy difference can be characterised solely by their thresholds. While union find adapted with the forward method has a slightly higher threshold, the apparatus of the present disclosure implementing a 2: 1 cluster growth schedule leads to a logical qubit lifetime l / / that is 24.9(5)% longer on average over the FIG. 20 data. Thus when tested on the surface code under circuit-level noise, the presently disclosed apparatus implementing the 2: 1 growth schedule recovers ~97% of the threshold of UF adapted with the forward method, but in absolute terms is 24.9(5)% more accurate.

[0279] Thus, for the surface code under circuit-level noise, the apparatus and method disclosed herein, specifically in relation to the 2: 1 growth schedule implementation described in relation to FIG. 16 to FIG. 21, is roughly as accurate as UF adapted with the forward method.

[0280] Regarding runtime, as in FIG. 12, the plots in FIG. 21 show the count of timesteps per d measurement rounds against surface code distance d, under circuit level noise for different physical error probabilities p below threshold on a log-log scale for, in pane (a), a streaming decoder implementing the forward method, and, in pane (b), the streaming decoder of the present disclosure where the classical modular processor units are configured for implementing a 2: 1 cluster growth schedule. Each solid line shows the mean of 103lots of d measurement rounds for a given physical error probability p. Each dashed line shows the 99thpercentile of 103lots of d measurement rounds for a given physical error probability p. The shading shows the standard deviation. The standard error of the mean is smaller than the solid line thickness.

[0281] In generating the data for FIG. 21, the controller-processor communication cost is excluded by assuming implementations where the controller connects directly to each processor.

[0282] Estimating the scaling m for the runtime, assuming that mean runtime is proportional to <7, it is found that while the Forward Method’s scaling is sublinear, the scaling for the apparatus of the present disclosure implementing a 2: 1 cluster growth schedule is subquadratic. We suspect that this is because for Union Find adapted by the Forward Method, active clusters in the same batch all grow at the same time regardless of their vertical coordinate. In the apparatus of the present disclosure implementing a 2: 1 cluster growth schedule, this process is somewhat serialized in that older active clusters startgrowing before newer ones do, as they enter the viewing window W. Despite this discrepancy, subquadratic is still better than the slightly-higher-than-cubic scaling of original Union Find.

[0283] To investigate the practical regime for implementing the 2: 1 cluster growth schedule, plots of the distribution of runtimes for the decoder at the lowest emulated noise level shows that the distribution of runtimes does not have a long tail. Such consistent runtimes are beneficial for hard real-time decoding: the time limit can be set lower for a given target timeout failure rate, accelerating the quantum program and increasing qubit coherence.

[0284] Features, integers, characteristics or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and / or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and / or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. In particular, any dependent claims may be combined with any of the independent claims and any of the other dependent claims.

[0285] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

CLAIMS1. Apparatus for finding a correction, C, to an error, E, detected in measurements of a qubit register received at intervals over time in a stream of successive measurement rounds, comprising: a plurality of identical classical modular processor units coupled by communication links, configured to provide a set of nodes, V, joined by a set of edges, E, together representing a viewing window, W = (V, E corresponding to a subgraph of successive layers of a decoding graph, G, each layer of the decoding graph being for encapsulating faults that can occur in a measurement round of a quantum error correction code used for encoding at least one logical qubit across plural physical qubits in the qubit register; wherein the nodes comprise: a subset of detector nodes, VD, configured to, in use, for a first, top layer of the viewing window, receive at each detector node one of a set of measurement bits of a stabilizer code for a given ancilla qubit in the qubit register in the most recent measurement round, and flag defects where a measurement bit flips relative to the previous measurement round, a defect being flagged when an odd number of edges, E, incident on a node experience faults in that measurement round, each edge representing the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident, the set of defects in the viewing window defining a syndrome, S, caused by an error, E, of the subset of edges suffering faults; and a subset of boundary nodes, VB, arranged along one or more walls of the viewing window, each boundary node communicatively coupled to a detector node such that an edge is provided in the viewing window to represent all faults than can each cause a flip in the measurement bit of the detector node incident on the edge; the processor units having circuitry to be configured to: store between them information on: the location of defects; clusters of edges grown around defects within which a correction to the errors causing the defects is sought; and a tentative correction, T, to the error for each cluster to be determined by the processors units as the clusters stream through the viewing window; and, for performing a decoding cycle including, in turn, in each measurement round:in a drop operation, drop the stored information on defects, clusters and tentative correction down one layer of the viewing window to receive a new measurement round for detector nodes in the top layer of the viewing window; in a grow operation, grow active clusters along all available edges by a positive fraction of an edge, the fraction being less than one, such that clusters grow at a slower rate than they fall through the viewing window; and in a merge operation: nucleate new active clusters at defects that are received in for the current measurement round at the top layer of the viewing window, W = (V, merge together clusters that have become joined by a fully grown edge; within active clusters, pass defects along fully grown edges towards any boundary node fully connected to the active cluster, or otherwise towards the highest node fully connected to the active cluster; store any edges along which defects are passed in a tentative correction, T, for the cluster; annihilate defects at nodes at which two defects are received; and mark any clusters inactive that no longer contain any defects or if the defect has been passed to a boundary node, such that the inactive cluster no longer grows in the next decoding cycle; wherein, in a commit region of c layers comprising at least the last, bottom layer of the viewing window, W= (V, E the edges flagged in the tentative correction, T, are committed to form part of a correction, C, of a set of edges to be bitflipped to correct for the error, B, such that the syndrome, S, is the null set in the commit region.

2. The apparatus of claim 1, wherein, for each edge that represents the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident, the set of faults is based on a noise model that includes at least the faults that can arise in: a data qubit in the qubit register; and a measurement outcome of a stabilizer code in a given ancilla qubit.

3. The apparatus of claim 2, wherein the set of faults is based on a noise model that further includes the faults that can arise in: a quantum circuit performed during a measurement round.

4. The apparatus as claimed in any one of claims 1 to 3, wherein the quantum error correction code is a repetition code or a surface code.

5. The apparatus as claimed in any of any one of claims 1 to 4, wherein the topology of the decoding graph, G, and the set of nodes, V, joined by a set of edges, E, together representing a viewing window, W = (V, E), provided by the plurality of identical classical modular processor units coupled by communication links, is based on the quantum error correction code and the noise model.

6. The apparatus of any one of claims 1 to 5, wherein the viewing window, W = (V, E consists of the commit region and a buffer region of b layers above and consecutive with the commit region, wherein the buffer region includes at least 2*floor(t / / 2) layers, wherein d is the code distance of the quantum error correction code, such that the edges in the tentative correction, T, committed to the correction, C, in the commit region, is always complete in that all defects in the commit region are annihilated.

7. The apparatus of any one of claims 1 to 6, wherein the commit region consists of c layers, and wherein c = 1, such that W consists of a minimised number of layers.

8. The apparatus of any one of claims 1 to 7, further comprising one or more processor units configured to: provide a measurement queue for storing measurement bits from measurement rounds of the qubit register; receive and store in a queue measurement bits from consecutive measurement rounds completed for the qubit register; and responsive to the completion of a decoding cycle, pass to the top layer of the detector nodes in the viewing window, W= (V, E the measurement bits from the oldest measurement round stored in the queue to provide the new measurement round for the next decoding cycle.

9. The apparatus of claim 8, wherein the one or more processor units are configured such that the average time taken to complete a decoding cycle is shorter than the average time between measurement rounds of the qubit register.

10. The apparatus of any one of claims 1 to 9, wherein the viewing window, W = (V, E), is raised by one layer each decoding cycle, and wherein the computed tentative correction, T, is retained between decoding cycles.

11. The apparatus of any one of claims 1 to 10, the processor units being further configured to, in the decoding cycle, bitflip all edges added to the tentative correction, T, such that the syndrome, 8, is modified even in layers above the commit region.

12. The apparatus of any one of claims 1 to 11, wherein the plurality of identical classical modular processor units are each coupled by communication links to one or more of the other modular processor units to perform communication only with their nearest neighbours.

13. The apparatus of any one of claims 1 to 12, wherein each processor unit further comprises circuitry configured to perform the decoding cycle by carrying out the drop, grow and merge operations local to that processor based only on the information stored thereat and only by communication with its nearest neighbour processor nodes only.

14. The apparatus of any one of claims 1 to 12, wherein the apparatus is configured such that the processor units independently perform the drop, grow and merge operations in turn and synchrony.

15. The apparatus of claim 14, wherein the processor units are configured to independently perform the drop, grow and merge operations in successive, discrete and synchronised timesteps, the drop and grow operations each taking one timestep, the merge operation taking an undetermined number of timesteps.

16. The apparatus of claim 14 or 15, further comprising a controller coupled to the processor units and configured to send an instruction to the processor units to cause the nodes to perform a drop operation after three timesteps unless any of the nodes are still busy merging.

17. The apparatus of any one of claims 1 to 16, wherein one processor unit is provided for each node in the viewing window, such that the processor units and communication links together form a plurality of stacked layers arranged as the decoding graph within the viewing window.

18. The apparatus of any one of claims 1 to 17, wherein one processor unit is provided for each set of nodes representing the same ancilla qubit across plural layers in the viewing window, such that the layers of the viewing window are flattened into a single layer of processor units, the processor units and communication links together being arranged to provide the decoding graph in the viewing window.

19. The apparatus of any one of claims 1 to 18, wherein each processor unit comprises memory configured to store local to each node the information on defects, clusters and the tentative correction as attributes including: whether the node has a defect; whether the node is in an active cluster; which cluster the node belongs to based on a unique cluster identifier, CID; and, for each edge owned by the node: a growth value; and whether the edge belongs in the tentative correction, T.

20. The apparatus of claim 19, wherein the processor units are configured such that, in the drop operation, each node communicates in one timestep its stored attributes down to the corresponding node in the next layer corresponding to the next oldest measurement round.

21. The apparatus of claim 19 or 20, wherein the processor units are configured such that, in the grow operation, each node in an active cluster causes in one timestep the growth value of edges incident on that node to increase by 1 for all edges having a growth value of less than 1, such that clusters nucleate and become active at nodes flagging defects and grow along edges at half the rate the nodes drop their attributes, and by which separate clusters can become fully connected by edges having a growth value of 1, allowing clusters to be merged.

22. The apparatus of any one of claims 19 to 21, wherein the processor units are configured such that, in the merge operation, each node in an active cluster is configured to iteratively perform in successive timesteps until completion: firstly, syncing, by which the defects are passed along fully grown edges towards any boundary node fully connected to the active cluster, or otherwise towards the highest node fully connected to the active cluster, by which, for any edges along which defects are passed during syncing, attributes indicating whether those edges belong in the tentative correction, T, are flipped, by which any nodes receiving two defects causes the defects to annihilate, and by which the cluster is marked inactive and no longer grows in the next decoding cycle if it no longer contains any defects or if a defect has been passed to a boundary node; and secondly, flooding, by which the cluster identifier of the node is updated to indicate a node identifier of the highest node fully within the cluster.

23. The apparatus of any one of claims 19 to 22, wherein each node stores a unique node identifier, wherein the detector nodes higher in the viewing window have a lower ordinal node identifier than detector nodes lower in the viewing window, and wherein the boundary nodes have lower ordinal node identifiers than the detector nodes, and wherein the nodeidentifiers are used by the nodes as a basis for passing defects towards the highest node fully connected to an active cluster, and for flooding so that each node in an active cluster knows, through its cluster identifier, the ordinal node identifier of its root.

24. The apparatus of any one of claims 1 to 23, wherein the classical modular processor units are configured such that, in the grow operation, the fraction the edges are grown by may vary.

25. The apparatus of any one of claims 1 to 24, the processor units having circuitry to be configured to perform each decoding cycle by carrying out, in turn: a drop operation; a first grow operation in which active whole-edge clusters that have been grown an even number of times to have ungrown or half-grown edges available for growth are grown along those edges by a positive fraction of an edge, the fraction being half an edge; a merge operation; a second grow operation in which active half-edge clusters that have been grown an odd number of times to have only half-grown edges available for growth are grown along those edges by a positive fraction of an edge, the fraction being half an edge; and a further merge operation.

26. A classical modular processor unit for use in an apparatus as claimed in any one of claims 1 to 24.

27. A method of finding a correction, C, to an error, E, detected in measurements of a qubit register, the method performed in a plurality of identical classical modular processor units coupled by communication links configured to provide a set of nodes, V, joined by a set of edges, E, together representing a viewing window, W= (V, E), corresponding to a subgraph of successive layers of a decoding graph, G, each layer of the decoding graph being for encapsulating faults that can occur in a measurement round of a quantum error correction code used for encoding at least one logical qubit across plural physical qubits in the qubit register, the method including, for each of a stream of measurement rounds, performing a decoding cycle comprising: receiving, a set of measurement bits of a stabilizer code for the most recent measurement round, each measurement bit for a given ancilla qubit in the qubit register being received at one of a subset of detector nodes, VD, and stored in a first, top layer of the viewing window;flagging defects at detector nodes, VD, where a measurement bit flips relative to the previous measurement round, a defect being flagged when an odd number of edges, E, incident on a node experience faults in that measurement round, each edge representing the set of faults that each cause a flip in the measurement bit of the or each detector node on which the edge is incident, the set of defects in the viewing window defining a syndrome, Ss, caused by an error, E, of the subset of edges suffering faults; a drop operation including dropping down one layer of the viewing window, to receive the new measurement round for detector nodes in the top layer of the viewing window, stored information on: the locations of any defects; any clusters of edges grown around defects within which a correction to the errors causing the defects is sought; and a tentative correction, T, to the error for each cluster to be determined by the processor units as the clusters stream through the viewing window; a grow operation including growing active clusters along all available edges by a positive fraction of an edge, the fraction being less than one, such that clusters grow at a slower rate than they fall through the viewing window; and a merge operation including: nucleating new active clusters at defects as they are received in new measurement rounds at the top layer of the viewing window, W = V, E , merging together clusters that become joined by a fully grown edge; within active clusters, passing defects along fully grown edges towards: any of a subset of boundary nodes, VB, fully connected to the active cluster, the boundary nodes, VB, being arranged along one or more walls of the viewing window, each boundary node communicatively coupled to a detector node such that an edge is provided in the viewing window to represent all faults than can each cause a flip in the measurement bit of the detector node incident on the edge; or otherwise towards the highest node fully connected to the active cluster; storing any edges along which defects are passed in a tentative correction, T, for the cluster; annihilating defects at nodes at which two defects meet; andmarking any clusters inactive that no longer contain any defects or if the defect has been passed to a boundary node, such that the inactive cluster no longer grows in the next decoding cycle; for a commit region of layers comprising at least the last, bottom layer of the viewing window, W = (F, E), committing the edges flagged in the tentative correction, T, to form part of a correction, C, of a set of edges to be bitflipped to correct for the error, E, such that the syndrome, 0, is the null set in the commit region.

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