Temperature-compensated reference voltage generator that applies controlled voltages through resistors.

Abstract

An apparatus and a method for generating a temperature-compensated reference voltage are disclosed. The apparatus generates substantially equal temperature-compensated currents by controlling (through negative feedback) voltages across separate resistors through which the currents flow, respectively. Two of the temperature-compensated currents are formed by combining (e.g., summing) a temperature current complementary to the absolute (ctat) (ictat) and a temperature current proportional to the absolute (ptat) (iptat). A reference voltage vref is produced by setting the other temperature-compensated current to flow through an output resistor.

Description

1 / 16 “TEMPERATURE-COMPENSATED REFERENCE VOLTAGE GENERATOR THAT IMPRESSES CONTROLLED VOLTAGES THROUGH RESISTORS” REFERENCE REQUESTED ON REQUEST

[001] This application claims priority to the benefit of non-provisional application no. 14 / 970,265 filed with the United States Patent and Trademark Office on December 15, 2015, the contents of which are incorporated herein by reference. BACKGROUND Field

[002] Aspects of the present disclosure relate in general to the generation of temperature-compensated reference voltages, and more particularly, to a temperature-compensated reference voltage generator that generates temperature-compensated currents by printing controlled voltages across resistors. Background

[003] A power gap reference voltage source generates a VREF reference voltage that is substantially constant across a defined (very wide) temperature range. In discrete circuit or integrated circuit (IC) applications, the VREF reference voltage is used in many applications, such as for voltage regulation where a supply voltage is regulated based on the reference voltage.

[004] The generated power gap reference voltage is typically around 1.2 Volts because the voltage source is based on the 1.22 eV silicon power gap at zero (0) Kelvin. Since the power gap reference voltage VREF is approximately 1.2 Petition 870180050363, dated 12 / 06 / 2018, p. 7 / 40 2 / 16 Volts, a power gap reference voltage source requires a supply voltage greater than 1.2 Volts, such as a supply voltage of 1.4 Volts to accommodate, for example, a drain-to-source voltage of 200 millivolts (mV) Vds from a field-effect transistor (FET) used to bias the power gap reference voltage.

[005] Currently, due to the continuous reduction in the size of FETs used in ICs and the additional need to reduce power consumption, many circuits operate with supply voltages below the 1.2 Volt power gap voltage. In response to this need, power gap reference voltage sources have been designed to operate with a supply voltage below 1.2 Volts. SUMMARY

[006] What follows presents a simplified summary of one or more modalities to provide a basic understanding of such modalities. This summary is not an extensive overview of all modalities considered, and does not intend to identify key or critical elements of all modalities nor to delineate the scope of all or any modalities. Its sole purpose is to present some concepts of one or more modalities in a simplified form as a prelude to the more detailed description that is presented later.

[007] One aspect of the disclosure relates to a device configured to generate a temperature-compensated reference voltage. The apparatus includes first and second sets of resistors; a current generator configured to generate a first temperature current. Petition 870180050363, dated 12 / 06 / 2018, p. 8 / 40 3 / 16 compensated through the first set of one or more resistors, where a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; a control circuit configured to generate a second voltage across the second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated across the second set of resistors based on the second voltage; and a third set of one or more resistors through which the second temperature-compensated current flows, wherein the temperature-compensated reference voltage is generated across the third set of one or more resistors based on the second temperature-compensated current.

[008] Another aspect of the disclosure relates to a method for generating a temperature-compensated reference voltage. The method includes generating a first temperature-compensated current through a first set of one or more resistors, where a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; generating a second voltage across a second set of one or more resistors, where the second voltage is based on the first voltage, and where a second temperature-compensated current is generated across the second set of resistors based on the second voltage; and applying the second temperature-compensated current across a third set of one or more resistors, where the temperature-compensated reference voltage is Petition 870180050363, dated 12 / 06 / 2018, p. 9 / 40 4 / 16 generated through the third set of one or more resistors.

[009] Another aspect of the disclosure relates to a device configured to generate a temperature-compensated reference voltage. The apparatus comprises means for generating a first temperature-compensated current through a first set of one or more resistors, wherein a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current; means for generating a second voltage through a second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated across the second set of resistors based on the second voltage; and means for applying the second temperature-compensated current through a third set of one or more resistors, wherein the temperature-compensated reference voltage is generated across the third set of one or more resistors.

[0010] For the accomplishment of the above and related purposes, one or more embodiments include the features described fully below and particularly indicated in the claims. The following description and the accompanying drawings detail certain illustrative aspects of one or more embodiments. These aspects are indicative, however, of only some of the various ways in which the principles of various embodiments may be employed, and the embodiments described are intended to include all such aspects and their equivalents. Petition 870180050363, dated 12 / 06 / 2018, p. 10 / 40 5 / 16 BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 illustrates a schematic diagram of an exemplary device for generating a temperature-compensated reference voltage according to an aspect of the revelation.

[0012] Figure 2 illustrates a schematic diagram of another exemplary device for generating a temperature-compensated reference voltage according to another aspect of the disclosure.

[0013] Figure 3 illustrates a schematic diagram of yet another exemplary device for generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure.

[0014] Figure 4 illustrates a schematic diagram of yet another exemplary device for generating a temperature-compensated reference voltage in accordance with another aspect of the disclosure.

[0015] Figure 5 illustrates a flowchart of an exemplary method of generating a temperature-compensated reference voltage according to another aspect of the revelation. DETAILED DESCRIPTION

[0016] The detailed description set forth below, with respect to the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be put into practice. The detailed description includes specific details for the purpose of providing a complete understanding of the various concepts. However, it will be evident to those skilled in the art that these Petition 870180050363, dated 12 / 06 / 2018, page 11 / 40 6 / 16 concepts can be put into practice without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0017] Figure 1 illustrates a schematic diagram of an exemplary apparatus 100 for generating a temperature-compensated reference voltage VREF according to an aspect of the disclosure.

[0018] Apparatus 100 includes a sub-circuit 110 to generate a temperature-complementary current (CTAT) ICTAT (e.g., a negative temperature coefficient current). Sub-circuit 110 includes field-effect transistor (FET) M1, resistor R4, and diode D1. FET M1, which can be implemented with a p-channel metal-oxide-semiconductor (PMOS) FET, is coupled in series with the parallel coupling of resistor R4 and diode D1 between a first voltage rail (e.g., Vdd) and a second voltage rail (e.g., ground). FET M1, serving as a current source, is configured to generate a current I1, which is split between resistor R4 and diode D1. The voltage VA formed across diode D1 has a negative temperature coefficient, e.g., a CTAT voltage. The voltage VA is also across resistor R4. Thus, a current ICTAT is formed through resistor R4.

[0019] Apparatus 100 includes a sub-circuit 120 to generate a temperature-proportional current (PTAT). Sub-circuit 120 includes resistors R5 and R6, a group of N parallel diodes D21 to D2N, an operational amplifier (Op Amp) 130, and FET M2. The FET Petition 870180050363, dated 12 / 06 / 2018, p. 12 / 40 7 / 16 M2, resistor R5, and diode group 125 are coupled in series between Vdd and ground. FET M2, which can be implemented with a PMOS FET, is also coupled in series with resistor R6 between Vdd and ground. Op Amp 130 includes a negative input terminal configured to receive voltage VA through diode D1, a positive input terminal configured to receive voltage VB through the series connection of resistor R5 and diode group 125, and an output terminal coupled to the gates of FETs M1 and M2.

[0020] Through negative feedback control, the Op Amp 130 controls the currents I1 and I2 through the FETs M1 and M2 via their respective gate voltages, so that the voltage VB is based on the voltage VA (i.e., substantially equal to each other, VB = VA). Since the FETs M1 and M2 are configured to have the same size and also have their gates coupled together to form a current mirror, the currents I1 and I2 are also substantially equal. Since the voltages VA and VB are equal, and resistors R4 and R6 are configured to have substantially the same resistance, the current through resistor R6 is also an ICTAT current, i.e., substantially equal to the ICTAT current through resistor R4.

[0021] Therefore, the current through diode D1 is substantially equal to the combined current through the N parallel diodes D21 to D2N of diode group 125. Diodes D21 and D2N of diode group 125 are individually configured to be substantially equal to diode D1. Thus, since the same current through diode D1 is divided among N diodes of the group of Petition 870180050363, dated 12 / 06 / 2018, p. 13 / 40 8 / 16 diodes 125, the current density through each of the diodes in the diode group 125 is a factor of N smaller than the current density through diode D1. Due to the difference in current density, the diode group 125 produces a CTAT voltage that is different from the CTAT voltage across diode D1. As a result, a voltage is produced across resistor R5 that has a positive temperature coefficient (i.e., a PTAT voltage). This produces an IPTAT current through resistor R5.

[0022] The current I2 produced by FET M2 is a combination (i.e., sum) of the currents IPTAT and ICTAT. Thus, by appropriate selection of the resistors R4, R5, and R6, the current I2 can be configured to be substantially constant over a defined temperature range.

[0023] Device 100 also includes a subcircuit 140 configured to generate the temperature-compensated reference voltage VREF based on the temperature-compensated current I1 to M2. Subcircuit 140 includes FET M3 and resistor R1. The temperature-compensated current I2 is mirrored through the current mirror configuration of FETs M2 and M3 (i.e., the FETs are configured to have substantially the same size and the same gate-to-source voltage Vgs) to form a temperature-compensated current I3. FET M3, which can also be implemented with a PMOS FET, is coupled in series with a resistor R7 between Vdd and ground, resulting in the temperature-compensated current I3 flowing through resistor R7 to form the temperature-compensated reference voltage VREF. Petition 870180050363, dated 12 / 06 / 2018, p. 14 / 40 9 / 16

[0024] Thus, for device 100 to operate properly, the currents I1, I2, and I3 generated by the current sources M1, M2, and M3 must be substantially equal. However, due to the relatively low supply voltage Vdd (e.g., sub 1V), the drain-to-source voltage Vds of FETs M1 and M2 may become relatively small because the voltages VA and VB increase with decreasing temperature. In such a case, the Vds of FETs M1 and M2 may be significantly smaller than the Vds of FET M3; and consequently, the METs M1 and M2 may have output impedances different from the output impedance of FET M3. This produces a current mismatch between current I3 and currents I1 and I2, which produces an error in the reference voltage VREF.

[0025] Additional mismatch between streams I1, I2 and I3 may be caused by mismatch in FETs M1, M2 and M3 due to process variation.

[0026] Figure 2 illustrates a schematic diagram of another exemplary device 200 for generating a temperature-compensated reference voltage VREF according to another aspect of the disclosure. Device 200 is configured to handle the problem associated with FETs M1, M2, and M3 having different drain-to-source voltages Vds; and consequently, different output impedances that produce current mismatch between currents I1, I2, and I3. Device 200 is similar to that of device 100, but includes a modified reference voltage VREF generating subcircuit 240 having an additional control circuit to ensure that the voltages across the current source FETs M1, M2, and M3 are substantially equal. Petition 870180050363, dated 12 / 06 / 2018, p. 15 / 40 10 / 16

[0027] In particular, in addition to FET M3 and resistor R7, subcircuit 240 includes an Op Amp 245 and a FET M4. Op Amp 245 includes a positive input configured to receive the voltage VB, a negative input coupled to the drain of FET M3, and an output coupled to a gate of FET M4. FET M4, which can be implemented with a PMOS FET, is coupled between FET M3 and resistor R7. The reference voltage VREF is generated at the drain of FET M4.

[0028] Due to negative feedback, Op Amp 245 controls the gate of FET M4 in such a way that the voltage VC is substantially equal to the voltage VB. In this way, the voltages across the current source FETs M1, M2 and M3 are substantially equal.

[0029] Although this is an improvement over apparatus 100 shown in Figure 1, there is still an error in the reference voltage VREF due to the mismatch between the current source FETs M1, M2, and M3. That is, although the voltages across FETs M1, M2, and M3 can be made substantially equal through the negative feedback control provided by Op Amps 130 and 245 and FET M4, the currents I1, I2, and I3 respectively through FETs M1, M2, and M3 can be different due to the difference in their transconductance gains caused by process variations. This results in different currents I1, I2, and I3, which produces an error in the reference voltage VREF. This error becomes more prevalent as the supply voltage Vdd is reduced.

[0030] Figure 3 illustrates a schematic diagram of yet another exemplary device 300 for generating a temperature-compensated reference voltage. Petition 870180050363, dated 12 / 06 / 2018, p. 16 / 40 11 / 16 VREF, according to another aspect of the revelation. The concept behind the 300 device originates from the fact that resistors can be made more compatible than FETs; and thus, better matching between resistors can be obtained compared to FETs. Consequently, the concept behind the 300 device is to replace the current sources M1, M2, and M3 with respective resistors R1, R2, and R3 (having substantially equal resistance) and apply negative feedback control using 130 and 245 op-amps to print substantially the same voltages across resistors R1, R2, and R3. This ensures that the currents I1, I2, and I3 generated respectively through resistors R1, R2, and R3 are substantially equal, leading to a significant reduction in error in the VREF reference voltage.

[0031] In particular, device 300 includes a sub-circuit 310 configured to generate an ICTAT current, a sub-circuit 320 configured to generate an IPTAT current, and a sub-circuit 340 configured to generate a temperature-compensated reference voltage VREF. Sub-circuits 310, 320, and 340 are respectively similar to sub-circuits 110, 120, and 240 of device 200, but differ in that resistors R1, R2, and R3 are replaced by Current source FETS M1, M2 and M3, respectively. Furthermore, the 300 device also includes an M10 FET, which can be implemented with a PMOS FET, coupled between the supply voltage rail Vdd and resistors R1, R2, and R3. The output of the Op Amp 130 is coupled to the gate of the M10 FET to control a voltage VSB at a common node to resistors R1, R2, and R3. This is called single-point biasing, where the negative feedback operates on a bias voltage. Petition 870180050363, dated 12 / 06 / 2018, p. 17 / 40 12 / 16 (e.g., VSB) on a single node.

[0032] Therefore, the negative feedback control provided by Op Amp 130 forces the voltages VA and VBa to be substantially equal. Thus, the voltage drops across resistors R1 and R2 are equal to each other (VSB-VA = VSB-VB because VA=VB). Similarly, the negative feedback control produced by Op Amp 245 forces the voltages VBe and Vca to be substantially equal. Thus, the voltage drops across resistors R2 and R3 are equal to each other (VSB-VB = VSB-Vc because VB=Vc).

[0033] Since the voltages across resistors R1, R2, and R3 are substantially equal, and resistors R1, R2, and R3 can be manufactured to have substantially the same resistance, the temperature-compensated currents I1, I2, and I3 are substantially equal. This results in a significant reduction in the error in generating the reference voltage VREF.

[0034] Figure 4 illustrates a further schematic diagram of another exemplary device 400 for generating a temperature-compensated reference voltage VREF according to another aspect of the disclosure. Device 400 may be an example of a more detailed implementation of reference voltage source 300. Device 400 includes a sub-circuit 410 configured to generate an ICTAT current, a sub-circuit 420 configured to generate an IPTAT current, and a sub-circuit 440 configured to generate a temperature-compensated reference voltage VREF. With some differences as noted below, the sub-circuits 410, 420, and 440 are similar to subcircuits 310, 320, and 340 of device 300, respectively. The set of Petition 870180050363, dated 12 / 06 / 2018, p. 18 / 40 The remaining 13 / 16 circuits of device 400, namely Op Amps 130 and 245 and FET M10, are substantially the same as those of device 300.

[0035] The differences between the 400 and devices 300 are as follows: (1) resistor R1 is replaced by series-coupled resistors R11 and R12; (2) resistor R2 is replaced by series-coupled resistors R21 and R22; (3) resistor R3 is replaced by series-coupled resistors R31 and R32; (4) resistor R4 is replaced by series-coupled resistors R41-R48; (5) resistor R5 is replaced by a pair of series-coupled resistors R51-R52 and R53-R54 coupled in parallel with each other; (6) resistor R6 is replaced by series-coupled resistors R61-R68; (7) resistor R7 is replaced by series-coupled resistors R71-R74; (8) diode D1 is replaced with a bipolar transistor connected by diode Q1; and (9) the 125 diode group of parallel diodes D21-D2N is replaced by a 425 diode group of parallel diodes connected by bipolar transistors Q21-Q2N.

[0036] The operating principle of apparatus 400 is essentially the same as that of apparatus 300. The reasons for multiple resistors in apparatus 400 instead of single resistors in apparatus 300 are twofold: (1) due to process requirements (e.g., limitations on the length-to-width ratio of a resistor), multiple resistors (each conforming to the process requirement) may need to be connected in series or parallel to obtain the desired resistance; and (2) multiple resistors allow process variations to be statistically measured for better control of Petition 870180050363, dated 12 / 06 / 2018, page 19 / 40 14 / 16 total resistance of each set of resistors. Note that the number and / or combination of resistors that replace each single resistor may vary in other implementations. It should be evident to a person skilled in the art that the concept disclosed here is not limited to the specific implementation illustrated in Figure 4.

[0037] Figure 5 illustrates a flowchart of an exemplary 500 method for generating a temperature-compensated reference voltage VREF according to another aspect of the disclosure. The 500 method involves generating a first temperature-compensated current through a first set of one or more resistors, where a first voltage is generated across the first set of one or more resistors based on the first temperature-compensated current (block 502).

[0038] With reference to figures 3-4, examples of means for generating a first temperature-compensated current I2 include the circuit set having: (1) resistor(s) R1 (or R11-R12), R2 (or R21-R22), R4 (or R41-R48), R5 (or R51-R54), and R6 (or R61-R68); (2) diode D1 or transistor connected by diode Q1; (3) diode group 125 of diodes D21-D2N coupled in parallel or diode group 425 of transistors connected by diode Q21-Q2N; and (4) control circuit including Op Amp 130 and transistor (e.g., FET) M10. The first temperature-compensated current I2 flows through a first set of one or more resistor(s) R2 or R21-R22, where a first voltage (VSB-VB) is generated across the first set of one or more resistor(s) R2 or R21-R22 based on the first temperature-compensated current I2. Petition 870180050363, dated 12 / 06 / 2018, p. 20 / 40 15 / 16

[0039] The 500 method involves generating a second voltage through a second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current is generated through the second set of resistors based on the second voltage (504 block).

[0040] With reference to figures 3-4, examples of means to generate a second voltage include Op Amp 245 and transistor (e.g., FET) M4. Thus, the second voltage (VSB-VC) is generated through the second set of one or more resistor(s) R3 or R31-R32, where the second voltage (VSB-Vc) is based on (e.g., substantially equal to) the first voltage (VSB-VB), and where the second temperature-compensated current I3 is generated through the second set of resistor(s) R3 or R31-R32 based on the second voltage (VSB-VC).

[0041] The 500 method involves applying the second current through a third set of one or more resistors, where a temperature-compensated reference voltage is generated across the third set of one or more resistors (block 506).

[0042] With reference to figures 3-4, examples of means for applying the second current through a third set of one or more resistors include connecting resistor R3 or R31-R32 in series, FET M4 and resistor(s) R7 or R71-R74. In this way, the second current I3 is applied through the third set of one or more resistor(s) R7 or R71-R74 to generate a temperature-compensated reference voltage VREF across the third set of one or more resistor(s) R7 or R71-R74. Petition 870180050363, dated 12 / 06 / 2018, p. 21 / 40 16 / 16

[0043] The preceding description of the revelation is provided to enable anyone skilled in the art to make or use the revelation. Various modifications to the revelation will be readily apparent to those skilled in the art, and the generic principles set forth herein may be applied in other variations without departing from the spirit or scope of the revelation. Thus, the revelation is not intended to be limited to the examples described herein, but should be agreed upon in the broader scope compatible with the new principles and features revealed herein. Petition 870180050363, dated 12 / 06 / 2018, page 22 / 40

Claims

1 / 4 CLAIMS 1. Apparatus (300, 400), characterized in that it comprises: a first set of one or more resistors (R2, R21, R22); a second set of one or more resistors (R3, R31, R32); a current generator configured to generate a first temperature-compensated current (I2) through the first set of one or more resistors, wherein a first voltage (VSB-VB) is generated through the first set of one or more resistors based on the first temperature-compensated current; a first control circuit configured to generate a second voltage (VSB-VC) through the second set of one or more resistors, wherein the second voltage is based on the first voltage, and wherein a second temperature-compensated current (I3) is generated through the second set of resistors based on the second voltage;and a third set of one or more resistors (R7, R71, R74) through which the second temperature-compensated current (I3) flows, wherein a temperature-compensated reference voltage (VREF) is generated across the third set of one or more resistors based on the second temperature-compensated current.

2. Apparatus, according to claim 1, characterized in that the current generator comprises: a current generator with a temperature complementary to the absolute temperature, CTAT, configured to generate a CTAT current; a current generator with a temperature proportional to the absolute temperature, PTAT, configured to generate a PTAT current, wherein the first compensated temperature current comprises a combination of the CTAT current with the PTAT current.

3. Apparatus, according to claim 2, characterized in that the CTAT current generator comprises: a first device configured to generate a first CTAT voltage; and a fourth set of one or more resistors, wherein the first CTAT voltage is applied across the fourth set of one or more resistors to generate the CTAT current.

4. Apparatus according to claim 3, characterized in that the first device comprises a diode or a transistor connected by a diode.

5. Apparatus, according to claim 3, characterized in that the PTAT current generator comprises: a second device configured to generate a second CTAT voltage; a fifth set of one or more resistors configured to receive through it a PTAT voltage based on the difference between the third voltage and the second CTAT voltage, wherein the third voltage is based on the first CTAT voltage.

6. Apparatus, according to claim 5, characterized in that the second device Petition 870260059303, dated 06 / 17 / 2026, page 7 / 18 3 / 4 comprises a plurality of diodes coupled in parallel or a plurality of diode-connected transistors coupled in parallel.

7. Apparatus, according to claim 5, characterized in that the current generator additionally comprises a second control circuit configured to generate the third voltage based on the first CTAT voltage.

8. Apparatus, according to claim 7, characterized in that the second control circuit further comprises: a first operational amplifier comprising: a first input configured to receive the first CTAT voltage; a second input configured to receive the third voltage; an output configured to generate a control signal based on the first CTAT voltage and the third voltage; a first transistor including a control terminal configured to receive the control signal, wherein the first transistor is coupled between a first voltage rail and a first node; and a sixth set of one or more resistors coupled between the first node and the first input of the first operational amplifier; wherein the first set of one or more resistors is coupled between the first node and the second input of the first operational amplifier; Petition 870260059303, dated 06 / 17 / 2026, p.8 / 18 4 / 4 wherein a sixth set of one or more resistors is coupled between the second input and the first operational amplifier and a second voltage rail; and wherein the first control circuit comprises: a second transistor coupled between the second set of resistors and the third set of resistors; and a second operational amplifier including a first input coupled to the second input of the first operational amplifier, the second input coupled to a second node between the second set of resistors and the second transistor, and an output coupled to a control terminal of the second transistor.

9. Apparatus, according to claim 1, characterized in that the first control circuit comprises: a transistor coupled between the second set of resistors and the third set of resistors; and an operational amplifier including a first input coupled to the first set of resistors, a second input coupled to a node between the second set of resistors and the transistor; and an output coupled to a control terminal of the transistor. Petition 870260059303, dated 06 / 17 / 2026, page 9 / 18

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