Polar encoding and decoding method, and encoding and decoding apparatus.

Abstract

The embodiments of this patent application provide a polar coding method that includes: performing CRC coding on an information block to obtain a CRC-coded block with a length of b, where a CRC length is lcrc, an information block length is k, and b = k + lcrc; interleaving the CRC-coded block, where lpc CRC bits in an interleaved coded block are located between bits of the information block, each CRC bit of the lpc CRC bits is located after all bits checked using the CRC bit, and lpc is an integer greater than 0 and less than lcrc; and mapping the interleaved coded blocks to information bits, setting a freeze bit to an agreed fixed value, and performing polar coding on the information bits and the freeze bit to obtain a polar-coded codeword. The coding method can further improve the performance of a polar code.

Description

1 / 68 Polar encoding and decoding methods, and encoding and decoding devices. TECHNICAL FIELD

[001] Embodiments of the present invention relate to the field of wireless communications and, more specifically, to a polar encoding / decoding method and an encoding / decoding apparatus. BACKGROUND

[002] In a communications system, the reliability of data transmission is generally improved through channel coding, to ensure communication quality. Polar code, proposed by Professor Turco Arikan, is the first high-performance code that has theoretically proven to be capable of achieving Shannon capability and has low encoding / decoding complexity. Polar code is a linear block code. A coding matrix of polar code is Gn, and a coding process is xiN = uiNGn, where uiN = (ui, U2rU3, ...run) is a binary row vector of length N (namely, a mother code length), Gn is an NxN matrix, and Gn = F20(log2(2V) 1). F20(log2(2V) 1 is defined as a Kronecker product of log2N matrices F2. The matrix F2 = [1 1]

[003] In a conventional polar code encoding process, a portion of the unit bits are used to carry information and are referred to as information bits, and a set of indices of these bits is denoted as A. The other portion of bits is set to fixed values ​​that are pre-agreed upon by a transmitting end and a receiving end and are referred to as fixed bits or frozen bits, and a Petition 870250030778, dated 04 / 16 / 2025, p. 10 / 173 2 / 68 The set of fixed bit indices is represented using a complement set Acde A. The polar code encoding process is equivalent to xin = uaGn(A) ®uac Gn(Ac) . Here, Gn(A) is a submatrix obtained based on rows corresponding to the indices in set A in Gn, and Gn(Ac) is a submatrix obtained based on rows corresponding to the indices in set Acm Gn. ua is a set of information bits in uin, and the number of information bits is K; and un is a set of frozen bits in uin, the number of frozen bits is (NK), and the frozen bits are known bits. The values ​​of these frozen bits are usually set to 0. However, the fixed bits can be set randomly as long as the transmitting end and the receiving end pre-agree. When the fixed bits are set to 0, the polar code encoding output can be simplified as: xiN= uaGn (a), and xiN= uaGn (A), Gn(A) is a KxN matrix.

[004] A polar code construction process, namely, an A-set selection process, determines the polar code performance. The polar code construction process is generally as follows: a total of N polarized channels corresponding respectively to N rows of the encoding matrix are determined based on a mother code length N; the reliability of the polarized channels is calculated; and indices of the first K polarized channels with relatively high reliability are used as elements in the A-set, and indices corresponding to (NK) remaining polarized channels are used as elements in the Ac-set of fixed bit indices. The A-set determines information bit positions, and the Ac-set Petition 870250030778, dated 04 / 16 / 2025, p. 11 / 173 3 / 68 determines fixed bit positions.

[005] At one end of decoding, the polar code can be decoded sequentially from a first bit using a successive cancellation decoding algorithm (SC for short). A successive cancellation list decoding algorithm (SCL for short) is an improvement over the SC decoding algorithm. Based on the SCL decoding algorithm, a plurality of candidate decoding results is maintained in a decoding process. In SCL, the decoding process is considered a path search process. Specifically, a first bit is used as a root node for path extension, and a metric is used to evaluate the path. The metric is dynamically updated with path extension according to a predefined rule.For each extension time (when a subsequent bit is decoded), L candidate paths whose path metrics are ideal in a current layer are maintained until the extension is executed to a final layer (a final bit is decoded). Finally, a path whose metric is ideal in the L candidate paths is used as the decoding output. Maximum likelihood decoding performance can be obtained by using the SCL decoding algorithm.

[006] To improve the performance of a polar code, a polar CA code is proposed to improve the polar code in the state of the art. The polar CA code is a concatenated CRC (Cyclic Redundancy Check) polar code. Petition 870250030778, dated 04 / 16 / 2025, p. 12 / 173 4 / 68 cyclic redundancy check), and is referred to as a polar CA code. CRC encoding is performed on a block of information, and then CRC-encoded bits are mapped to information bits. Correspondingly, during decoding, a CA-SCL (CRC-Assisted Successive Cancellation List) decoding algorithm is used for decoding; in other words, a candidate path that passes the CRC is selected, from the L candidate path outputs in SCL decoding, as the decoding output. If a correct path is detected due to a low metric at an intermediate CA-SCL decoding node, a subsequent CRC check cannot improve the SCL decoding performance. SUMMARY

[007] Embodiments of this patent application provide a polar coding method, a coding apparatus, a decoding method and a decoding apparatus, to further improve the performance of a polar AC code.

[008] According to a first aspect, a coding method is provided which includes: Perform CRC encoding on a block of information to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, a block of information length is K, and B = K + Lcrc; Interleave the CRC-encoded block, where Lpc CRC bits in an interleaved encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; and Petition 870250030778, dated 04 / 16 / 2025, page 13 / 173 5 / 68 map the interleaved encoded block to information bit positions, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a polar encoded codeword, where the information bit positions are positions corresponding to B polarized channels with ideal reliability, a freeze bit position is a position corresponding to one of the remaining NB polarized channels, and N is a mother code length of a polar code.

[009] According to a second aspect, an encoding device is provided which includes: a CRC encoding unit, configured to perform CRC encoding on a block of information to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, a block of information length is K, and B = K + Lcrc; an interleaving unit, configured to interleave the CRC-encoded block, where Lpc CRC bits in an interleaved encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; and a polar encoding unit, configured to: map the encoded block obtained after interleaving is performed by the interleaving unit to information bit positions, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a word of Petition 870250030778, dated 04 / 16 / 2025, page 14 / 173 6 / 68 encoded polar code, where the positions of the information bits are positions corresponding to B polarized channels with ideal reliability, a freeze bit position is a position corresponding to one of the remaining NB polarized channels, and N is a mother code length of a polar code.

[0010] According to a third aspect, a coding device is provided which includes: A memory, configured to store a program; and a processor, configured to execute the program stored in memory, where when the program is executed, the processor is configured to: perform CRC encoding on a block of information to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, a block of information length is K, and B = K + Lcrc; interleaf the CRC-encoded block, where Lpc CRC bits in an interleaved encoded block are located between bits of the block of information, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;and map the interleaved encoded block to information bits, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a polar encoded codeword, where the positions of the information bits are positions corresponding to B polarized channels with ideal reliability, a freeze bit position is a position corresponding to one of the remaining NB polarized channels, and N is a mother code length of a polar code. Petition 870250030778, dated 04 / 16 / 2025, p. 15 / 173 7 / 68

[0011] According to a fourth aspect, an encoding device is provided which includes: at least one input end, configured to receive a block of information; A signal processor, configured to: perform CRC encoding on the information block to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B = K + Lcrc; interleave the CRC-encoded block, where Lpc CRC bits in an interleaved encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;and map the interleaved encoded block to information bits, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a polar-encoded codeword, where the positions of the information bits are positions corresponding to B polarized channels with ideal reliability, a position of the freeze bit is a position corresponding to one of the remaining NB polarized channels, and N is a mother code length of a polar code; and at least one output end, configured to output the polar-encoded codeword obtained by the signal processor.

[0012] According to a fifth aspect, a polar coding method is provided which includes: obtain information bit positions and a bit Petition 870250030778, dated 04 / 16 / 2025, p. 16 / 173 8 / 68 frozen in the bits to be decoded, where the information bits include K bits of an information block and Lcrc cyclic redundancy check bits CRC, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; Deinterleaf T candidate paths whose metrics are ideal on the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and perform a CRC check on the T candidate paths, and use, as decoding output, a block of information in a candidate path that passes the CRC check and whose path metric is ideal.

[0013] According to a sixth aspect, an encoding device is provided which includes: a retrieval unit, configured to obtain bit positions of information and a bit frozen in the bits to be Petition 870250030778, dated 04 / 16 / 2025, p. 17 / 173 9 / 68 decoded, where the information bits include K bits of an information block and Lcrc CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; A decoding unit, configured to: sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; an interleaving unit, configured to deinterleaf T candidate paths whose metrics are ideal on the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and a CRC verification unit, configured to: perform a CRC check on the T candidate paths and use, as decoding output, a block of information on a candidate path that passes the CRC check and whose path metric is ideal.

[0014] According to a seventh aspect, an encoding device is provided which includes: Petition 870250030778, dated 04 / 16 / 2025, p. 18 / 173 10 / 68 a memory, configured to store a program; and a processor, configured to execute the program stored in memory, where when the program is executed, the processor is configured to: obtain information bit positions and a freeze bit in the bits to be decoded, where the information bits include K bits of an information block and Lcrc CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all the bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L;and perform a CRC check on the T candidate paths, and use, as decoding output, a block of information in a candidate path that passes the CRC check and whose path metric is ideal. Petition 870250030778, dated 04 / 16 / 2025, p. 19 / 173 11 / 68

[0015] According to an eighth aspect, a decoding device is provided which includes: at least one input end, configured to receive information regarding bits to be decoded; A signal processor, configured to: obtain information bit positions and a freeze bit in the bits to be decoded, where the information bits include K bits of an information block and Lcrc CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value for each CRC bit of the Lpc CRC bits is determined based on a bit value from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and perform a CRC check on the T candidate paths;and at least one output unit, configured to use, as a decoding output, a block of information in one; Petition 870250030778, dated 04 / 16 / 2025, p. 20 / 173 12 / 68 candidate path that passes the CRC verification and whose path metric is ideal.

[0016] With reference to all the aspects mentioned above, in a first possible implementation, the interleaving of the CRC encoded block includes: interleaving the CRC encoded block by means of an interleaving sequence π = [%i, π2, ..., πη], and permuting a sequence of CRC encoded bits [b1, b2, ..., bn] into bπ1, bπ2, ..., bπn, where n is an integer greater than 0 and less than or equal to B, and a value of πn represents a bit position sequence number that is of a bit of order n of the interleaved encoded block and that is in the CRC encoded block before the interleaving is performed.

[0017] With reference to all the aspects mentioned above and to the first possible implementation, in a second possible implementation, Lpc, Lcrc, T and an upper false alarm rate limit FAR that is specified in a communications system satisfy the following condition: Lpc < Lcrc — log2T + log2FAR.

[0018] With reference to all the aspects mentioned above and to both possible implementations mentioned above, in a third possible implementation, Lcrc is 27 and Lpc is 8; or Lcrc is 24 and Lpc is 6; or Lcrc is 22, 23, 14 or 15 and Lpc is 4.

[0019] With reference to any of the fifth to eighth aspects, in a fourth possible implementation, the metric is a PM path metric.

[0020] With reference to any of the fifth to eighth aspects or to the fourth possible implementation, in a fifth possible implementation, if none of the T candidate paths Petition 870250030778, dated 04 / 16 / 2025, p. 21 / 173 13 / 68 passes the CRC check, a block of information from a path whose metric is ideal in the T candidate paths is used as decoding output, or it is determined that the decoding fails.

[0021] With reference to the first to fourth aspects, in a sixth possible implementation, the CRC encoding is a CRC encoding time. The CRC encoded block is obtained after only one CRC encoding time is executed based on the length Lcrc.

[0022] With reference to all aspects and all possible implementations mentioned above, in a sixth possible implementation, Lcrc and Lpc satisfy the following relation: Lcrc - Lpc = 10; or Lcrc - Lpc = 18.

[0023] With reference to all aspects and all possible implementations mentioned above, in a seventh possible implementation, Lpc = 1 and Lcrc = 11; Lpc = 2 and Lcrc = 12; Lpc = 4 and Lcrc = 14; Lpc = 6 and Lcrc = 16; or Lpc = 8 and Lcrc = 18.

[0024] With reference to all aspects and all possible implementations mentioned above, in an eighth possible implementation, Lpc = 1 and Lcrc = 19; Lpc = 2 and Lcrc = 20; Lpc = 4 and Lcrc = 22; Lpc = 6 and Lcrc = 24; or Lpc = 8 and Lcrc = 26.

[0025] According to a ninth aspect of this patent application, a computer-readable storage medium is provided. The computer-readable storage medium stores an instruction, wherein when the instruction is executed on a computer, the computer is able to execute the encoding method or the decoding method in the aspects mentioned above or in possible implementations. Petition 870250030778, dated 04 / 16 / 2025, page 22 / 173 14 / 68

[0026] According to another aspect of this patent application, a computer program product is provided that includes an instruction, where when the instruction is executed on a computer, the computer is able to execute the encoding method or the decoding method in the aspects or possible implementations mentioned above.

[0027] According to yet another aspect of this patent application, a computer program is provided whereby when the computer program is run on a computer, the computer is able to execute the encoding method or the decoding method in the aspects or possible implementations mentioned above.

[0028] In the embodiments of this patent application, after CRC encoding, interleaving is performed on the CRC encoded block, so that a portion of the CRC bits in the interleaved encoded block is distributed among the bits of the information block, and each CRC bit in the CRC bit portion is located after all bits checked using the CRC bit; in other words, each of the CRC bit portions is used to check only bits that are from the information block and are before the CRC bit. In the decoding process, the CRC bit portion is used as parity check bits for decoding. If a previous information bit is decoded incorrectly, a CRC bit value that is calculated based on the previous information bit will more likely be consistent with a received LLR.In this case, a route metric is degraded, and this incorrect route will most likely be excluded when candidate route metrics are ranked. Therefore, the... Petition 870250030778, dated 04 / 16 / 2025, p. 23 / 173 15 / 68 CA-SCL decoding performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a schematic diagram of a basic wireless communication procedure between a transmitting end and a receiving end; Figure 2(a) is a schematic diagram of path extension and metric calculation when a current bit LLR is greater than 1 according to an embodiment of this patent application; Figure 2(b) is a schematic diagram of path extension and metric calculation when a current bit LLR is less than 0 according to an embodiment of this patent application; Figure 3 is a schematic diagram of path extension and PM update in SCL decoding; Figure 4 is a schematic diagram of a polar AC encoding process; Figure 5 is a schematic diagram of a polar AC construction; Figure 6 is a schematic diagram of a coding process according to an embodiment of this patent application; Figure 7 is a schematic structural diagram of a coding apparatus according to an embodiment of this patent application; Figure 8 is a schematic flowchart of a coding method according to an embodiment of this patent application; Figure 9 is a schematic diagram of a check relationship between each special CRC bit and bits of Petition 870250030778, dated 04 / 16 / 2025, page 24 / 173 16 / 68 information before the special CRC bit according to an embodiment of this patent application; Figure 10 is a schematic diagram of a polar AC construction according to an embodiment of this patent application; Figure 11 is a flowchart of another coding method according to an embodiment of this patent application; Figure 12 is a schematic structural diagram of another coding apparatus according to an embodiment of this patent application; Figure 13 is a schematic structural diagram of yet another coding apparatus according to an embodiment of this patent application; Figure 14 is a schematic structural diagram of a decoding device according to an embodiment of this patent application; Figure 15 is a schematic flowchart of a decoding method according to an embodiment of this patent application; Figure 16 is a schematic diagram of path extension and path metric update in SCL decoding according to an embodiment of this patent application; Figure 17(a) shows the comparison between polar AC performance in an AWGN channel in a solution from this patent application and polar AC performance in an AWGN channel in a conventional solution when List = 8 and K = 32; Figure 17(b) shows the comparison between polar AC performance in an AWGN channel in a solution of this order of Petition 870250030778, dated 04 / 16 / 2025, p. 25 / 173 17 / 68 patent and performance of polar AC in an AWGN channel in a conventional solution when K = 48; Figure 18 is a schematic structural diagram of another decoding apparatus according to an embodiment of this patent application; and Figure 19 is a schematic structural diagram of yet another decoding apparatus according to an embodiment of this patent application. DESCRIPTION OF MODALITIES

[0030] The technical solutions in the embodiments of this patent application can be applied to a 5G communications system or a future communications system, or they can be applied to various other communications systems such as a global system for mobile communications (GSM), a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) system, a general packet radio service (GPRS) system, a long-term evolution (LTE) system, a frequency division duplex (FDD) LTE system, a time division duplex (TDD) LTE system, and a universal mobile telecommunications system (UMTS).

[0031] Figure 1 shows a basic wireless communication procedure. At one end of the transmission, a source is sent after source encoding, channel encoding, and digital modulation have been sequentially performed. Petition 870250030778, dated 04 / 16 / 2025, page 26 / 173 18 / 68 at the source. At one receiving end, the source undergoes digital demodulation, channel decoding, and source decoding sequentially, and then a collector is emitted. Polar code can be used for channel encoding and decoding, and SC decoding and SCL decoding can be used during channel decoding. An SCL decoding algorithm is an improvement over an SC decoding algorithm. A plurality of candidate paths is maintained in a decoding process, and one path is selected as a decoding result based on a metric of each candidate path.

[0032] For an l-order path metric PMl(i), that is, a path metric (English: path metric, abbreviated PM) of the l-order path when an i-order bit is decoded, a calculation formula is shown as formula (1) (assuming that when LLR>0, a value corresponding to LLR is 0, or when LLR<0, a value corresponding to LLR is 1): ' PM;(i — 1), when the value corresponding to LLR is PMl (i) = - consistent with a decision result PMl(i — 1) + \LLRlfí)\, when the value corresponding to LLR is inconsistent with a decision result formula (1) where LLR(i) represents a log-likelihood ratio (LLR) of the current bit. The value corresponding to LLR can be 0 or 1. For example, when LLR<0, the value corresponding to LLR is 1, or when LLR>0, the value corresponding to LLR is 0. Of course, in real-world applications, another method can be used alternatively. For example, when LLR<0, the value corresponding to LLR is set to 0, or when LLR>0, Petition 870250030778, dated 04 / 16 / 2025, page 27 / 173 19 / 68 The value corresponding to LLR is set to 1. When LLR=0, the value corresponding to LLR can be considered 0 or 1, and can be set as desired in a real application. If the value corresponding to the LLR of the current bit is consistent with the decision result, the PM remains unchanged; or if the value (0 or 1) corresponding to the LLR of the current bit is inconsistent with the decision result, a penalty value |LLR(i)| is added to the PM. The penalty value is an absolute value of the LLR of the current bit. It can be learned from the PM calculation formula that a smaller PM indicates that the probability between a codeword corresponding to the path and a received signal is relatively high and indicates that the path metric is more desirable. Therefore, a path whose PM is minimal can ultimately be output as a decoding result.In formula (1), if the value (0 or 1) corresponding to the LLR of the current bit is inconsistent with the decision result, the penalty value |LLR(i)| can alternatively be subtracted from PM, i.e., PMl(i)=PMl(i-1)-|LLR(i)|. Correspondingly, selecting a path whose metric is ideal means selecting a path whose PM is maximal. This patent application uses formula (1) as an example for description.

[0033] In an SCL decoding process, if the current bit is a configuration bit, each path is extended to two paths, and a total of 2L paths are obtained through extension, where L is the number of candidate paths that need to be ultimately maintained. A decision result for each node is 0 or 1, and a PM for each path is calculated according to the preceding formula. Petition 870250030778, dated 04 / 16 / 2025, p. 28 / 173 20 / 68 Next, the paths obtained by extension are sorted based on PMs, L paths whose PMs are smaller are kept, and the remaining L paths are deleted. This is also referred to as pruning. If the current bit is a frozen bit, a corresponding node in each path is not extended and is directly determined as a corresponding known fixed value, and a path PM is calculated according to formula (1).

[0034] For ease of description, an example in which when LLR<0, the corresponding LLR value is 1, or when LLR>0, the corresponding LLR value is 0 is used as an example for description. As shown in Figure 2(a), if an LLR(i) of a current decoded bit is greater than 0 (a corresponding LLR value is 0), in a path extension process, if the current bit is an information bit, two paths need to be obtained by extension. If a decision result is also 0, the decision result is consistent with the corresponding LLR value (represented by 7 in Figure 2). In this case, PM(i)=PM(i1). If a decision result is 1, the decision result is inconsistent with the corresponding LLR value (represented by x in Figure 2). In this case, PM(i)=PM(i1) + |LLR(i)|. If the current bit is a frozen bit, a path is not extended, and a PM is calculated based on a known fixed value.If the known fixed value is 0 and the value corresponding to the LLR is also 0, the known fixed value is consistent with the value corresponding to the LLR. In this case, PM(i) = PM(i-1). If the known fixed value is 1, the fixed value is inconsistent with the value corresponding to the LLR. In this case, PM(i) = PM(i-1) + |LLR(i)|. As shown in... Petition 870250030778, dated 04 / 16 / 2025, p. 29 / 173 21 / 68 Figure 2(b), if an LLR(i) of a current decoded bit is less than 0 (a value corresponding to an LLR is 1), in a path extension process, if the current bit is an information bit, two paths need to be obtained by extension. If a decision result is 0, the decision result is inconsistent with the value corresponding to the LLR. In this case, PM(i)=PM(i-1) + |LLR(i)|. If a decision result is 1, the decision result is consistent with the value corresponding to the LLR. In this case, PM(i)=PM(i-1). If the current bit is a frozen bit, a path is not extended, and a PM is calculated based on a known fixed value. If the known fixed value is 0 and the value corresponding to the LLR is also 1, the known fixed value is inconsistent with the value corresponding to the LLR, and PM(i)=PM(i-1)+|LLR(i)|. If the known fixed value is 1, the fixed value is consistent with the value corresponding to the LLR, and PM(i)=PM(i-1).

[0035] Figure 3 shows an example in which two candidate paths are maintained in a decoding process of an SCL decoding algorithm when List=2. Generally, the first several bits are frozen bits, and are set to fixed values, for example, 0. Therefore, the decoding actually starts from a first bit of information. In Figure 3, a path whose PM is minimum is maintained during each extension, and two candidate paths L1 and L2 indicated by arrows are finally obtained. A PM of path L1 is finally 0,0, and a PM of the other path L2 is finally 0,2. Therefore, the path L1 whose PM is smaller, i.e., 0,0, is selected as the decoding output, and a value of one bit of information. Petition 870250030778, dated 04 / 16 / 2025, p. 30 / 173 The 22 / 68 code obtained through decoding is 0011. A polar code and a CRC (Cyclic Redundancy Check) code are concatenated to obtain a concatenated code, referred to as a polar CA code. After a CRC check is performed, a path that passes the CRC is selected as the decoding output from candidate path outputs in the SCL decoding. A CRC-assisted successive cancellation list (CA-SCL) decoding algorithm can significantly improve the performance of the polar code.

[0036] A process for constructing the polar CA code is as follows: Assuming that an information block size is Kinfo, a CRC length is Kcrc, and a mother code length of the polar code is N, Kinfo+Kcr polarized channels with higher reliability need to be selected from N polarized channels as information bits, and a remaining polarized channel is used as a freeze bit. A polar CA encoding process is shown in Figure 4. First, CRC encoding is performed on an information block, and then a CRC encoded bit is mapped to an information bit position. A fixed value agreed upon between a transmitting end and a receiving end is set in a freeze bit position. Then, polar encoding is performed to obtain a polar CA encoded block.In an SCL decoding process, the information block and the CRC bit are both unknown, and decoding is performed based on a normal SCL decoding process. After the SCL decoding is complete, L candidate decoding results are obtained, and the decoding results. Petition 870250030778, dated 04 / 16 / 2025, page 31 / 173 23 / 68 includes the information block and the CRC bit. A CRC check is performed on each candidate result starting from a path whose PM is minimum. If the path passes the CRC check, an information block in the path is used as the decoding output. If no path passes the CRC check, an information block in the path whose PM is minimum is used as the decoding output, or a decoding failure is indirectly indicated.

[0037] As shown in Figure 5, in a polar CA encoding / decoding process, all CRC bits are used as information bits for processing, and CRC bits are used to provide path selection assistance when SCL decoding ends. However, at an intermediate node in the SCL, a current path may be excluded due to an excessively large PM.

[0038] In the embodiments of this patent application, in a polar AC encoding / decoding process, a portion of CRC bits is moved to positions between bits of an information block by means of interleaving, and the values ​​of the CRC bit portion are determined based on the bit values ​​of an information block located before the CRC bits; in other words, a parity check is performed using the CRC bits on the information bits located before the CRC bits, in order to provide assistance for SCL decoding of the polar AC code. This increases the probability of excluding an incorrect path in the intermediate mode and improves the performance of the polar AC code. The CRC bit portion may also be referred to as parity check (PC) bits or special CRC bits. In either case, these special CRC bits satisfy Petition 870250030778, dated 04 / 16 / 2025, p. 32 / 173 24 / 68 under the following conditions: The special CRC bits are located between bits of an information block in an encoded sequence (interleaving sequence), and are used to verify only the bits of the information block located before the special CRC bits. Equations for verifying the special CRC bits are determined through CRC decoding; that is, the special CRC bits are used to verify which bits are determined in a CRC encoding process. Bits verified using a special CRC bit do not change after interleaving, but only the positions of the bits to be verified change, so that all bits verified using the special CRC bit are located before the special CRC bit.Thus, when the special CRC bit is decoded during decoding, a value of the special CRC bit is directly determined based on the bits checked using the special CRC bit and located before the special CRC bit. Since different parameters such as an information block length, a CRC length, and a CRC generator polynomial are always sent, the position of the special CRC bit changes and is not always a fixed position. A different number of special CRC bits can alternatively be configured according to a specific requirement. For ease of description, these bits are collectively referred to as special CRC bits as follows.

[0039] As shown in Figure 6, a coding process includes the following steps: (1) CRC Encoding: CRC encoding is executed Petition 870250030778, dated 04 / 16 / 2025, page 33 / 173 25 / 68 in a block of information to obtain a CRC-encoded block. (2) Interleaving: Interleaving is performed on the CRC encoded block. A successive SCL decoding algorithm is used. If a portion of CRC bits is used as PC bits for verification, these CRC bits are related only to the bits to be decoded located outside the CRC bits. Through interleaving, it can be guaranteed that a portion of information bits that are distributed among bits of the information block and that are verified using a CRC bit are located before the CRC bit. (3) Polar coding: An interleaved coded block is mapped to information bit positions (bit positions corresponding to relatively high-reliability biased channels). A frozen bit position corresponds to a remaining biased channel, and the frozen bit is set to an agreed fixed value, for example, 0 or 1. Polar coding is performed on the information bits and the frozen bit to obtain a polar-coded codeword.

[0040] When decoding is performed at a receiving end, the SCL decoding algorithm is used for decoding, path extension is performed on the information bits, and a decision is made based on a path metric. However, path extension is not required for a special CRC bit that is distributed among information blocks and is located after all information bits checked using the special CRC bit, and a special bit value. Petition 870250030778, dated 04 / 16 / 2025, page 34 / 173 The 26 / 68 CRC is determined based on the information bits obtained through decoding and located before the special CRC bit. Path extension is not performed on the freeze bit. The freeze bit is decoded directly as a fixed value. After SCL decoding is complete, L candidate paths are obtained, deinterleaving is performed on some or all of the L candidate paths to obtain the information block and CRC bits, a CRC check is performed on each path, and a path that passes the CRC check and whose PM is ideal is selected as the decoding output from the candidate paths. During decoding, the CRC bit can be used to select a decoding result from the candidate paths, and can also be used for error checking, i.e., to determine whether the decoding result is correct or not.During decoding, the special CRC bit can be used as a PC bit for decoding, thus providing assistance for SCL decoding. This increases the probability of excluding an incorrect path. Error checking can alternatively be performed during decoding. Once it is found that none of the paths obtained through extension can pass the check performed using the CRC bit, subsequent decoding is interrupted, that is, the decoding is terminated, and it is determined that the decoding has failed.

[0041] Since the value of the special CRC bit is determined by the values ​​of the information bits that are obtained through decoding and that are located before the special CRC bit, since the bits of Petition 870250030778, dated 04 / 16 / 2025, page 35 / 173 27 / 68 information that is obtained through decoding and that is located before the CRC special bit is incorrect when the CRC special bit is decoded, a possibility that a value of the CRC special bit that is obtained through calculation based on the information bits is inconsistent with the received value corresponding to an LLR increases. Correspondingly, when a path PM is calculated, an absolute value of the CRC special bit's LLR is added to the PM through calculation according to formula (1). This increases the path PM, so that a possibility of excluding the path in a subsequent decoding process increases.

[0042] A coding apparatus 700 shown in Figure 7 can perform a coding method shown in Figure 7. The coding apparatus 700 includes a CRC coding unit 701, an interleaving unit 702, and a polar coding unit 703. As shown in Figure 7, the coding method in this embodiment of this patent application may include the following process: 801. Perform cyclic redundancy check (CRC) encoding on a block of information to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, a block of information length is K, and B = K + Lcrc.

[0043] The 701 CRC encoding unit is configured to perform CRC encoding on a block of information to be sent to obtain K+Lcrc CRC-encoded bits. A CRC generator polynomial is [Co, Ci, ..., Cn-r], where K is a block length of information, n=K+Lcrc, and an original generator matrix of the CRC encoding is a matrix of K*n: Petition 870250030778, dated 04 / 16 / 2025, page 36 / 173 28 / 68 Gcrc — 'C0ci · CqC1Cn-k θcn-k 0

[0044] c0 Cl C?t-fc By using an elimination method The Gaussian generating matrix described above is simplified as follows: G=[IP] , where I is a K*K unitary matrix and P is a matrix K*Lcrc. The matrix G is the matrix K*n. A row number in each row can be understood as a sequence number of a bit in a corresponding information block, a column number in each column can be understood as a sequence number of a corresponding bit output after CRC encoding, and a value of each encoded CRC bit is a sum of bit values ​​corresponding to all rows whose values ​​are 1 in the column. In this case, each column of the matrix P corresponds to a CRC bit, and bits corresponding to row numbers to which values ​​of 1 in the column correspond are used as bits of the information block that are verified using the CRC bit. Lcrc=4 and K=12 are used as examples. The matrix G=[IP] is generated by means of a calculation based on a CRC-4

[10011] generator polynomial, as shown in Table 1.

[0045] In this document, CRC encoding is performed once in the information block. Table 1. CRC generating matrix with a CRC length of 4 when k=12 bl b2 b3 b4 b5 b6 b7 b8 b9 blO bll b!2 b!3 b!4 b!5 b!6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1 Petition 870250030778, dated 04 / 16 / 2025, p. 37 / 173 29 / 68 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 2 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 1 0 0 1 1

[0046] A sequence [al, a2, ..., al2] represents a block of information, and [bl, b2, ..., bl6] represents a CRC-encoded block, where bl3, bl4, bl5, and bl6 are CRC bits. It can be learned from the table that the bits of the information block to which the values ​​1 in a column corresponding to bl3 correspond are a2, a3, a4, a5, a7, a9, and al0, and the corresponding CRC-encoded bits are b2, b3, b4, b5, b7, b9, and bl0. Therefore, bl3=b2+b3+b4+b5+b7+b9+bl0, a verification equation is: b2+b3+b4+b5+b7+b9+bl0+bl3=0, and a sequence [2, 3, 4, 5, 7, 9, 10, 13] can be used to represent the verification equation. Similarly, for bl4, bl5, and bl6, verification equations based on Table 1 can be represented respectively as [3, 4, 5, 7, 9, 10, 11, 14], [4, 5, 6, 7, 9, 11, 12], and [1, 2, 3, 4, 6, 8, 9, 12].

[0047] Different CRC lengths correspond to different CRC generating polynomials. The same CRC length can correspond to a plurality of different polynomials. Several CRC lengths and their corresponding generating polynomials are listed below.

[0048] It is assumed that the length Lcrc is 14, and Petition 870250030778, dated 04 / 16 / 2025, page 38 / 173 30 / 68 corresponding polynomials [100111110011111] [101000101010011] [110111111011111] [100000000101011] [111010101110111] [110100100101111] [100111011010011] [101010010011111] [100011001000101] [100011000111101] [110011101010111] [100000000000111] [110111111111111] [100100000000101] [110111001010111] [101111111110111] [100001111010001] [101000111011101] [101010110011101] [111110111011111] [100001001011011] [100011011100011] [101110111111011]

[0049] It is assumed that corresponding polynomials [1001111001000111] CRC generators include: The Lcrc length is 15, CRC generators include: [1011111111111111] [1001111010100011] [1011011010101111] Petition 870250030778, dated 04 / 16 / 2025, page 39 / 173 31 / 68 [1001011111110011] [1001101001111001] [1010100110101101] [1000000000000011] [1011010010001111] [1000011000001101] [1010111111001111] [1110111101111111] [1100111101001011] [1100011000010111] [1000000000101001] [1011100110111101] [1001001011101101] [1001101011001011] [1011011110101011] [1101010100011011] [1010111001110101] [1100010110011001] [1001000010111001] [1110100000010101]

[0050] It is assumed that corresponding polynomials [1000111001011110011] [1000000000000100111] [1000111000101111101] [1011010000100111111] [1000011011101010111] [1010111110110101101] [1011101110010010011] [1001101010001111011] The Lcrc length is 18, CRC generators include: Petition 870250030778, dated 04 / 16 / 2025, page 40 / 173 32 / 68 [1010000111101110011] [1000000000000110001] [1001011111010100111] [1011100111110111101] [1001111011101111001] [1100101100011010011] [1110010101010100111] [1001011111011010101]

[0051] It is assumed that the length Lcrc is 19, and corresponding generating polynomials of CRC include: [11011111011010101111] [10010000000100111111] [10000001001101110101] [11011010001001100111] [10001011111000111001] [11101010111001111111] [10011110110101000101] [10000000000000100111] [10010111010110011001] [11101111011000011111] [10000000000000101001] [10100011101011110011] [10001001111011101011] [10101101000010110101] [10100001011010010011] [11101111001110001111]

[0052] It is assumed that the length Lcrc is 22, and corresponding generating polynomials of CRC include: [11000010001111110100111] [11011011100100000000001] Petition 870250030778, dated 04 / 16 / 2025, page 41 / 173 33 / 68 [10100101001101010101001] [11100100010101111010011] [10011100101001101101011] [11101111000011000101101] [11111011111000101100011] [10010111101111011111011] [11011011100000100110001] [11100010110000110100101] [10000000000000000000011] [10101011101101110100111] [11011011110110001001111] [10010010000111100101001] [10000000000000010001111] [11100101011011010100111] [10101010010101001010101] [10110111001110100100011] [10100010011100111111101] [10010001111011110001001] [10001011101111101101111]

[0053] It is assumed that the length Lcrc is 23, corresponding generating polynomials of CRC include: [101010000001101111100001] [100101101011000010110001] [101101100111100101001001] [110011100110001011100011] [100011010110001101010111] [100001010010111101100001] [100001001001111001110111] [101111001111011001000111] [100000000000000000100001] Petition 870250030778, dated 04 / 16 / 2025, page 42 / 173 34 / 68 [100000000000001010101001] [100000000000000000110111] [100100110101101010100101] [101001111011111011011101] [100101101111001110100011] [110101111000000111101011] [101111000100100000110011] [100011010011101011111001] [100011000111011011101111]

[0054] It is assumed that the length Lcrc is 2^6, corresponding generating polynomials of CRC include: [110011110000011001111011111] [111010011001101110010011111] [100111111010110111101100111] [101001000010100010111110101] [110110010010101010110010111] [111011011000010100011001111] [111110100110010001001010111] [101001010011110111100111101] [101110100000001111101001111] [101101100000111011100111111] [111010010010111110010011111] [100000000000000000001000111] [110000011011111110011101011] [100111100010110100100101011] [100000000000000000000010011] [100011101110110110000100101] [110001000111101001101011011] [100101000111110110011010111] [100001100001101100001100001] Petition 870250030778, dated 04 / 16 / 2025, page 43 / 173 35 / 68 [101100010001010100010001101] [101011110110001001001110111] [100100100011010011101111101] [101011111110111101100011111] [110010110111101111011010011]

[0055] It is assumed that the length Lcrc is 27, and corresponding generating polynomials of CRC include: [1011110000001000110001101011] [1000100001010010110100001101] [1000000000000000000000100111] [1101001100001100011000100111] [1110100010111101000101111111] [1000000000000000000000100011] [1101010011000010001101111111] [1010001101011111111100110101] [1100101101111010101000100111] [1011000011010010101111000111] [1101100001111111111000011011] [1001100101101100101100011111] [1010010000111110110010010111] [1000010010110001100000011111] [1000111010011111101010001111] 802: Interleave CRC-encoded block, where Lpc CRC bits in an interleaved encoded block are located between bits of the information block, and each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit.

[0056] The 702 interleaving unit is configured to interleave the CRC encoded block. One result of interleaving is that the Lpc CRC bits are located between Petition 870250030778, dated 04 / 16 / 2025, page 44 / 173 36 / 68 the bits of the information block, each CRC bit of the Lpc CRC bits is located after all the bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc. The fact that the 702 interleaving unit can be configured to interleave the CRC-encoded block includes: interleaving the CRC-encoded block using an interleaving sequence π = [π1, π2, ..., πη], and permuting a sequence of CRC-encoded bits [b1, b2, ..., bn] into bπ1, bπ2, ..., bπn, where n is an integer greater than 0 and less than or equal to B, and a value of πn represents a bit position sequence number that is of a bit of order n of the interleaved encoded block and that is in the CRC-encoded block before interleaving is performed.As shown in Figure 9, after interleaving, a portion of the CRC bits is distributed among the bits of the information block, and each CRC bit of the CRC bit portion is used for information block check bits that are located before the CRC bit, as shown by arrows in Figure 9.

[0057] An Lpc quantity of a portion of the CRC special bits can be set to any integer greater than 0 and less than Lcrc. For example, if Lcrc=27, an Lpc value can be any value in the range of 1 to 26, for example, it can be 8. For example, if an Lcrc value is 22, 23, 14, or 15, an Lpc value is 4. Alternatively, it can be specified that if Lcrc is within a specific range, the Lpc value is fixed. For example, if Lcrc is less than or equal to 23, the Lpc value is always set to 4.

[0058] If a false alarm rate (FAR) is considered, Petition 870250030778, dated 04 / 16 / 2025, p. 45 / 173 37 / 68 The value of Lpc is related to the CRC length Lcrc, a quantity T of paths in which CRC-assisted decoding is performed after SCL decoding, and a requirement for the false alarm rate (FAR). The false alarm rate indicates a probability of occurrence of an event in which a decoding result is incorrect, but a CRC check is successful. For example, the value of Lpc can be selected with reference to the following formula (2); LpC <lcrc- log2t + log2far fórmula (2)

[0059] In formula (2), Lpc is a part of the CRC length, Lcrc is the whole CRC length, and T is a pre-agreed quantity of candidate paths that need to pass the CRC check to select a decoding result during decoding. If there are L candidate paths, T is an integer greater than 0 and less than L.

[0060] In a communications system, an upper false alarm rate limit may be specified. For example, it is assumed that a false alarm rate required by a downlink control channel in NR 5G is less than or equal to 2-16 (blind detection is not considered), and if a quantity T of paths in which CRC-assisted decoding is performed after SCL decoding is performed in a polar code is 4, and the CRC length Lcrc is 24, a quantity of CRC bits that can be used for a parity check is Lpc<(24-2-16)=6. It is assumed that a false alarm rate required by a downlink control channel is less than or equal to 28, and if a quantity T of paths in which it is performed Petition 870250030778, dated 04 / 16 / 2025, p. 46 / 173 38 / 68 CRC-assisted decoding after SCL decoding is performed on a polar code for 8, and the CRC length Lcrc is 24, a number of CRC bits that can be used for a parity check is Lpc<24-3-8=13.

[0061] In one implementation, fixed values ​​of Lcrc and Lpc can be calculated using Lpc=Lcrc—log2T+log2FAR, that is, Lcrc-Lpc=log2T-log2FAR. For example, if FAR=2-16 and T=4, LcrcLpc=18; if FAR=2-8 and T=4, Lcrc-Lpc=10; if FAR=2-16 and T=8, Lcrc-Lpc=19; or if FAR=2-8 and T=8, Lcrc-Lpc=11. Of course, a value of (Lcrc-Lpc) varies with values ​​of T and FAR. Different combinations can alternatively be configured based on the value of (Lcrc-Lpc) and stored at an encoding end and a decoding end. For example, when LcrcLpc=10, Lpc and Lcrc can be: Lpc=1 and Lcrc=11; Lpc=2 and Lcrc=12; Lpc=4 and Lcrc=14; Lpc=6 and Lcrc=16; or Lpc=8 and Lcrc=18. When Lcrc-Lpc=18, Lpc and Lcrc can be: Lpc=1 and Lcrc=19; Lpc=2 and Lcrc=20; Lpc=4 and Lcrc=22; Lpc=6 and Lcrc=24; or Lpc=8 and Lcrc=26.

[0062] A CRC encoded bit is usually located in the last position of an encoded block. As shown in Table 1, b13, b14, b15, and b16 are located after b1, b2, ..., and b12. At the decoding end, a CRC check is performed after decoding of all information blocks and CRC bits is complete. To allow a portion of CRC bits to be checked before the decoding terminals, the bit positions of an information block and the CRC bits can be changed by interleaving, so that some of the CRC bits are located between bits of Petition 870250030778, dated 04 / 16 / 2025, page 47 / 173 39 / 68 information, and bits of a block of information to be verified are also located before the CRC bits.

[0063] Merging can be performed on the CRC-encoded block [b1, b2, ..., bn] using the merge sequence π = [%i, π2, ..., πη], where each element value in π is a sequence number of the CRC-encoded block, and represents a merged encoded block C = [Ci, C2, ..., Cn] = ^πχ, bπ2, ..., bπn]. A Table 1 is used as an example. The merge sequence can be π = [2, 3, 4, 5, 7, 9, 10, 13, 8, 6, 11, 14, 12, 1, 15, 16], and represents a merge sequence C = [C1, C2, ..., C12] = [b2, b3, b4, b5, b7, b9, b10, b13, b8, b6, b11, b14, b12, b1, b15, b16], where underlined bits are CRC bits, and a correspondence between bits before and after merge is shown in Table 2. It can be learned that a CRC bit b13 is moved to a position of C8 after merge, and b2, b3, b4, b5, b7, b9, and b10 before b8 are all bits checked using b13, and are corresponding C1, C2, C3, C4, C5, C6, and C7, respectively. b14 is moved to a position of C12 after interleaving, and b3, b4, b5, b7, b9, b10, and b11 are all bits checked using b14, and are respectively corresponding to interleaved C2, C3, C4, C5, C6, C7, C9, C10, and C11, which are also located before b14.The positions of b15 and b16 are not changed, but the positions of bits checked using b15 and b16 are changed. The bits b4, b5, b6, b7, b9, b11, and b12 checked using b15 correspond to C3, C4, C10, C5, C6, C11, and C13 interleaved. The bits b1, b2, b3, b4, b6, b8, b9, and b12 checked using b16 are... Petition 870250030778, dated 04 / 16 / 2025, p. 48 / 173 40 / 68 corresponding to interleaved C14, Ci, C2, C3, C10, C9, Cg, and C13. For the sequence number of the interleaved encoded block, verification equations are updated to: C1 + C2 + C3 + C4 + C5 + C6 + C7 + C8=0; C2 + C3 + C4 + C5 + C6 + C7 + C9 + C10 + C11 + C12=0; C3 + C4 + C10 + C5 + C6 + C11 + C13 + C15=0; Θ C14+C1+C2+C3+C10+C9+C6+C13+C16=0.

[0064] Verification equations represented by sequences are as follows: [1, 2, 3, 4, 5, 6, 7, 8]; [2, 3, 4, 5, 6, 7, 9, 10, 11, 12]; [3, 4, 10, 5, 6, 11, 13, 15]; and [14, 1, 2, 3, 10, 9, 6, 13, 16]. Table 2 b 2 b 3 b 4 b 5 b 7 b 9 b1 0 b1 3 b 8 b6 b1 1 b1 4 b1 2 b1 b1 5 b1 6 C1 C2 C3 C4 C5 Cg C7 C8 C9 C1 0 C11 C12 C13 C1 4 C15 C16

[0065] In an example in Table 2, b13 is moved to a position that is after all bits checked using b13 and that is as close to the front as possible. This is not limited to this. For example, b13 can alternatively be moved to a position that is near the back, for example, moved to a position after b8. Similarly, b14 can be moved to a position after b12. b13 and b14 are referred to as CRC special bits. After interleaving, the CRC special bits are distributed among bits of the information block, and all bits of information blocks checked using the CRC special bits are located before the CRC special bits. The remaining CRC bits b15 Petition 870250030778, dated 04 / 16 / 2025, page 49 / 173 41 / 68 and b16 may not be used as special CRC bits, and may be used as normal CRC bits for a CRC check. The CRC check is performed after the decoding terminals and is used to select a candidate path. The two CRC bits are located at the end, or may be moved to any other position in an interleaving process. For example, an interleaving sequence π = [2, 3, 15, 4, 5, 16, 7, 9, 10, 8, 13, 6, 11, 14, 12, 1] may be used. A difference from an interleaving mode shown in Table 3 lies in the fact that b13 is moved to a position after b8, and b15 and b16 are also distributed among the bits of the information block. Table 3 b2 b3 b15 b4 b5 b16 b7 b9 b10 b8 b13 b6 b11 b14 b12 b1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 803: Map the interleaved encoded block to information bits, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a polar encoded codeword.

[0066] The 703 polar encoding unit is configured to: map the interleaved encoded block to information bits, set the freeze bit to the agreed fixed value, and perform Arikan polar encoding on the information bits and the freeze bit to obtain the polar encoded codeword. The codeword obtained through encoding may also be referred to as an encoded block, an encoded sequence, or similar. The positions of the information bits correspond to the first B polarized channels of the polarized channels of Petition 870250030778, dated 04 / 16 / 2025, page 50 / 173 42 / 68 polar codes that are ranked based on reliability in descending order, a bit corresponding to one of the remaining (NB) polarized channels is used as a freeze bit and is set to an agreed fixed value, and N is a mother code length of the polar code.

[0067] As shown in Figure 10, the polar code, the information block, and the CRC bits constructed in this embodiment of this patent application are distributed together in a more reliable polarized channel, and the freeze bit is distributed in a polarized channel whose reliability is lower than that of the information bits. After the interleaved encoded block is mapped to the information bit positions corresponding to the polarized channels, the CRC bits are distributed among the information block bits. During decoding, a portion of the CRC bits are used as parity check bits. This can improve the probability of excluding an incorrect path during CA-SCL decoding. Furthermore, a remaining CRC bit can still be used for a CRC check.Once a verification equation for a specific CRC bit is determined in a CRC verification process, the verification equation does not need to be configured separately.

[0068] In step 802, the collation sequence can be predefined after calculation, or it can be calculated in real time during an encoding process. There are a plurality of methods for determining the collation sequence. Some examples are provided below.

[0069] The interleaving sequence π is calculated based on a CRC generating matrix, in the CRC length Lcrc, Petition 870250030778, dated 04 / 16 / 2025, page 51 / 173 43 / 68 in the bit length of information K and in the quantity Lpc of special CRC bits, and a process may include the following steps: (1) Elementary row permutation is performed on the CRC spanning matrix G=[IP] to obtain G=[I' P']. (a) By means of row permutation, the first p1 rows in a first column of P' are 1, and all subsequent elements are 0. A row of order (p1+1) to a row of order (p1+p2) in a second column are 1, and all subsequent elements are 0. By analogy, a row of order (p1+p2...+pn-1+1) in a column of order (n-1) is 1, and all subsequent elements are 0. (b) An initial merging sequence πο is obtained based on column sequence numbers corresponding to elements 1 in each row of P. (2) Lpc rows are inserted into P' to obtain P”. The special CRC bits corresponding to Lpc columns in P' are selected, and then P' is processed to columns corresponding to all CRC bits column by column as follows: (a) If a column of order i corresponds to a special CRC bit, a line is inserted below a line in which a last element 1 in the column of order i is located, and a line number is written. An element of order i in the inserted line is 1, and the remaining elements are 0. (b) If a column of order i corresponds to a common CRC bit, a line is inserted below any line, and a line number is written. An element of order i in the inserted line is 1, and the elements Petition 870250030778, dated 04 / 16 / 2025, p. 52 / 173 44 / 68 remaining equals 0. (3) P” is read. For the Lpc columns corresponding to the special CRC bits in P”, a set of row sequence numbers to which elements 1 correspond is read column by column. For the column of order i, a set read represents a PCFi check equation. (4) Based on the line number of the inserted line recorded in step (2), a sequence %p = [K+1, K+2, ..., K+Lcrc] is sequentially inserted into the initial merging sequence πο to obtain a final merging sequence π = [πι, π2, ..., πη], and a final verification equation is obtained.

[0070] It should be noted that an operation process for matrix P in steps (1) and (2) is not unique, provided that a last element 1 in each column of the Lpc columns corresponding to the special CRC bits is located in the row entered in step (2).

[0071] CRC-4 is used below as an example to describe a process for generating the interleaving sequence.

[0072] (1) The matrix G=[IP] is generated by means of a calculation based on a generating polynomial [1 0 0 1 1] of CRC-4 when K=12, as shown in Table 1. Row permutation is performed on the generating matrix G. A second row, a third row, a fourth row, a fifth row, a seventh row, a ninth row and a tenth row are permuted to a first row, the second row, the third row, the fourth row, the fifth row, the sixth row and the seventh row based on row numbers corresponding to elements 1 in a thirteenth column; Petition 870250030778, dated 04 / 16 / 2025, page 53 / 173 45 / 68 an eleventh row is permuted to the tenth row based on row numbers corresponding to elements 1 in a fourteenth column; a twelfth row is permuted to the eleventh row based on row numbers corresponding to elements 1 in the fifteenth column; and G=[I' P'J is finally obtained, as shown in Table 4. Based on a square matrix 1' to the left of G', column sequence numbers corresponding to elements 1 are read row by row to obtain the initial merging sequence πο=[2, 3, 4, 5, 7, 9, 10, 8, 6, 11, 12, 1], where πο indicates the initial merging performed on the information block. Table 4 bl b2 b3 b4 b5 b6 b7 b8 b9 blO bll b!2 b!3 b!4 b!5 b!6 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[0073] (2) A row is inserted into P' to obtain P. An element 1 in the inserted row may be adjacent to a last element 1 in the column in P', or it may be separated from a last element 1 in the column in P' by several rows. A Petition 870250030778, dated 04 / 16 / 2025, page 54 / 173 46 / 68 inserted row represents a position of an interleaved CRC bit. For example, a row is inserted above each of an eighth row, a twelfth row, a fourteenth row, and a sixteenth row of matrix P' sequentially, and a sequence of inserted row numbers is [8, 12, 14, 16], as shown in Table 5.

[0074] (3) CRC bits [13, 14, 15, 16] are inserted into the initial collation sequence at positions [8, 12, 14, 16], to obtain a final collation sequence π = [2, 3, 4, 5, 7, 9, 10, 13, 8, 6, 11, 14, 12, 15, 1, 16] . The four-bit CRC verification equations can be represented sequentially as follows: [1, 2, 3, 4, 5, 6, 7, 8], [2, 3, 4, 7, 9, 10, 11, 12], [3, 4, 5, 6, 10, 11, 13, 14] and [1, 2, 3, 6, 9, 10, 13, 15, 16].

[0075] The positions of the inserted lines are not limited. The bits of the information block that satisfy the check may be located before the special CRC bits and as close as possible to the front, and the insertion positions of common CRC bits may be random. For example, a row can be inserted above each of the ninth row, the thirteenth row, the fourteenth row, and the sixteenth row of the matrix P' sequentially, and a sequence of inserted row numbers is [9, 13, 14, 16], as shown in Table 6. The CRC bits [13, 14, 15, 16] are inserted into the initial collation sequence at positions [9, 13, 14, 16], to obtain a final collation sequence π = [2, 3, 4, 5, 7, 9, 10, 8, 13, 6, 11, 12, 14, 15, 1, 16]. The four-bit CRC verification equations can be represented sequentially as follows: [1, 2, 3, 4, 5, 6, 7, 9], [2, 3, 4, Petition 870250030778, dated 04 / 16 / 2025, p. 55 / 173 47 / 68 [3, 4, 5, 6, 10, 11, 13, 14] [1, 2, 3, 7, 8, 10, 11, 13] 6, 9, 10, 13, 15, 16] . Table 5 1 2 3 4 1 1 0 0 1 2 1 1 0 1 3 1 1 1 1 4 1 1 1 0 5 1 0 1 0 6 1 0 1 1 7 1 1 0 0 8 1 0 0 0 9 0 1 0 1 10 0 1 1 1 11 0 1 1 0 12 0 1 0 0 13 0 0 1 1 14 0 0 1 0 15 0 0 0 1 16 0 0 0 1 Table 6 1 2 3 4 1 1 0 0 1 2 1 1 0 1 3 1 1 1 1 4 1 1 1 0 5 1 0 1 0 6 1 0 1 1 7 1 1 0 0 Petition 870250030778, dated 04 / 16 / 2025, page 56 / 173 48 / 68 0 1 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1

[0076] Figure 11 is a schematic flowchart of another coding method according to an embodiment of this patent application. The method can be performed by the coding apparatus shown in Figure 7 or by a coding apparatus shown in Figure 12 or Figure 13. The method includes the following steps: 1101: Obtain a CRC length Lcrc and a CRC polynomial. This step can be performed by a 701 acquisition unit in Figure 7, a 1202 processor in Figure 12, or a 1302 signal processor in Figure 13. The CRC length Lcrc can be pre-configured at a transmit end and a receive end in a communications system. 1102: Perform CRC encoding on a block of information. This step can be performed by the CRC encoding unit 701 in Figure 7, the processor 1202 in Figure 12, or the signal processor 1302 in Figure 13.

[0077] It is assumed that A=K, B=K+Lcrc, a sequence input in CRC encoding is ao, ai, ao, . .., aA-i, check bits generated after CRC encoding are po, pi, ..., pLcrc-i, and a sequence output after encoding of Petition 870250030778, dated 04 / 16 / 2025, page 57 / 173 49 / 68 CRC is bi, b2, ..., bB-1. The sequence obtained by CRC encoding satisfies formula (3). í bk= ak, for k = 0,1,2,..., A — 1 [bk= pk-A, for k = A, A + 1, A + 2,..., B — 1 formula (3) 1103: Obtain an interleaved sequence π = [πι, π2, ..., %b] , where the interleaved sequence can be predefined, or can be obtained by calculation based on a CRC generator matrix, an information block length and a CRC length Lcrc. By interleaving, Lpc CRC bits are located between information block bits, and information bits to be checked are located before the CRC bit. Lpc can be a smaller amount than Lcrc, or can be selected based on a range determined by formula (2) . Lpc is selected according to a predefined rule, and can be configured at the transmit end and at the receive end in the communications system. 1104: Interleaf, based on the interleaving sequence, the sequence b1, b2, ..., bB-1 emitted after CRC encoding to obtain an interleaving sequence Co, C1, ..., Cc1, where C=B. Values ​​of the sequence Co, C1, ..., Cc-1 correspond to 6π1, bπ2, ..., bπB. 1105: Set values ​​of the information bits and a freeze bit to obtain d1, d2, ..., dD-1, where D=N and N is a mother code length of a polar code. This step can be performed by the polar encoding unit 703 in Figure 7, by the processor 1202 in Figure 12, or by the signal processor 1302 in Figure 13. The set values ​​of the information bits and the freeze bit are obtained based on formula (4). Petition 870250030778, dated 04 / 16 / 2025, p. 58 / 173 50 / 68 {di = Cj, ic a set of information bits or a set of CRC bits di - 0, i E a set of frozen bits formula (4) 1106: Perform Arikan polar encoding to output an encoded sequence ec, e1, e2, ..., θε-1, where E=N. A calculation process in polar encoding can be represented using formula (5) below. This step can be performed by the 703 polar encoding unit in Figure 7. [ec, ei, e2, ..., eE-i] = [do, di, d2, ..., dD-i]-F20n, where n=log2N. formula (5)

[0078] Optionally, the method may also include step 1105: Perform rate matching on the encoded sequence, and output an encoded sequence F0, F1, F2, ..., Ff-1 after rate matching, where F=M, and M is a target code length. If the target code length M is different from the mother code length N, rate matching is performed on the encoded sequence obtained in step 1105, for example, rate matching is performed using a repetition, shortening, or punching method. When the mother code length N is less than the target code length M, (MN) bits may be repeated in the encoded sequence to obtain an encoded sequence of the target code length M.If the length of the parent code N is greater than the length of the target code M, (N—M) bits can be punched or shortened to obtain an encoded sequence of the length of the target code M, where a punching or shortening solution can be predefined. Step 1105 can be performed by a rate matching unit (not shown in the figures). Petition 870250030778, dated 04 / 16 / 2025, page 59 / 173 51 / 68 figures) in the encoding device in Figure 7, in processor 1202 in Figure 12 or in signal processor 1302 in Figure 13.

[0079] As shown in Figure 12, this patent application provides another encoding apparatus 1200 that can implement the encoding method in this patent application. The encoding apparatus 1200 includes a memory 1201 and a processor 1202.

[0080] Memory 1201 is configured to store a program.

[0081] Processor 1202 is configured to: execute the program stored in memory and, when the program is executed, execute the encoding method shown in Figure 8. For example, the method includes: performing CRC encoding on a block of information to obtain a CRC-encoded block with a length of B.Where a CRC length is Lcrc, an information block length is K, and B = K + Lcrc; interleave the CRC-coded block, where Lpc CRC bits in an interleaved coded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; and map the interleaved coded block to information bits, set a freeze bit to an agreed fixed value, and perform polar coding on the information bits and the freeze bit to obtain a polar-coded codeword, where positions of the information bits are positions corresponding to B polarized channels with ideal reliability, a position of the freeze bit is a position corresponding to one of the NB. Petition 870250030778, dated 04 / 16 / 2025, pp. 60 / 173 52 / 68 remaining polarized channels, and N is a mother code length of a polar code.

[0082] For content such as an Lpc quantity of special CRC bits, an interleaving sequence, and a generation method, reference may be made to the aforementioned encoding method. Memory 1201 may be a physically independent unit, or it may be integrated into a processor 1202. For other content related to the encoding method, reference may be made to Figure 8 and related parts in the embodiment corresponding to Figure 8, and details are not described in this document.

[0083] The encoding device in Figure 12 may also include a transmitter (not shown in the figure), configured to send an encoded block obtained after polar encoding is performed on the information bits and the freeze bit by processor 1202.

[0084] As shown in Figure 13, this patent application provides yet another encoding apparatus 1300 that can implement the encoding method in this patent application. The encoding apparatus 1300 includes at least one input end 1301, a signal processor 1302 and at least one output end 1303.

[0085] At least one input end 1301 is configured to receive a block of information.

[0086] The 1302 signal processor is configured to: perform CRC encoding on the information block to obtain a CRC-encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B = K + Lcrc; interleave the CRC-encoded block, where Lpc CRC bits in an encoded block Petition 870250030778, dated 04 / 16 / 2025, pp. 61 / 173 Interleaved 53 / 68 bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc; and map the interleaved encoded block to information bits, set a freeze bit to an agreed fixed value, and perform polar encoding on the information bits and the freeze bit to obtain a polar encoded codeword, where positions of the information bits are positions corresponding to B polarized channels with ideal reliability, a position of the freeze bit is a position corresponding to one of the remaining NB polarized channels, and N is a mother code length of a polar code.

[0087] At least one output end 1303 is configured to output the encoded block obtained by the signal processor 1302.

[0088] For content such as an Lpc quantity of special CRC bits, an interleaving sequence, and a generation method, reference may be made to the aforementioned encoding method. Optionally, the 1302 signal processor may be implemented using hardware, for example, a baseband processor, a processing circuit, an encoder, or an encoding circuit. For other content related to the encoding method, reference may be made to Figure 8 and related parts in the embodiment corresponding to Figure 8, and details are not described in this document.

[0089] The encoding device in Figure 12 may also include a transmitter (not shown in the figure), configured Petition 870250030778, dated 04 / 16 / 2025, pp. 62 / 173 54 / 68 to send the encoded block output through the output end (output) 1303.

[0090] The encoding apparatus in this patent application may be any device with a wireless communications function, for example, an access point, a station, user equipment, or a base station.

[0091] A 1400 decoding apparatus shown in Figure 14 can be configured to perform a decoding method in this patent application. As shown in Figure 15, a decoding process includes the following process: 1501: Obtain information bit positions and a frozen bit in the bits to be decoded.

[0092] A 1401 acquisition unit is configured to obtain the positions of the information bits and the freeze bit in the bits to be decoded, where the information bits include K bits of an information block and Lcrc bits of CRC, Lpc bits of CRC are located between bits of the information block, and each CRC bit of the Lpc bits of CRC is located after all bits checked using the CRC bit. The 1401 acquisition unit can obtain the positions of the information bits and the freeze bit based on a biased channel reliability ranking sequence, where the reliability of biased channels corresponding to the information bits is greater than the reliability of a biased channel corresponding to the freeze bit. Specifically, based on the biased channel reliability ranking sequence, the 1401 acquisition unit selects K + Lcrc most reliable biased channels as information bits, and uses the channels Petition 870250030778, dated 04 / 16 / 2025, pp. 63 / 173 55 / 68 polarized remaining as frozen bits, where K is a block size of information, and Lcrc is a quantity of CRC bits. 1502: Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal.

[0093] A 1402 decoding unit is configured to: sequentially decode the bits to be decoded using the successive cancellation list (SCL) decoding algorithm, and output the L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is checked using the CRC bit, and which is located before the CRC bit, and remaining CRC bits (Lcrc-Lpc) are decoded in a decoding mode of the information bits.

[0094] In an SCL decoding process, a CRC bit is used as an information bit for decoding and is an unknown bit, and path extension needs to be performed in the decoding process. At one end of the encoding, values ​​of a portion of CRC bits are determined, through interleaving, only by information bits that are located before the CRC bits. Therefore, if the portion of CRC bits is used as parity check bits, the CRC bits are decoded Petition 870250030778, dated 04 / 16 / 2025, pp. 64 / 173 56 / 68 in a freeze-bit decoding mode, and are used as known bits for decoding, and path extension is not performed in the decoding process, but the decoding results of the CRC bit portion are determined using check equations and decoded information bits located before the CRC bit portion. Path extension does not need to be performed on the freeze-bit, since the corresponding bit is directly set to a fixed value in the decoding process. For a specific decoding process, reference can be made to Figure 2 and Figure 3 and corresponding descriptions of Figure 2 and Figure 3. 1503: Deinterlegate T candidate paths whose metrics are ideal in the L candidate paths, where T is an integer greater than 0 and less than or equal to L.

[0095] A 1403 deinterleaving unit is configured to perform deinterleaving on the T candidate paths whose metrics are ideal on the L candidate paths, where T is an integer greater than 0 and less than or equal to L. To be specific, the 1403 deinterleaving unit can perform deinterleaving on all L candidate paths (when T=L), or it can select a portion of paths for deinterleaving (when T <l) . se lcrc, lpc e um limite superior de taxa alarme falso forem dados, valor t pode ser determinado mediante referência à fórmula (2).1504: Perform a CRC check on the candidate paths.

[0096] A CRC 1404 verification unit can sequentially perform CRC verification on T candidate paths starting from a candidate path whose metric Petition 870250030778, dated 04 / 16 / 2025, pp. 65 / 173 57 / 68 would be ideal. The CRC verification unit can perform CRC verification on each of the T candidate paths to obtain a result: verification is successful or verification fails. Alternatively, after the first candidate path that passes the CRC verification is obtained, the remaining candidate paths are no longer verified. 1505: Use, as decoding output, a block of information in a candidate path that passes the CRC check and whose metric is ideal.

[0097] A 1405 output unit is configured to select, as output for this decoding time, the information block corresponding to the information bit in the candidate path that passes the CRC check and whose metric is ideal. If the 1404 CRC check unit starts the CRC check from the candidate path whose metric is ideal, the first candidate path that passes the CRC check can be used directly as a decoding result, and an information block in the first candidate path is output.

[0098] Step 1501 may also include: obtaining a verification equation. The verification equation can be determined using a CRC polynomial and a merging sequence. Information bits verified using each CRC bit depend on a generator matrix determined by the CRC polynomial, and the merging sequence can determine the positions, after merging, of information bits verified using each CRC bit, so that a merged verification equation is obtained. Petition 870250030778, dated 04 / 16 / 2025, pp. 66 / 173 58 / 68

[0099] Figure 16 shows an example in which two candidate paths are maintained in a decoding process of an SCL decoding algorithm when List=2. Generally, the first several bits are freeze bits and are set to fixed values, for example, 0 or 1. Therefore, the decoding actually starts from the first bit of information. In Figure 16, a PM is calculated using formula (1). A path whose PM is minimum is maintained during each extension, and two candidate paths L1 and L2 indicated by arrows are finally obtained. A PM of path L1 is finally 0.3, and a PM of the other path is finally 0.2. A CRC check is first performed on the path L2 whose PM is minimum (a metric is ideal). If path L2 passes the check, L2 is selected as the decoding output. If path L2 does not pass the check, the check is performed on path L1.If path L1 passes the check, L1 is selected as the decoding output. If neither L1 nor L2 passes the check, path L2, whose PM is smaller (whose metric is ideal), can be selected as a decoding result to output. If neither L1 nor L2 passes the check, it can alternatively be determined that this decoding time fails. In the decoding process, a value of List can be different, for example, List=8, 16, 32, or 64.

[00100] The i-th order bits marked in Figure 16 are a part of CRC bits (special CRC bits) described in this patent application. Two arrows 1601 indicate that a special CRC bit value is determined by an (i-3) order bit (information bit). It can be learned that when a bit of Petition 870250030778, dated 04 / 16 / 2025, pp. 67 / 173 59 / 68 order i is decoded, path extension does not need to be performed, and a value of the bit of order i is determined by a value of the bit of order (i-3) in the path. Therefore, a value of a special CRC bit in path L1 is 0, and a value of a special CRC bit in L2 is 1. A difference between Figure 16 and Figure 3 lies in the fact that the bit of order i corresponds to a frozen bit in Figure 3, and the bit of order i corresponds to a special CRC bit in Figure 15. When the special CRC bit is decoded, the PM in Figure 16 changes relative to the PM in Figure 3. Specifically, in Figure 16, it is assumed that an LLR(i) of the special CRC bit in path L1 and an LLR(i) of the special CRC bit in path 2 are less than 0, and a corresponding value is assumed to be 1 when the LLR(i) is less than 0.In path L1, a decoding result of 0 for bit i is inconsistent with a result corresponding to LLR(i), and based on formula (1), a |LLR(i)| is added to PM, assuming that |LLR(i)| is 0.3. In path L2, a decoding result of 1 for bit i is consistent with the value corresponding to LLR(i), and based on formula (1), PM(i)=PM(i-1)=0.2. If the decoding performed on a previous bit in L1 is incorrect, the special CRC bit i is determined based on a result obtained through the decoding performed on the previous bit in L1, and it may also be incorrect. This increases the probability that the decoding result of bit i is inconsistent with the value corresponding to LLR(i), and a penalty value |LLR(i)| is added to PM(i). In this case, the PM of the path increases, and the probability that the incorrect path will be deleted during decoding increases. Petition 870250030778, dated 04 / 16 / 2025, pp. 68 / 173 60 / 68 modality, a lower PM indicates a better route, and a higher PM indicates a worse route.

[00101] Figure 17(a) shows the comparison between the performance of polar AC in an AWGN channel in a solution of this patent application and the performance of polar AC in an AWGN channel in a conventional solution when List=8 and K=32. Figure 17(b) shows the comparison between the performance of polar AC in an AWGN channel in a solution of this patent application and the performance of polar AC in an AWGN channel in a conventional solution when K=48. In conventional polar AC, all CRC bits are used for a CRC check to perform error correction or error detection. In the solution of this patent application, a portion of CRC bits is interleaved between bits of an information block, all bits of the checked information block are located before the CRC bits, and the portion of CRC bits is used as PC bits for decoding. In Figure 17(a) and Figure 17(b), performance curves represented by solid lines correspond to a CRC length of 27.Eight bits are interleaved and used as PC bits to provide assistance for SCL decoding, and the remaining CRC bits are used to select a path after SCL decoding. Dashed lines correspond to the CRC length 27, and are all used to select a path after SCL decoding. It can be learned that in the solution of this patent application, compared to polarized CA, a performance gain is greater than 0.4 dB when K=32, and a gain is greater than 0.1 dB when K=48.

[00102] An 1800 decoding device shown in Figure 18 can also be configured to execute a method Petition 870250030778, dated 04 / 16 / 2025, pp. 69 / 173 61 / 68 decoding. The 1800 decoding device includes an 1801 memory and an 1802 processor.

[00103] Memory 1801 is configured to store a program.

[00104] The 1802 processor is configured to: execute the program stored in memory and, when the program is executed, execute the decoding method shown in Figure 15. The method includes: obtaining information bit positions and a freeze bit in the bits to be decoded, where the information bits include K bits of an information block and Lcrc CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a CRC bit value for each of the Lpc CRC bits is determined based on a bit value from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and remaining CRC bits (Lcrc-Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and perform a CRC check on the T candidate paths. Petition 870250030778, dated 04 / 16 / 2025, pp. 70 / 173 62 / 68 and use, as a decoding output, a block of information in a candidate path that passes the CRC check and whose path metric is ideal.

[00105] If none of the T candidate paths pass the CRC check, a path whose metric is ideal can be selected as the decoding output, or it can be determined that the decoding fails.

[00106] For content such as an Lpc quantity of special CRC bits, an interleaving sequence, a generation method, and a number of times a CRC check is performed, reference may be made to the encoding method and decoding method modes. The 1801 memory may be a physically independent unit, or it may be integrated into the 1802 processor.

[00107] The decoding device in Figure 18 may also include a receiver (not shown in the figure), configured to receive information regarding the bits to be decoded.

[00108] As shown in Figure 19, this patent application provides another decoding apparatus 1900 that can implement the decoding method in this patent application. The decoding apparatus 1900 includes at least one input end 1901, a signal processor 1902, and at least one output end 1903.

[00109] At least one input end 1901 is configured to receive information regarding bits to be decoded.

[00110] The 1902 signal processor is configured to: obtain information bit positions and a freeze bit. Petition 870250030778, dated 04 / 16 / 2025, pp. 71 / 173 63 / 68 in the bits to be decoded, where the information bits include K bits of an information block and Lcrc CRC bits, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit, and Lpc is an integer greater than 0 and less than Lcrc;Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, where in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value for each CRC bit of the Lpc CRC bits is determined based on a bit value from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and remaining CRC bits (Lcrc-Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and perform a CRC check on the T candidate paths.

[00111] At least one output end 1903 is configured to use, as a decoding output, a block of information in a first candidate path that passes the CRC check.

[00112] For content such as an Lpc quantity of special CRC bits, an interleaving sequence, a generation method, and a number of times a CRC check is performed, reference can be made to the modalities of the method. Petition 870250030778, dated 04 / 16 / 2025, pp. 72 / 173 64 / 68 encoding and decoding method.

[00113] Optionally, the 1902 signal processor can be implemented using hardware, for example, a baseband processor, a processing circuit, an encoder, or an encoding circuit.

[00114] The decoding device in Figure 19 may also include a receiver (not shown in the figure), configured to receive information regarding the bits to be decoded.

[00115] The decoding apparatus in this embodiment of this patent application may be any device with a wireless communications function, for example, an access point, a station, user equipment, or a base station.

[00116] The information block described in the embodiments of this patent application refers to information bits to be transmitted, or may be referred to as an information bit sequence, a to-becoded bit sequence, a data block, data bits, an information bit set, an information bit vector, or similar. Correspondingly, the length of the information block may be called the information block size, and refers to a quantity of bits in an information bit sequence, a quantity of bits to be decoded in a to-becoded bit sequence, a quantity of bits in a data block, a quantity of data bits, or a Petition 870250030778, dated 04 / 16 / 2025, pp. 73-173 65 / 68 quantity of elements in a set of information bits. The coded block described in the embodiments of this patent application may alternatively be referred to as coded bits, a coded bit sequence, or similar.

[00117] The successive cancellation list decoding algorithm SCL described in the embodiments of this patent application includes another decoding algorithm, similar to SCL, in which decoding is performed sequentially and which provides a plurality of candidate paths, or an improved algorithm with respect to the SCL decoding algorithm.

[00118] In actual use, the decoding apparatus or decoding device described in the embodiments of this patent application may be a stand-alone device or it may be an integrated device; and is configured to: encode information to be encoded and then transmit encoded information, or decode received information.

[00119] In the examples described in the embodiments of this patent application, units and processes of methods may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on specific applications and design constraints of the technical solutions. Persons skilled in the art may implement the described functions by using different methods for each specific application.

[00120] In the various embodiments provided in this patent application, it should be understood that the apparatus and method Petition 870250030778, dated 04 / 16 / 2025, pp. 74 / 173 The 66 / 68 disclosed methods can be implemented in other ways. The described device modalities are merely examples. For example, the division of units is merely a logical division of functions and may be another division during actual implementation. For example, a plurality of units and components may be combined or integrated into another system. Some steps in the method may be skipped or may not be performed. Furthermore, couplings or direct couplings or communication connections between units may be implemented using some interfaces, and these interfaces may be implemented in electronic, mechanical or other forms.

[00121] The units described as separate parts may or may not be physically separated, and may be located in one position or may be distributed across a plurality of network units. Furthermore, functional units in the embodiments of this patent application may be integrated into a processing unit, or each of the units may exist physically isolated, or two or more units may be integrated into a unit.

[00122] All or some of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement the embodiments, the embodiments may be implemented wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the procedures or functions according to the embodiments of the present invention Petition 870250030778, dated 04 / 16 / 2025, pp. 75 / 173 67 / 68 are wholly or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable device. Computer instructions may be stored on a computer-readable storage medium, or may be transmitted using a computer-readable storage medium. Computer instructions may be transmitted from one Internet site, computer, server, or data center to another Internet site, computer, server, or data center in a wired mode (e.g., a coaxial cable, a fiber optic cable, or a digital subscriber line (DSL)) or wireless mode (e.g., infrared, radio, or microwave). The computer-readable storage medium may be any usable medium accessible to a computer, or a data storage device, such as a server or data center, integrating one or more usable media.The usable medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape, a USB flash drive, a ROM, or a RAM), an optical medium (for example, a CD or a DVD), a semiconductor medium (for example, a solid-state disk (SSD)), or similar.

[00123] The aforementioned embodiments are intended merely to describe the technical solutions of the present invention, but not to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, persons skilled in the art should understand that they may still make modifications to the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some Petition 870250030778, dated 04 / 16 / 2025, pp. 76 / 173 68 / 68 of its technical resources. Replacements do not cause the corresponding ones to deviate from the modalities of the present. However, these modifications or essence of technical solutions fall within the scope of the invention. Petition 870250030778, dated 04 / 16 / 2025, pp. 77 / 173

Claims

1 / 7 CLAIMS 1. Polar coding method, characterized in that the method comprises: performing cyclic redundancy check coding, CRC, on an information block to obtain a CRC-coded block with a length of B, wherein a CRC length is Lcrc, an information block length is K, and B = K + Lcrc; interleaving the CRC-coded block, wherein Lpc CRC bits in an interleaved CRC-coded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using said CRC bit, and the Lcrc-Lpc CRC bits are located at the end of the interleaved CRC-coded block;and map the interleaved CRC encoded block to polar code information bit positions, set a freeze bit to an agreed fixed value, and perform polar encoding on the polar code information bits and the freeze bit to obtain a polar encoded codeword, wherein polar code information bit positions are positions corresponding to B polarized channels with ideal reliability, a freeze bit position is a position corresponding to one of NB remaining polarized channels, and N is a mother code length of a polar code, wherein Lcrc is 24 and Lpc is 6.

2. Method, according to claim 1, characterized in that the interleaving of the CRC encoded block comprises: interleaving the CRC encoded block using an interleaving sequence π = [π1, π2, ..., πη], and permuting a sequence of CRC encoded bits [b1, b2, ..., bn} into [t^1, bπ2, ..., bπn], where n is an integer greater than 0 and less than or equal to B, and a value of πη represents a bit position sequence number that is of a bit of order n of the interleaved encoded block and that is in the CRC encoded block before the interleaving is performed.

3. Encoding apparatus, characterized in that the apparatus comprises: a cyclic redundancy check (CRC) encoding unit, configured to perform CRC encoding on an information block to obtain a CRC-encoded block with a length of B, wherein a CRC length is Lcrc, an information block length is K, and B = K + Lcrc; an interleaving unit, configured to interleave the CRC-encoded block, wherein Lpc CRC bits in an interleaved CRC-encoded block are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using said CRC bit, and the Lcrc-Lpc CRC bits are located at the end of the interleaved CRC-encoded block;and a polar encoding unit, configured to: map the CRC encoded block obtained after interleaving is performed by the interleaving unit to polar code information bit positions, set a freeze bit to an agreed fixed value, and perform polar encoding on the polar code information bits and Petition 870250030778, dated 04 / 16 / 2025, page 147 / 173 3 / 7 on the freeze bit to obtain a polar encoded codeword, wherein polar code information bit positions are positions corresponding to B polarized channels with ideal reliability, a freeze bit position is a position corresponding to one of NB remaining polarized channels, and N is a mother code length of a polar code, wherein Lcrc is 24 and Lpc is 6.; 4. Apparatus, according to claim 3, characterized in that the interleaving unit interleaves the CRC encoded block by using an interleaving sequence π = [π1, π2, ..., πη], and permutes a sequence of CRC encoded bits [b1, b2, ..., bn] into bπ1, bπ2, ..., bπn, where n is an integer greater than 0 and less than or equal to B, and a value of πn represents a bit position sequence number that is of a bit of order n of the interleaved CRC encoded block and that is in the CRC encoded block before the interleaving is performed.

5. Encoding apparatus, characterized in that the apparatus comprises: a memory, configured to store a set of instructions; and a processor, configured to execute the set of instructions stored in the memory, wherein, when the set of instructions is executed, the method, as defined in claim 1 or 2, is executed.

6. Encoding apparatus, characterized in that the apparatus comprises: at least one input terminal, configured to receive a block of information; Petition 870250030778, dated 04 / 16 / 2025, page 148 / 173 4 / 7 a signal processor, configured to: execute the method, as defined in claim 1 or 2.

7. Polar decoding method, characterized by the fact that the method comprises: obtaining information bit positions and a frozen bit in bits to be decoded, wherein the information bits comprise K bits of an information block and Lcrc cyclic redundancy check bits (CRC), Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit;Sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, wherein in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L;and perform a CRC check on the T candidate paths, and use, as decoding output, a Petition 870250030778, dated 04 / 16 / 2025, p. 149 / 173 5 / 7 block of information on a candidate path that passes the CRC check and whose path metric is ideal, where Lcrc is 24 and Lpc is 6.; 8. Decoding apparatus, characterized in that the apparatus comprises: an acquisition unit, configured to obtain information bit positions and a frozen bit in bits to be decoded, wherein the information bits comprise K bits of an information block and Lcrc cyclic redundancy check bits CRC, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit;A decoding unit, configured to: sequentially decode the bits to be decoded using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, wherein in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a value of each CRC bit of the Lpc CRC bits is determined based on a bit value that is from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; an interleaving unit, configured to deinterleaf T candidate paths whose metrics are ideal in the L candidate paths, where T is an integer greater than 0 and less than or equal to L;and Petition 870250030778, dated 04 / 16 / 2025, page 150 / 173 6 / 7 a CRC verification unit, configured to perform a CRC check on the T candidate paths; and an output unit, configured to use, as decoding output, a block of information in a candidate path that passes the CRC check and whose path metric is ideal, where Lcrc is 24 and Lpc is 6.; 9. Decoding apparatus, characterized in that the decoding apparatus comprises: a memory, configured to store a set of instructions; and a processor, configured to execute the set of instructions stored in the memory, wherein, when the set of instructions is executed, the method, as defined in claim 7, is executed.

10. Decoding apparatus, characterized in that the decoding apparatus comprises: at least one input terminal, configured to receive information relating to bits to be decoded; a signal processor, configured to: obtain information bit positions and a freeze bit in the bits to be decoded, wherein the information bits comprise K bits of an information block and Lcrc cyclic redundancy check bits CRC, Lpc CRC bits are located between bits of the information block, each CRC bit of the Lpc CRC bits is located after all bits checked using the CRC bit;sequentially decode the bits to be decoded (Petition 870250030778, dated 04 / 16 / 2025, p. 151 / 173 7 / 7) using a successive cancellation list (SCL) decoding algorithm, and output L candidate paths whose metrics are ideal, wherein in a decoding process, a frozen bit value in each candidate path is set to an agreed fixed value, a CRC bit value for each Lpc bit is determined based on a bit value from the information block, which is verified using the CRC bit, and which is located before the CRC bit, and the remaining CRC bits (Lcrc - Lpc) are decoded in a decoding mode of the information bits; deinterleave T candidate paths whose metrics are ideal into the L candidate paths, where T is an integer greater than 0 and less than or equal to L; and perform a CRC check on the T candidate paths;and at least one output unit, configured to use, as a decoding output, a block of information in a candidate path that passes the CRC check and whose path metric is ideal, where Lcrc is 24 and Lpc is 6. Petition 870250030778, dated 04 / 16 / 2025, pp. 152 / 173;

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