Methods and apparatus for performing qc-ldpc decoding and encoding for HARQ transmission using a qc-ldpc rate compatible design

Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding codes compatible with quasi-cyclic low-density parity check rate (qc-ldpc), for example, using a parity check matrix comprising first layers according to a high-rate core graph and second layers for harq transmission, wherein the parity check matrix has quasi-line orthogonality or full-line orthogonality within the second layers.An exemplary method for performing low-density parity check (ldpc) decoding includes receiving soft bits associated with an ldpc codeword and performing ldpc decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a raised parity check of a raised ldpc codeword, at least two columns of the parity check matrix correspond to punched variable nodes of the raised ldpc codeword, and the parity check matrix has row orthogonality between each pair of consecutive rows below a row in which at least two punched variable nodes are connected.

Description

1 / 62 Methods and Apparatus for Performing QC-LDPC Decoding and Encoding for HARQ Transmission Using a QC-LDPC Rate Compliant Design CROSS-REFERENCE TO RELATED REQUESTS

[0001] This Patent Application claims priority to U.S. Provisional Application No. 62 / 505,573, filed May 12, 2017, and U.S. Patent Application No. 15 / 975,440, filed May 9, 2018, both assigned to the assignee hereof and hereby expressly incorporated by reference herein in their entirety. TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to methods and apparatus for wireless communications and, more particularly, to line orthogonality in a design compatible with low-density parity check rate (LDPC). INTRODUCTION

[0003] Wireless communication systems are widely implemented to provide various types of communication content, such as voice, data, and so on. These systems can be multiple access systems capable of supporting communication with multiple users sharing the available system resources (e.g., bandwidth and transmission power). Examples of such multiple access systems include LTE (Long Term Evolution) systems, CDMA (Code Division Multiple Access) systems, TDMA (Time Division Multiple Access) systems, FDMA (Frequency Division Multiple Access) systems, and LTE 3GPP (3rd Generation Partnership) systems. Petition 870250040184, dated 05 / 16 / 2025, page 13 / 22 2 / 62 Project), LTE-A (Long Term Evolution Advanced) systems and OFDMA (Orthogonal Frequency Division Multiple Access) systems.

[0004] Generally, a wireless multiple access communication system can simultaneously support communication to multiple wireless nodes. Each node communicates with one or more base stations through transmissions on forward and reverse links. The forward link (or downlink) refers to a communication link from the base stations to the nodes, and a reverse link (or uplink) refers to a communication link from the nodes to the base stations. The communication links can be established through a single-input single-output system, a multiple-input single-output system, or a MIMO (multiple-input multiple-output) system.

[0005] In the modern information age, binary values ​​(e.g., ones and zeros) are used to represent and communicate various types of information, such as video, audio, statistical information, etc. Unfortunately, during the storage, transmission, and / or processing of binary data, errors can be unintentionally introduced; for example, a one can be changed to a zero or vice versa.

[0006] Generally, in the case of data transmission, a receiver observes each received bit in the presence of noise or distortion, and only an indication of the bit's value is obtained. Under these circumstances, the observed values ​​are interpreted as a soft bit source. A soft bit indicates a preferred estimate of the bit's value (e.g., one or zero) along with some indication of the reliability of that estimate. Although the number of errors may be relatively low, even a small number of Petition 870210036966, dated 04 / 23 / 2021, page 6 / 105 3 / 62 errors or distortion levels can render the data unusable or, in the case of transmission errors, may require retransmission of the data.

[0007] To provide a mechanism for checking for errors and, in some cases, correcting errors, binary data can be encoded to introduce carefully designed redundancy. Encoding a data unit produces what is generally called a codeword. Due to its redundancy, a codeword usually includes more bits than the input data unit from which the codeword was produced.

[0008] Redundant bits are added by an encoder to the transmitted bit stream to create a codeword. When signals resulting from the transmitted codewords are received or processed, the redundant information included in the codeword as observed in the signal can be used to identify and / or correct errors or remove distortions from the received signal in order to recover the original data unit. This error checking and / or correction can be implemented as part of a decoding process. In the absence of errors, or in the case of correctable errors or distortion, decoding can be used to recover the source data being processed, the original data unit that was encoded. In the case of unrecoverable errors, the decoding process may produce some indication that the original data cannot be fully recovered.Such indications of decoding failure can be used to initiate data retransmission.

[0009] With the increased use of fiber optic lines Petition 870210036966, dated 04 / 23 / 2021, page 7 / 105 4 / 62 optical for data communication and the increase in the rate at which data can be read and stored on data storage devices (e.g., disk drives, tapes, etc.), there is a growing need not only for efficient use of data storage and transmission capacity, but also for the ability to encode and decode data at high speed rates.

[0010] Although encoding efficiency and high data rates are important, for an encoding and / or decoding system to be practical for use in a wide range of devices (e.g., consumer devices), it is important that the encoders and / or decoders be able to be implemented at a reasonable cost.

[0011] Communication systems often need to operate at several different rates. One way to keep the implementation as simple as possible and provide encoding and decoding at different rates is to use adjustable low-density parity check (LDPC) codes. In particular, one can generate higher-rate LDPC codes by punching lower-rate codes.

[0012] These multiple access technologies have been adopted in various telecommunications standards to provide a common protocol that allows different wireless devices to communicate at the municipal, national, regional, and even global levels. An example of an emerging telecommunications standard is New Radio (NR). NR is a set of improvements to the LTE mobile standard (e.g., 5G radio access) promulgated by the 3GPP (Third Generation Partnership Project). NR was designed to offer better support for Petition 870210036966, dated 04 / 23 / 2021, page 8 / 105 5 / 62 Mobile broadband Internet access, improving spectral efficiency, reducing costs, enhancing services, making use of new spectrum and better integrating with other open standards using OFDMA with a cyclic prefix (CP) on the downlink (DL) and uplink (UL), as well as supporting beamforming, multiple-input multiple-output (MIMO) antenna technology and carrier aggregation.

[0013] As the demand for mobile broadband access continues to increase, there is a need for further improvements in NR technology. Preferably, these improvements should be applicable to other multiple access technologies and to the telecommunications standards that employ these technologies. One area for improvement is the encoding / decoding area, applicable to NR. For example, techniques for high-performance LDPC codes for NR are desirable. BRIEF SUMMARY

[0014] The systems, methods, and devices of this disclosure have various aspects, none of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure, as expressed by the following claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled Detailed Description, we will understand how the features of this disclosure provide advantages that include enhanced communications between access points and stations on a wireless network.

[0015] Certain aspects of this disclosure provide a method for performing low-density parity-checking (LDPC) decoding. The method Petition 870210036966, dated 04 / 23 / 2021, page 9 / 105 6 / 62 generally involves receiving soft bits associated with an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity check matrix correspond to punched variable nodes of the raised LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which at least two punched variable nodes are connected.

[0016] Certain aspects of the present disclosure provide an apparatus for low-density parity-check decoding (LDPC). The apparatus generally includes a processor configured to cause the apparatus to receive soft bits associated with an LDPC codeword and perform LDPC decoding of the soft bits using a parity-check matrix, wherein each row of the parity-check matrix corresponds to a raised parity check of layered raised LDPC code, at least two columns of the parity-check matrix correspond to the punched variable nodes of the raised LDPC code, and the parity-check matrix has row orthogonality between each pair of consecutive rows that are below a row on which at least two punched variable nodes are connected. The device also generally includes a memory coupled to the processor.

[0017] Certain aspects of the present disclosure Petition 870210036966, dated 04 / 23 / 2021, p. 10 / 105 7 / 62 provides an apparatus for low-density parity-check decoding (LDPC). The apparatus generally includes means for receiving soft bits from an LDPC codeword and means for performing LDPC decoding of the soft bits using a parity-check matrix, wherein each row of the parity-check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity-check matrix correspond to the punched variable nodes of the raised LDPC code, and the parity-check matrix has row orthogonality between each pair of consecutive rows that are below a row to which at least two punched variable nodes are connected.

[0018] Certain aspects of the present disclosure provide a computer-readable means for performing low-density parity-check (LDPC) decoding. The computer-readable means generally includes instructions that, when executed by at least one processor, cause at least one processor to receive soft bits associated with an LDPC codeword and perform LDPC decoding of the soft bits using a parity-check matrix, wherein each row of the parity-check matrix corresponds to a raised parity check of a raised LDPC codeword, at least two columns of the parity-check matrix correspond to punched variable nodes of the raised LDPC codeword, and the parity-check matrix has row orthogonality between each pair of rows below a row to which at least two punched variable nodes correspond. Petition 870210036966, dated 04 / 23 / 2021, p. 11 / 105 8 out of 62 are connected.

[0019] Certain aspects of the present disclosure provide a method for performing low-density parity-check (LDPC) coding. The method generally involves obtaining information bits from a codeword and performing encoding of the information bits to compute parity bits of an LDPC codeword according to a parity-check matrix, wherein each row of the parity-check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity-check matrix correspond to punched variable nodes of the raised LDPC code, and the parity-check matrix has row orthogonality between each pair of consecutive rows that are below a row in which at least two punched variable nodes are both connected.

[0020] Certain aspects of the present disclosure provide an apparatus for performing low-density parity-checking (LDPC) coding. The apparatus generally includes a processor configured to cause the apparatus to obtain information bits from a codeword and perform encoding of the information bits to compute parity bits of an LDPC codeword according to a parity-checking matrix, wherein each row of the parity-checking matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity-checking matrix correspond to variable punctured nodes of the raised LDPC code, and the parity-checking matrix has row orthogonality between each pair of rows. Petition 870210036966, dated 04 / 23 / 2021, p. 12 / 105 9 / 62 consecutive rows below a line in which at least two variable punched nodes are connected. The device also usually includes a memory coupled to the processor.

[0021] Certain aspects of the present disclosure provide an apparatus for low-density parity-check (LDPC) decoding. The apparatus generally includes means for obtaining information bits from a codeword and means for performing encoding of the information bits to compute parity bits of an LDPC codeword according to a parity-check matrix, wherein each row of the parity-check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity-check matrix correspond to the punched variable nodes of the raised LDPC code, and the parity-check matrix has row orthogonality between each pair of consecutive rows that are below a row on which at least two punched variable nodes are connected.

[0022] Certain aspects of the present disclosure provide a computer-readable means for performing low-density parity-check (LDPC) decoding. The computer-readable means generally includes instructions that, when executed by at least one processor, cause at least one processor to obtain information bits from a codeword and perform encoding of the information bits to compute parity bits of an LDPC codeword according to a parity-check matrix, wherein each row of the matrix of Petition 870210036966, dated 04 / 23 / 2021, page 13 / 105 10 / 62 parity check corresponds to a parity check lifted from a lifted LDPC code, at least two columns of the parity check matrix correspond to punched variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows below a row to which at least two punched variable nodes are connected.

[0023] Other aspects, features, and embodiments of the present invention will become apparent to those skilled in the art after reviewing the following description of specific exemplary embodiments of the present invention in conjunction with the accompanying figures. Although the features of the present invention may be discussed in relation to certain embodiments and figures below, all embodiments of the present invention may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more of these features may also be used in accordance with the various embodiments of the invention discussed herein. Similarly, although exemplary embodiments may be discussed below as device, system, or method embodiments, it should be understood that such exemplary embodiments may be implemented in various devices, systems, and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order that the manner in which the above-mentioned features of this disclosure may be understood in detail, a more particular description, Petition 870210036966, dated 04 / 23 / 2021, page 14 / 105 11 / 62, briefly summarized above, can be obtained by reference to aspects, some of which are illustrated in the accompanying drawings. The accompanying drawings illustrate only certain typical aspects of this disclosure, however, and should not, therefore, be considered limiting of its scope, as the description may admit other equally effective aspects.

[0025] FIG. 1 illustrates an example of a multi-access wireless communication system, in accordance with certain aspects of the present disclosure.

[0026] FIG. 2 illustrates a block diagram of a base station and a wireless node, in accordance with certain aspects of the present disclosure.

[0027] FIG. 3 illustrates various components that can be used in a wireless device, according to certain aspects of the present disclosure.

[0028] FIGS. 4A-4B show graphical and matrix representations of an exemplary low-density parity checking (LDPC) code, in accordance with certain aspects of the present disclosure.

[0029] FIG. 5 graphically illustrates the survey of the LDPC code from FIG. 4A, according to certain aspects of this disclosure.

[0030] FIG. 6 is an integer representation of a matrix for a quasi-cyclic IEEE 802.11 LDPC code.

[0031] FIG. 7 is a simplified block diagram illustrating an encoder, in accordance with certain aspects of the present disclosure.

[0032] FIG. 8 is a simplified block diagram illustrating a decoder, in accordance with certain aspects of the present disclosure. Petition 870210036966, dated 04 / 23 / 2021, p. 15 / 105 12 / 62

[0033] FIG. 9 illustrates a high-level block diagram of a generic layered LDPC decoder, in accordance with certain aspects of the present disclosure.

[0034] FIG. 10 illustrates an example of this process for calculating / updating bit LLRs and posterior LLRs in a parity check matrix, in accordance with certain aspects of the present disclosure.

[0035] FIGS. 11A and 11B illustrate an example of a layered decoder pipeline processing timeline, in accordance with certain aspects of the present disclosure.

[0036] FIGS. 12 and 12A to 12H illustrate a parity checking matrix with quasi-line orthogonality, in accordance with certain aspects of the present disclosure.

[0037] FIGS. 13 and 13A to 13H illustrate a parity check matrix with full-line orthogonality, in accordance with certain aspects of the present disclosure.

[0038] FIG. 14 is a flow diagram illustrating an example of operations for decoding low-density parity check (LDPC) codes, in accordance with certain aspects of this disclosure.

[0039] FIG. 15 is a flow diagram that illustrates an example of operations for performing low-density parity check (LDPC) coding, in accordance with certain aspects of this disclosure.

[0040] To facilitate understanding, identical reference numbers have been used, whenever possible, to designate identical elements common to the figures. It is contemplated that the elements disclosed in one embodiment may be used beneficially in other embodiments. Petition 870210036966, dated 04 / 23 / 2021, page 16 / 105 13 / 62 without specific recitation. DETAILED DESCRIPTION

[0041] The aspects of this disclosure provide apparatus, methods, processing systems and computer program products for encoding for new radio (NR) (new radio access technology). New radio (NR) may refer to radios configured to operate in accordance with a new air interface or fixed transport layer. NR can include enhanced mobile broadband (eMBB) techniques targeting a wideband communications system (e.g., 80 MHz and wider), millimeter wave (mmW) techniques targeting high carrier frequency communications systems (e.g., 27 GHz and higher), massive machine-type communication (mMTC) techniques targeting backward-compatible machine-type communication (MTC) systems, and mission-critical techniques targeting ultra-reliable low-latency communications (URLLC). For these general topics, different techniques are considered, such as coding techniques, including low-density parity-check coding (LDPC) and polar coding. An NR cell can refer to a cell operating under the new air interface or a fixed transport layer. An NR B node (e.g., a 5G B node) can correspond to one or more transmit-receive points (TRPs).

[0042] Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity-checked (LDPC) coded transmissions and, more particularly, for decoding LDPC coded transmissions using Petition 870210036966, dated 04 / 23 / 2021, page 17 / 105 14 / 62 is a parity-checking matrix with a large number of orthogonal rows of paired solid lines.

[0043] Several aspects of the disclosure are described in more detail hereafter with reference to the accompanying drawings. This disclosure can, however, be incorporated in many different ways and should not be interpreted as limited to any specific structure or function presented throughout this disclosure. Instead, these aspects are provided so that this disclosure is thorough and complete and fully conveys the scope of the disclosure to those skilled in the art. Based on the teachings of this document, a person skilled in the art should understand that the scope of the disclosure is intended to encompass any aspect of the disclosure disclosed in this document, implemented independently or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein.Furthermore, the scope of the disclosure is intended to cover such apparatus or method, practiced using another structure, functionality, or structure and functionality in addition to or beyond the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be incorporated by one or more elements of a claim. The word exemplary is used herein to mean serving as an example, instance, or illustration. Any aspect described herein as exemplary should not necessarily be interpreted as preferred or advantageous in relation to other aspects.

[0044] Although particular aspects are Petition 870210036966, dated 04 / 23 / 2021, p. 18 / 105 15 / 62 described in this document, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not limited to specific benefits, uses, or objectives. Instead, the aspects of the disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the figures and description of the preferred aspects that follow. The detailed description and drawings are merely illustrative of the disclosure and not limiting, the scope of the disclosure being defined by the appended claims and their equivalents.

[0045] The techniques described in this document can be used for various wireless communication networks, such as LTE (Long Term Evolution) networks, CDMA (Code Division Multiple Access) networks, TDMA (Time Division Multiple Access) networks, FDMA (Frequency Division Multiple Access) networks, OFDMA (Orthogonal FDMA) networks, SC-FDMA (Single Carrier FDMA) networks, etc. The terms networks and systems are often used interchangeably. A CDMA network may implement a radio technology such as UTRA (Universal Terrestrial Radio). Access), CDMA2000, etc. UTRA includes W-CDMA (wideband CDMA) and LCR (low chip rate). CDMA2000 covers the IS-2000, IS-95, and IS-856 standards. A TDMA network can implement a radio technology such as GSM (Global System for Mobile Communications). An OFDMA network can implement a radio technology such as NR (e.g., 5G RA), E-UTRA (evolved UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Petition 870210036966, dated 04 / 23 / 2021, page 19 / 105 16 / 62 Flash-OFDM®, etc. UTRA, E-UTRA, and GSM are part of UMTS (Universal Mobile Telecommunication System). LTE (Long Term Evolution) is a version of UMTS that uses E-UTRA. UTRA, EUTRA, GSM, UMTS, and LTE are described in documents from an organization called 3GPP (3rd Generation Partnership Project). CDMA2000 is described in documents from an organization called 3GPP2 (3rd Generation Partnership Project 2). NR is an emerging wireless communication technology under development in conjunction with the 5GTF (5G Technology Forum). These communication networks are merely listed as examples of networks in which the techniques described in this disclosure can be applied; however, this disclosure is not limited to the communication network described above.

[0046] Single-carrier frequency division multiple access (SC-FDMA) is a transmission technique that uses single-carrier modulation on the transmitter side and frequency-domain equalization on the receiver side. SC-FDMA has similar performance and essentially the same overall complexity as the OFDMA system. However, the SC-FDMA signal has a lower peak-to-average power ratio (PAPR) due to its inherent single-carrier structure. SC-FDMA has attracted much attention, especially in uplink (UL) communications, where the lower PAPR greatly benefits the wireless node in terms of transmission power efficiency.

[0047] An access point (AP) may comprise, be implemented as, or be known as Node B, Radio Network Controller (RNC), eNode B (eNB), Node B (e.g., 5G Node B), Transmit Receive Point (TRP), Controller of Petition 870210036966, dated 04 / 23 / 2021, page 20 / 105 17 / 62 Base Station (BSC), Base Transceiver Station (BTS), Base Station (BS), Transceiver Function (TF), Radio Router, Radio Transceiver, Basic Service Set (BSS), Extended Service Set (ESS), Radio Base Station (RBS) or some other terminology.

[0048] An access terminal (AT) may comprise, be implemented as, or be known as an access terminal, a subscriber station, a subscriber unit, a mobile station, a remote station, a remote terminal, a user terminal, a user agent, a user device, user equipment (UE), a user station, a wireless node, or some other terminology. In some implementations, an access terminal may comprise a mobile phone, a smartphone, a cordless phone, a SIP (Session Initiation Protocol) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a tablet, a netbook, a smartbook, an ultrabook, a wirelessly capable portable device, a Station (STA), or some other suitable processing device connected to a wireless modem.Therefore, one or more aspects taught here can be incorporated into a telephone (e.g., a cell phone, a smartphone), a computer (e.g., a desktop), a portable communication device, a portable computing device (e.g., a laptop, a personal data assistant, a tablet, a netbook, a smartbook, an ultrabook), medical devices or equipment, biometric sensors / devices, an entertainment device (e.g., a music device or...). Petition 870210036966, dated 04 / 23 / 2021, page 21 / 105 18 / 62 video or satellite radio), a vehicle component or sensor, smart meters / sensors, industrial manufacturing equipment, a global positioning system device, or any other suitable device configured to communicate wirelessly or via a wired connection. In some respects, the node is a wireless node. A wireless node can provide, for example, connectivity to or from a network (e.g., a wide area network such as the Internet or a cellular network) via a wired or wireless communication link.

[0049] Although aspects may be described in this document using terminology commonly associated with 3G and / or 4G wireless technologies, aspects of this disclosure may be applied to other generation-based communication systems, such as 5G and later, including NR technologies. An example of a wireless communication system.

[0050] FIG. 1 illustrates an example of a communications network 100 in which aspects of the present disclosure can be realized. As illustrated, a node B 102 (for example, a TRP or 5G node B) may include several antenna groups, one group including antennas 104 and 106, another group including antennas 108 and 110, and an additional group including antennas 112 and 114. In FIG. 1, only two antennas are shown for each antenna group; however, more or fewer antennas may be used for each antenna group. Wireless node 116 may be in communication with antennas 112 and 114, where antennas 112 and 114 transmit information to wireless node 116 via the forward link 120 and receive information from wireless node 116 via the reverse link 118. Wireless node 122 may be in communication with Petition 870210036966, dated 04 / 23 / 2021, page 22 / 105 19 / 62 antennas 106 and 108, where antennas 106 and 108 transmit information to wireless node 122 via the forward link 126 and receive information from wireless node 122 via the reverse link 124. Node B 102 may also be in communication with other wireless nodes, which may be, for example, Internet of Things (IoT) devices. IoT device 136 may be communicating with one or more antennas of Node B 102, where the antennas transmit information to IoT device 136 via the forward link 140 and receive information from IoT device 136 via the reverse link 138. IoT device 142 may be communicating with one or more other antennas of Node B 102, where the antennas transmit information to IoT device 142 via the forward link 146 and receive information from IoT device 142 via the reverse link 144. In a Frequency Division Duplex (FDD) system, the communication links 118, 120, 124, 126, 138, 140, 144, and 146 may use different frequencies for communication. For example, the forward link 120 may use a different frequency than the reverse link 118, and the forward link 140 may use a different frequency than the reverse link 138.

[0051] Each group of antennas and / or the area in which they are designed to communicate are often referred to as a sector of Node B. In one aspect of the present disclosure, each group of antennas may be designed to communicate with wireless nodes in a sector of the areas covered by Node B 102.

[0052] Wireless node 130 may be in communication with node B 102, where antennas of node B 102 transmit information to wireless node 130 via direct link 132 Petition 870210036966, dated 04 / 23 / 2021, page 23 / 105 20 / 62 and receive information from wireless node 130 via reverse link 134.

[0053] In communication via direct links 120 and 126, the BS 102 transmitting antennas can use beamforming to improve the signal-to-noise ratio of the direct links to the different wireless nodes 116, 122, 136, and 142. Furthermore, a Node B using beamforming to transmit to wireless nodes randomly scattered throughout its coverage causes less interference to wireless nodes in neighboring cells than a Node B transmitting through a single antenna to all its wireless nodes.

[0054] Although aspects of the examples described herein may be associated with LTE technologies, aspects of this disclosure may be applicable to other wireless communication systems, such as NR. NR may utilize orthogonal frequency-division multiplexing (OFDM) with a CP on the uplink and downlink and include support for half-duplex operation using time-division duplexing (TDD). A single-component carrier bandwidth of 100 MHz may be supported. NR resource blocks may encompass 12 subcarriers with a subcarrier bandwidth of 75 kHz for a duration of 0.1 ms. Each radio frame may consist of 2 half-frames, each half-frame composed of 5 subframes, with a length of 10 ms. Consequently, each subframe may have a length of 1 ms.Each subframe can indicate a link direction (i.e., downlink (DL) or uplink (UL)) for data transmission, and the link direction for each subframe can be dynamically switched. Each subframe can include DL / UL data as well as DL / UL control data. Beamforming. Petition 870210036966, dated 04 / 23 / 2021, page 24 / 105 21 / 62 can be supported and the beam direction can be dynamically configured. MIMO transmissions with pre-coding can also be supported. MIMO configurations in DL can support up to 8 transmit antennas with multi-layer DL transmissions with up to 8 streams. Multi-layer transmissions with up to 2 streams per UE can be supported. Multi-cell aggregation can be supported with up to 8 service cells. Alternatively, NR can support a different air interface, other than an OFDM-based air interface. NR networks can include entities such as central units or distributed units.

[0055] FIG. 2 illustrates a block diagram of one aspect of a transmitter system 210 (e.g., also known as a base station) and a receiver system 250 (e.g., also known as a wireless node) in a multiple-input multiple-output (MIMO) system 200, in which aspects of the present disclosure can be practiced. Each of the systems 210 and 250 has capabilities for transmitting and receiving. Whether the system 210 or the system 250 is transmitting, receiving, or transmitting and receiving simultaneously depends on the application. In the transmitter system 210, traffic data for a number of data streams are provided from a data source 212 to a transmission (TX) data processor 214.

[0056] In one aspect of this disclosure, each data stream can be transmitted through a respective transmitting antenna. The TX 214 data processor formats, encodes, and interleaves the traffic data for each data stream based on a specific encoding scheme (e.g., low-density parity check (LDPC)). Petition 870210036966, dated 04 / 23 / 2021, page 25 / 105 22 / 62 was selected for this data stream to provide encoded data.

[0057] The encoded data for each data stream can be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and can be used in the receiving system to estimate the channel response. The multiplexed pilot and encoded data for each data stream are modulated (e.g., symbol-mapped) based on a specific modulation scheme (e.g., BPSK, QSPK, M-PSK, or M-QAM) selected for that data stream to provide modulation symbols. The data rate, encoding, and modulation for each data stream can be determined by instructions executed by the processor 230. The memory 232 can store data and software / firmware for the transmitter system 210.

[0058] The modulation symbols for all data streams are then provided to a TX MIMO 220 processor, which can further process the modulation symbols (e.g., for OFDM). The TX MIMO 220 processor then provides Nt modulation symbol streams (e.g., where Nt is a positive integer) to Nt transmitters (TMTR) 222a to 222t. In certain aspects of the present disclosure, the TX MIMO 220 processor applies beamforming weights to the data stream symbols and to the antenna from which the symbol is being transmitted.

[0059] Each 222 transmitter receives and processes a respective symbol stream to provide one or more analog signals, and otherwise (e.g., amplify, filter, and convert) the analog signals to provide a Petition 870210036966, dated 04 / 23 / 2021, page 26 / 105 23 / 62 modulated signal suitable for transmission via the MIMO channel. The modulated signals from transmitters 222a to 222t are then transmitted from antennas 224a to 224t, respectively.

[0060] In the receiver system 250, the transmitted modulated signals can be received by the Nr antennas (for example, where Nr is a positive integer) 252a a 252r and the signal received from each antenna 252 can be provided to a respective receiver (RCVR) 254a to 254r. Each receiver 254 can condition (e.g., filter, amplify, and down-convert) a respective received signal, digitize the conditioned signal to provide samples, and further process the samples to provide a corresponding received symbol stream.

[0061] A receiving data processor (RX) 260 receives and processes the Nr symbol streams received from Nr receivers 254 based on a specific receiver processing technique to provide Nt detected symbol streams. The RX 260 data processor then demodulates, deinterleaves, and decodes each detected symbol stream to recover the traffic data for the data stream. The processing by the RX 260 data processor may be complementary to that performed by the TX MIMO processor 220 and the TX 214 data processor in the transmitter system 210.

[0062] A processor 270 periodically determines which pre-encoding matrix to use. Processor 270 formulates a reverse link message comprising a matrix index portion and a classification value portion. Memory 272 can store data and software / firmware for the receiving system 250. The reverse link message can Petition 870210036966, dated 04 / 23 / 2021, page 27 / 105 24 / 62 understand various types of information about the communication link and / or the received data stream. The reverse link message is then processed by a data processor TX 238, which also receives traffic data for a number of data streams from a data source 236, modulated by a modulator 280, conditioned by transmitters (TMTR) 254a to 254r, and transmitted back to the transmitter system 210.

[0063] In the transmitter system 210, the modulated signals from the receiver system 250 are received by antennas 224, conditioned by receivers (RCVR) 222, demodulated by a demodulator 240, and processed by a data processor RX 242 to extract the reverse link message transmitted by the receiver system 250. The processor 230 then determines which pre-coding matrix to use to determine the beamforming weights and then processes the extracted message.

[0064] Any of the 270 processors, RX 260 data processor, other processors / elements, or a combination thereof of the receiver system 250 and / or any of the 230 processors, RX 242 data processor, other processors / elements, or a combination thereof of the transmitter system 210 may be configured to perform the procedures for low-density parity check (LDPC) decoding in accordance with certain aspects of this disclosure discussed below with reference to FIG. 14. In one aspect, at least one of the 270 processors and RX 260 data processor may be configured to execute memory-stored algorithms 272 to perform the LDPC decoding described herein. In another aspect, at least one of the 230 processors and Petition 870210036966, dated 04 / 23 / 2021, page 28 / 105 The 25 / 62 RX 242 data processor can be configured to execute algorithms stored in memory 232 to perform the LDPC decoding described herein.

[0065] Any of the 270 processors, TX 238 data processor, other processors / elements, or a combination thereof of the receiver system 250 and / or any of the 230 processors, TX MIMO 220 processor, TX 214 data processor, other processors / elements, or a combination thereof of the transmitter system 210 may be configured to perform the procedures for low-density parity check (LDPC) coding in accordance with certain aspects of this disclosure discussed below with reference to FIG. 15. In one aspect, at least one of the 270 processors and TX 238 data processor may be configured to execute memory-stored algorithms 272 to perform the LDPC coding described herein. In another aspect, at least one of the 230 processors, TX MIMO 220 processor, and TX 214 data processor may be configured to execute memory-stored algorithms 232 to perform the LDPC coding described herein.

[0066] FIG. 3 illustrates various components that can be used in a wireless device 302 that can be employed within the wireless communication system 100 illustrated in FIG. 1. The wireless device 302 is an example of a device that can be configured to implement the various methods described in this document. The wireless device 302 can be a B node 102 (e.g., a TRP) or any of the wireless nodes (e.g., wireless nodes 116, 122, 130 or IoT device 136 or 142). For example, the Petition 870210036966, dated 04 / 23 / 2021, p. 29 / 105 The 26 / 62 wireless device 302 can be configured to perform operations 1400 and 1500 described in FIGS. 14 and 15, as well as other operations described in this document.

[0067] Wireless device 302 may include a processor 304 that controls the operation of wireless device 302. Processor 304 may also be referred to as a central processing unit (CPU). Memory 306, which may include read-only memory (ROM) and random access memory (RAM), provides instructions and data to processor 304. A portion of memory 306 may also include non-volatile random access memory (NVRAM). Processor 304 typically performs logical and arithmetic operations based on program instructions stored in memory 306. The instructions in memory 306 may be executable to implement the methods described herein, for example, to enable a UE to perform LDPC decoding and / or LDPC encoding. Some non-limiting examples of processor 304 may include a Snapdragon processor, application-specific integrated circuits (ASICs), programmable logic, etc.

[0068] The wireless device 302 may also include an enclosure 308 which may contain a transmitter 310 and a receiver 312 to enable the transmission and reception of data between the wireless device 302 and a remote location. The transmitter 310 and the receiver 312 may be combined into a transceiver 314. A single or plurality of transmitting antennas 316 may be connected to the enclosure 308 and electrically coupled to the transceiver 314. The wireless device 302 may also include (not shown) multiple transmitters, multiple receivers and multiple Petition 870210036966, dated 04 / 23 / 2021, page 30 / 105 27 / 62 transceivers. The 302 wireless device may also include wireless battery charging equipment.

[0069] The wireless device 302 may also include a signal detector 318 that can be used in an effort to detect and quantify the level of signals received by the transceiver 314. The signal detector 318 can detect signals such as total energy, energy per subcarrier per symbol, power spectral density, and other signals. The wireless device 302 may also include a digital signal processor (DSP) 320 for use in signal processing.

[0070] In addition, the wireless device may also include an encoder 322 for use in encoding signals for transmission and a decoder 324 for use in decoding received signals. In certain respects, the encoder 322 may perform encoding in accordance with certain aspects presented here (for example, implementing operations 1500 illustrated in FIG. 15). In certain respects, the decoder 324 may perform decoding in accordance with certain aspects presented here (for example, implementing operations 1400 illustrated in FIG. 14).

[0071] The various components of the wireless device 302 can be coupled together by a bus system 326, which may include a power bus, a control signal bus, and a status signal bus, in addition to a data bus. The processor 304 can be configured to access instructions stored in memory 306 to perform LDPC decoding and / or LDPC encoding, according to aspects of the present Petition 870210036966, dated 04 / 23 / 2021, page 31 / 105 28 / 62 disclosure discussed below. EXAMPLE OF ERROR CORRECTION CODING

[0072] Many communication systems use error-correcting codes. Specifically, error-correcting codes compensate for the inherent unreliability of information transfer in these systems by introducing redundancy into the data stream. Low-density parity-checking (LDPC) codes are a specific type of error-correcting code that uses an iterative coding system. In particular, Gallager codes are an early example of regular LDPC codes. LDPC codes are linear block codes in which most elements of their parity-checking matrix H are set to 'O'.

[0073] LDPC codes can be represented by bipartite graphs (usually called Tanner graphs), where a set of variable nodes corresponds to bits of a codeword (e.g., information bits or systematic bits) and a set of check nodes corresponds to a set of parity check constraints that define the code. The edges in the graph connect variable nodes to check nodes. Thus, the nodes in the graph are separated into two distinct sets, variable nodes and check nodes, with edges connecting the two different types of nodes.

[0074] A surveyed graph is created by copying a bipartite base graph (G), which may also be known as a protograph, a number of times, Z. A variable node and a check node can be considered neighbors if they are connected by an edge (i.e., the line that Petition 870210036966, dated 04 / 23 / 2021, page 32 / 105 29 / 62 connects the variable node and the check node) in the graph. Furthermore, for each edge (e) of the bipartite basis graph (G), a permutation is applied to the Z copies of edge (e) to interconnect the Z copies of G. A bit sequence having an individual association with the variable node sequence is a valid codeword if, and only if, for each check node, the bits associated with all neighboring variable nodes sum to zero modulo two (i.e., include an even number of 1's). The resulting LDPC code can be quasi-cyclic (CQ) if the permutations used are cyclic.

[0075] FIGS. 4A-4B show graphical and matrix representations of an exemplary LDPC code, in accordance with certain aspects of the present disclosure. For example, FIG. 4A shows a bipartite graph 400 representing an exemplary LDPC code. The bipartite graph 400 includes a set of 5 variable nodes 410 (represented by circles) connected to 4 check nodes 420 (represented by squares). The edges 430 in the graph 400 connect the variable nodes 410 to the check nodes 420 (represented by the lines connecting the variable nodes 410 to the check nodes 420). This graph consists of |V| = 5 variable nodes and |C| = 4 check nodes, connected by |E| = 12 edges.

[0076] The bipartite graph can be represented by a simplified adjacency matrix, which can also be known as a parity check matrix. FIG. 4B shows a 450 matrix representation of the 400 bipartite graph. The 450 matrix representation includes a parity check matrix H and a codeword vector x, where xi-xs represent bits of the codeword x. Petition 870210036966, dated 04 / 23 / 2021, p. 33 / 105 30 / 62 The parity check matrix H is used to determine if a received signal has been decoded normally. The parity check matrix H has rows C corresponding to j check nodes and columns V corresponding to i variable nodes (i.e., a demodulated symbol), where the rows represent the equations and the columns represent the bits of the codeword. In FIG. 4B, the matrix H has 4 rows and 5 columns corresponding to 4 check nodes and 5 variable nodes respectively. If a j-th check node is connected to an i-th variable node by an edge, i.e., the two nodes are neighbors, there will be a 1 in the element in the i-th column and j-th row of the parity check matrix H. That is, the intersection of an i-th row and a j-th column contains a 1 where an edge joins the corresponding vertices and a 0 where there are no edges joining the corresponding vertices.The codeword vector x represents a valid codeword if, and only if, Hx = 0 (for example, if, for each constraint node, the bits neighboring the constraint (through their association with variable nodes) sum to zero modulo two, that is, they comprise an even number of units). Thus, if the codeword is received correctly, Hx = 0 (mod 2). When the product of a received encoded signal and the parity check matrix H becomes '0', this means that no error occurred. The parity check matrix is ​​a binary matrix of row C by column V. The rows represent the equations and the columns represent the digits in the codeword.

[0077] The number of demodulated symbols or variable nodes is the length of the LDPC code. The number of Petition 870210036966, dated 04 / 23 / 2021, page 34 / 105 31 / 62 non-zero elements in a row is defined as the row weight dc. The number of non-zero elements in a column is defined as the column weight dv.

[0078] The degree of a node refers to the number of edges connected to that node. This characteristic is illustrated in the matrix H shown in FIG. 4B, where the number of edges incident to a variable node 410 is equal to the number of 1's in the corresponding column and is called the degree of the variable node d(v). Similarly, the number of edges connected to a check node 420 is equal to the number of edges in a corresponding row and is called the degree of the check node d(c).

[0079] A regular graph or code is one for which all variable nodes have the same degree, j, and all constraint nodes have the same degree, k. In this case, the code can be referred to as a regular (j, k) code. On the other hand, an irregular code has constraint nodes and / or variable nodes of different degrees. For example, some variable nodes may be of degree 4, some of degree 3, and still others of degree 2.

[0080] Lifting enables LDPC codes to be implemented using parallel encoding and / or decoding implementations, in addition to reducing the complexity normally associated with large LDPC codes. Lifting helps enable efficient parallelization of LDPC decoders while maintaining a relatively compact description. More specifically, lifting is a technique for generating a relatively large LDPC code from multiple copies of a smaller basecode. For example, a lifted LDPC code can be generated by producing Z parallel copies of a basegraph (by Petition 870210036966, dated 04 / 23 / 2021, p. 35 / 105 32 / 62 example, protographic) and then interconnecting the parallel copies through permutations of clustered edges from each copy of the base graph. The base graph defines the (macro) structure of the code and consists of a number (K) of information bit columns and a number (N) of code bit columns. Raising the base graph a number (Z) results in a final information block length of KZ. Some information bits can be reduced (set to 0) to obtain information block lengths less than KZ.

[0081] Thus, a larger graph can be obtained by a copy and permute operation, in which multiple copies of the base graph are made and connected to form a single raised graph. For the multiple copies, as edges that are a set of copies of a single base edge, are permuted and connected to form a connected graph Z times larger than the base graph.

[0082] FIG. 5 graphically illustrates the effect of making three copies of the graph in FIG. 4A. Three copies can be interconnected by permuting similar edges between the copies. If the permutations are restricted to cyclic permutations, the resulting graph will correspond to a quasi-cyclic LDPC with lifting Z = 3. The original graph from which three copies were made is referred to here as the base graph. To obtain derived graphs of different sizes, the copy and permute operation can be applied to a base graph.

[0083] A corresponding parity check matrix of the raised graph can be constructed from the parity check matrix of the base graph, Petition 870210036966, dated 04 / 23 / 2021, p. 36 / 105 33 / 62 replacing each entry in the base parity check matrix with a ZxZ matrix. Entries of 0 (those that have no base edges) are replaced by the 0 matrix and entries of 1 (indicating a base edge) are replaced by a ZxZ permutation matrix. In the case of cyclic lifts, the permutations are cyclic permutations.

[0084] A cyclically raised LDPC code can also be interpreted as a code over the modulus ring of the binary polynomial xz+1. In this interpretation, a binary polynomial, (x) = bc + b1X + b2x2+ ... + bz-1xz-1 can be associated with each variable node in the base graph. The binary vector (bü, b1, b2,..., bz-1) corresponds to the bits associated with the corresponding Z variable nodes in the raised graph, i.e., Z copies of a single base variable node. A cyclic permutation by k of the binary vector is achieved by multiplying the corresponding binary polynomial by xk, where the multiplication is done modulo xz + 1. A parity check of degree d on the base graph can be interpreted as a linear restriction on the neighboring binary polynomials B1(x),..., Bd(x) written as xk1B1(x) + xk2B2(x) + ... + xkdBd(x) = 0 where the values, k1,..., kd are the cyclic lifting values ​​associated with the corresponding edges.

[0085] This resulting equation is equivalent to the Z parity checks on the cyclically raised Tanner plot, corresponding to the associated single parity check on the base plot. Thus, the parity check matrix for the raised plot can be expressed using the matrix for the base plot, in which entries of 1 are replaced by monomials in the form x and entries of 0 are Petition 870210036966, dated 04 / 23 / 2021, page 37 / 105 34 / 62 raised as 0, but now 0 is interpreted as the modulus of the binary polynomial 0 xz + 1. This matrix can be written by supplying the value k in place of xk. In this case, the polynomial of 0 is sometimes represented as -1 and sometimes as another character to distinguish it from x0.

[0086] Typically, a square submatrix of the parity check matrix represents the parity bits of the code. The complementary columns correspond to the information bits that, at the time of encoding, are defined as equal to the information bits to be encoded. Encoding can be achieved by solving the variables in the aforementioned square submatrix in order to satisfy the parity check equations. The parity check matrix H can be divided into two parts M and N, where M is the square portion. Thus, encoding reduces to solving Mc = s = Nd where ced comprise x. In the case of quasi-cyclic codes or cyclically lifted codes, the algebra above can be interpreted as being over the ring of modulo binary polynomials xz + 1. In the case of IEEE 802.11 LDPC codes, which are quasi-cyclic, the encoding submatrix M has an integer representation, as shown in FIG. 6.

[0087] A received LDPC codeword can be decoded to produce a reconstructed version of the original codeword. In the absence of errors, or in the case of correctable errors, decoding can be used to recover the original data unit that was encoded. Redundant bits can be used by decoders to detect and correct bit errors. LDPC decoders generally operate by performing local calculations iteratively. Petition 870210036966, dated 04 / 23 / 2021, page 38 / 105 35 / 62 and transmitting these results by exchanging messages within the 400 bipartite graph, along the edges, and updating these messages by performing calculations on the nodes based on the received messages. These steps can generally be repeated multiple times and can be called message-passing steps. For example, each variable node 410 in the 400 graph can initially be provided with a soft bit (e.g., representing the received bit of the codeword) that indicates an estimate of the associated bit value, as determined by observations of the communication channel. Using these soft bits, LDPC decoders can update messages by iteratively reading them, or part of them, from memory and writing an updated message, or part of it, back to memory. The update operations are generally based on the parity-checking constraints of the corresponding LDPC code.In implementations for raised LDPC codes, messages on similar edges are often processed in parallel.

[0088] LDPC codes designed for high-speed applications generally use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations. LDPC codes with higher code rates (e.g., the ratio of message size to codeword length) tend to have relatively fewer parity checks. If the number of base parity checks is less than the degree of a variable node (e.g., the number of edges connected to a variable node), in the base graph, Petition 870210036966, dated 04 / 23 / 2021, page 39 / 105 36 / 62 This variable node will be connected to at least one of the base parity checks by two or more edges (for example, the variable node may have a double edge). Or if the number of base parity checks is less than the degree of a variable node (for example, the number of edges connected to a variable node), in the base graph, this variable node will be connected to at least one of the base parity checks by two or more edges. Having a base variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes. For example, these double edges can result in multiple simultaneous read and write operations on the same memory locations, which in turn can create data coherence problems.A double edge in a base LDPC code can trigger the parallel read of the same memory location of the soft bit value twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values ​​that are written back to memory, to properly incorporate the two updates. However, eliminating double edges in the LDPC code helps avoid this extra complexity.

[0089] In the definition of standard irregular LDPC code sets (degree distributions), all edges in the Tanner graph representation can be statistically interchangeable. In other words, there is a single statistical equivalence class of edges. A more detailed discussion of the LDPC codes raised can be found, for example, in the book entitled Modern Petition 870210036966, dated 04 / 23 / 2021, page 40 / 105 37 / 62 Coding Theory, published on March 17, 2008 by Tom Richardson and Ruediger Urbanke. For multi-edge LDPC codes, several edge equivalence classes may be possible. While in the standard irregular LDPC set definition, the nodes in the graph (variable and constrained) are specified by their degree, that is, the number of edges to which they are connected, in the multi-edge type configuration, an edge degree is a vector; it specifies the number of edges connected to the node of each edge equivalence class (type) independently. A multi-edge type set is composed of a finite number of edge types. The degree type of a constraint node is a vector of (non-negative) integers; the i-th entry of this vector records the number of sockets of the i-th type connected to that node. This vector can be called the edge degree.The degree type of a variable node has two parts, although the degree type can be viewed as a vector of (non-negative) integers. The first part refers to the received distribution and will be called the received degree, and the second part specifies the edge degree. The edge degree plays the same role as the constraint nodes. Edges are typed when pairing sockets of the same type. This constraint that sockets must pair with sockets of the same type characterizes the concept of multi-edged typing. In a multi-edged typing description, different node types can have different received distributions (e.g., the associated bits can pass through different channels).

[0090] FIG. 7 illustrates a portion 704 of a radio frequency (RF) modem 700 that can be configured to Petition 870210036966, dated 04 / 23 / 2021, p. 41 / 105 38 / 62 provide an encoded message for wireless transmission. In one example, a 706 encoder at a base station (e.g., Node B 102 and / or transmitter system 210) (or wireless node in the reverse path) receives bits of information from a 702 message for transmission. The 702 message may contain encoded data and / or voice or other content directed to the receiving device. The 706 encoder encodes the message using a suitable modulation and coding scheme (MCS), typically selected based on a configuration defined by the base station or other network entity. In some cases, the 706 encoder may encode the message, for example, in accordance with aspects of this disclosure (e.g., implementing operations 1500 illustrated in (FIG. 15). A coded bit stream 708 produced by the encoder 706 can then be supplied to a mapper 710 which generates a sequence of symbols Tx 712 that are modulated, amplified and processed by the chain Tx 714 to produce an RF signal 716 for transmission through the antenna 718.

[0091] FIG. 8 illustrates a portion 814 of an RF modem 800 that can be configured to receive and decode a wirelessly transmitted signal including an encoded message (e.g., a message encoded using an LDPC code as described above). In several examples, the modem 814 that receives the signal may reside in the wireless node (e.g., wireless node 116, receiving system 250), in the base station (e.g., Node B 102, transmitting system 210), or in any other means or apparatus suitable for performing the functions described (e.g., wireless device 302). An antenna 802 receives an RF signal 816 (e.g., the RF signal 716, produced in FIG. 7, altered by the channel). Petition 870210036966, dated 04 / 23 / 2021, p. 42 / 105 39 / 62 effective between RF chain 700 and RF chain 800) to a wireless node (e.g., wireless node 116, 122 and / or receiver system 250). An RF chain 804 processes and demodulates the RF signal 816 and can provide a sequence of demodulated symbols 806 to a demapper 808, which produces a bit stream (e.g., a series of received values ​​r_j, which may be referred to as smooth bits or scaled smooth bits and may be represented by log probability ratios) 810 representative of the encoded message.

[0092] An 812 decoder can then be used to decode m-bit information strings from a bitstream that has been encoded using an encoding scheme (e.g., an LDPC code). The 812 decoder may comprise a layered LDPC decoder with a full-parallel, line-parallel, or block-parallel architecture. LDPC decoders typically operate by iteratively performing local calculations and transmitting these results by exchanging messages within the 400 bipartite graph, along the edges, and updating these messages by performing calculations at the nodes based on the received messages. These steps can often be repeated multiple times and may be called message-passing steps.For example, each variable node 410 in graph 400 can initially be provided with a soft bit (e.g., representing the received bit, r_j, of the codeword) that indicates an estimate of the associated bit value, as determined by observations of the communication channel. The soft bit can be represented by a log-likelihood ratio (LLR) which, in some respects, can be... Petition 870210036966, dated 04 / 23 / 2021, page 43 / 105 40 / 62 defined as the log ((probability of the bit being 0) / (probability of the bit being 1)). Using these LLRs, LDPC decoders can update messages by iteratively reading them, or part of them, from memory and writing an updated message, or part of it, back to memory. The update operations are generally based on the parity checking constraints of the corresponding LDPC code. In implementations for raised LDPC codes, messages on similar edges are often processed in parallel. According to aspects of the present disclosure, following these decoding techniques, the 812 decoder can decode the 810 bit stream based on the LLRs to determine the 702 message containing data, encoded voice, and / or other content transmitted from the base station (e.g., Node B 102 and / or transmitter system 210).The decoder can decode the 810 bit stream in accordance with aspects of the present disclosure presented below (for example, implementing the 1400 operations illustrated in FIG. 14). EXAMPLE OF LDPC DECODER ARCHITECTURE

[0093] Low-density parity-check coding (LDPC) is a powerful error-correcting coding technology used in various applications such as wireless communications, storage, and Ethernet. LDPC is based on the design of codes on bipartite graphs, for example, as described above and illustrated in FIG. 4A. LDPC decoding is typically implemented using belief propagation techniques, described above, where messages are passed along the edges of the graph and nodes on the graph calculate their marginal distributions to Petition 870210036966, dated 04 / 23 / 2021, page 44 / 105 41 / 62 from which decisions about the source symbols can be made. Quasi-cyclic (QC) codes are a popular class of structured LDPC codes, in which a base LDPC parity check matrix (PCM) is 'lifted'. For example, lifting involves replacing each base PCM entry with a ZxZ submatrix. The ZxZ submatrix can be an all-zero matrix for base PCM entries '0' or a cyclically rotated identity matrix for base PCM entries '1'. LDPC QC codes enable parallel processing in hardware, enabling decoders, such as the decoder illustrated in FIG. 8, to replicate the processing Z times with switching networks to exchange messages.

[0094] LDPC decoders implement message transmission algorithms, which are generally rough approximations of the belief propagation (BP) algorithm. The log BP algorithm for LDPC decoding can be written as: —SneW(m) ( / '(Çmn)) (eq D n* / Sm / = nn6Mm)^n(L(qmn)) (eq 2) n* / Rm) ~sm)^ (^m / ) (eq. ^(^ / )=Σγπ and M( / ) Rmi + R) (eq. 4) £(<7m / ) = £( <? / ) —«m / (eq. 5) em que L(c) é uma razão de log-verossimilhança (LLR) associada para a variável binária c definida como Petition 870210036966, dated 04 / 23 / 2021, p. 45 / 105 42 / 62 where the probability is conditional on certain implicit information in the message transmission algorithm that expands as the algorithm progresses. The function Ψ is given by Ψ00 = logcoth (l^ll) index m usually indicates a binary parity check node or a binary PCM row index, jen usually indicates the bit node or the PCM column index qj which indicates the bit value associated with variable node j, equivalent to the jth binary PCM column, and qmn indicates the binary value associated with the edge connection variable node n to check node m, N(m) is the set of all bit indices for bits connected to parity check node m, M(j) is the set of all parity check node indices for all parity check nodes connected to bit j, and Rj is the LLR of bit j associated with the transmission observation of bit j. For example, in a standard BPSK transmission on an AWGN channel, we have σ where rj is the received value and σ2 is the additive noise variation of the channel. The algorithm can be initialized by setting L(qmj) equal to Rj and proceeds by repeatedly evaluating the given equations.According to aspects of the present disclosure, Equation 1 calculates a parity check metric Amj for bit j that sums the received bit LLRs L(qmn) for all bits connected to the parity check node m (other than the bit LLR g) via a Ψ transformation. This operation, together with Equation 3, calculates a posterior LLR, Rmj, for bit j based on observations of the other bits belonging to the parity check m. A. Petition 870210036966, dated 04 / 23 / 2021, p. 46 / 105 43 / 62 Equation 2 calculates the sign, Smj, of the posterior LLR, Rmj, based on the signs of the received bit LLRs L(qmn). Equation 4 calculates the updated bit LLRs, L(qj), by combining all the posterior LLRs Rmj (i.e., extrinsic LLRs) from the bit j decoder with the channel's prior LLR Rj (i.e., intrinsic LLR). Equation 5 subtracts the extrinsic LLR Rmj for the parity check node m from the sum of the bit LLR L(qj) before the sum of the bit LLR L(qmj) is passed back to the parity check node m for the calculation of an updated posterior and / or extrinsic LLR Rmj in the next iteration. For one iteration of the 'flood' LDPC decoder, steps 1-3 (i.e., calculating Equations 1-3) are performed for all parity check nodes, after all bit (variable) nodes perform step 4 (i.e., calculate Equation 4) to update the bit LLRs L(qj).

[0095] Layered LDPC decoders perform steps similar to Equations 1 to 5 above, but with some minor modifications. For example, the layered log BP algorithm can be written as: = I'M -Rmj (eq 6) Ajnj=Ση€Ν(πι)Ψ (I'Cflmn)) 7) η* / Smj Πη€\(τη)^ί5^( / '(ίπιπ)) η* / Rmj= —(·4 / η / )=+Rmi

[0096] In the steps of (eq 8) (eq 9) (eq 10) layered decoding Petition 870210036966, dated 04 / 23 / 2021, page 47 / 105 44 / 62 above (i.e., Equations 6-10), the bit LLRs L(qj) are initialized with the channel bit of the LLRs Rj. According to certain aspects of the present disclosure, an important difference between layered decoding (Equations 6-10) and flood decoding (Equations 1-5) is that in a layered decoding iteration, when the posterior LLR, Rmj, is calculated for a specific parity check node (PGM line) in Equation 9, the bit LLRs L(qj) are immediately updated with the new posterior LLRs, Rmj, in Equation 10 before calculating the next line are the posterior LLRs Rmj in Equations 6-9. This contrasts with the flood decoder, where all the a posteriori LLRs, Rmj, corresponding to the PGM lines are calculated (Equations 1-3 are repeated over all mej) before all bit LLRs L(qj) are updated with the a posteriori LLRs, Rmj, in Equation 4.As a result, layered decoding allows information, in the form of updated later LLRs, Rmj, to propagate through the belief propagation message faster than a flood decoder, resulting in faster decoder convergence.

[0097] FIG. 9 illustrates a high-level block diagram of a generic 900 layered LDPC decoder, which may be an example of the 812 decoder illustrated in FIG. 8. As illustrated, the layered LDPC decoder includes the LLR 902 storage memory for storing bit LLRs (e.g., L(qj)) (i.e., a bit-by-bit LLR of the codeword), which is initialized by the LLRs of -2Γ) channel bit (for example, ), which, in turn, are Petition 870210036966, dated 04 / 23 / 2021, p. 48 / 105 45 / 62 updated by later LLRs (e.g., Rmj). Channel bit LLRs or received LLRs are also known as soft bits or scaled soft bits, and the received value r_j is a soft bit. The 900-layer LDPC decoder also includes 904 datapath processors that operate in parallel to calculate a posteriori LLRs and update bit LLRs stored in the LLR storage memory 902. The 900-layer LDPC decoder additionally includes a 906 metric storage memory to store a posteriori LLRs calculated by the 904 datapath processors and a permutation network 908 to route LLRs (e.g., bit LLRs and later LLRs) between memories 902, 906, and datapath processors 904.

[0098] As discussed above, layered decoding traverses PCM columns (bit LLRs) along a row in the PCM to calculate a posteriori LLRs for that row. After the row's a posteriori LLRs are calculated, the bit LLRs are each immediately updated with the corresponding a posteriori LLR as they are fed into the calculation of the next row's a posteriori LLRs. If the column index of the updated bit LLR is connected to the next row, the updated bit LLR is passed to the calculation of the next row's a posteriori LLR. If there is no connection, the updated bit LLR can be stored in LLR 902 storage memory.

[0099] FIG. 10 illustrates an example of this process for calculating / updating bit LLRs and posterior LLRs in a 1000 parity check matrix (PCM) as described above. In particular, each cell of the PCM illustrates Petition 870210036966, dated 04 / 23 / 2021, page 49 / 105 46 / 62 a posteriori LLR calculated. For example, for the PCM illustrated in FIG. 10, once the posteriori LLRs of row 3, labeled 1002, are computed, the bit LLR of column 5, labeled 1010, can be updated (for example, using Equation 10 above) and used in the calculation of the posteriori LLR of row 4, labeled 1006 (for example, using the Equations 6-9 above), since column 5 is connected to rows 3 and 4 (e.g., PCM entries (3, 5), labeled 1020 and (4, 5), labeled 1022, are non-zero). However, when the bit LLR of column 6, labeled 1012, is updated with a posteriori LLR calculated from row 3 (labeled 1002), the updated bit LLR is stored in memory (e.g., storage memory LLR 902) because the calculation of the posteriori LLR of row 4 does not include column 6, since (4, 6), labeled as 1024, is empty. When the posteriori LLRs of row 5, labeled 1008, are being calculated, the bit LLR of column 6 is read from memory (e.g., storage memory LLR 902) instead of being passed from the previous update computation. It should also be noted that read and write conflicts are possible, as Equations 6 and 10 can both read and write to the LLR 902 Storage Memory. Such conflicts can create delays in a processing pipeline if the LLR 902 Storage Memory has only a single read and write port.

[0100] There may also be delays introduced due to recursive processing, where bit LLR updates for one line (layer) are passed to the next layer's posterior LLR processing, for which the computed posterior LLRs are used. Petition 870210036966, dated 04 / 23 / 2021, page 50 / 105 47 / 62 update the bit LLRs again. For example, given a non-zero processing pipeline depth, there may be a gap between bit LLR update phases so that a posteriori LLR calculations can be completed.

[0101] For example, FIG. 11A illustrates an example of processing pipeline 1100 showing this line-by-line processing to calculate a posteriori LLRs and update bit LLRs based on the a posteriori LLRs. As illustrated in FIG. 11A, pipeline delays (e.g., processing gaps) 1102, 1104, 1106, and 1108 are present due to recursive processing with an interdependence between the a posteriori calculation (e.g., Equations 6-9) and the bit LLR update steps (e.g., Equation 10). Pipeline delays increase with increasing pipeline depth, as well as memory conflicts, for example, as illustrated in the processing pipeline example 1150 shown in FIG. 11B, where it can be seen that an increase in pipeline depth to 3 cycles, along with memory conflicts, increases the number of processing cycles wasted due to pipeline delays 1152, 1154, 1156 and 1158.Thus, aspects of this disclosure present techniques for mitigating pipeline delays in LDPC decoding, for example, using a parity-checking matrix with full row orthogonality or near row orthogonality as described in more detail below. Line orthogonality in the design compatible with the LDPC rate.

[0102] Layered LDPC decoders often have delays in the update process, Petition 870210036966, dated 04 / 23 / 2021, p. 51 / 105 48 / 62 for example, as described above. For example, in a check-layer decoder, updates to the sums of the variable nodes (e.g., a posteriori computation described above, for example, using Equations 6-9) occur after the completion of a check layer update (e.g., the bit LLR update steps described above, for example, using Equation 10), and the incorporation of these updates may be delayed by additional processing steps and memory accesses. If the edge connectivity of the base LDPC code is such that the variable nodes are connected to two consecutive layers, there will be a negative impact on the decoder's performance. When the second layer is processed, the updated variable node sum may still not be available; therefore, the potential gain from processing the previous layer is not available and does not benefit the performance of that layer.In some cases, this lack of updated variable node sums can be circumvented by introducing an additional delay. However, this additional delay can result in a slowdown of the decoder and potentially impair performance by reducing the total number of available iterations.

[0103] In some cases, subsequent layers of an LDPC code may be restricted to being 'orthogonal', meaning that subsequent layers do not have common base variable nodes. This restriction may, however, degrade performance through the implicit restriction in the base graph structure, which limits graph connectivity.

[0104] LDPC projects for 5G NR are generally Petition 870210036966, dated 04 / 23 / 2021, page 52 / 105 49 / 62 compatible rates and have a high-rate core graph consisting of the first layers (e.g., approximately 6 layers or rows) of the construct, followed by layers of hybrid auto-repeat request (HARQ) bits that are used to lower the code rate, for example, as illustrated in FIGS. 12 and 12A to 12H. Note that FIGS. 12A to 12H represent a parity check matrix when arranged as illustrated in FIGS. 12. That is, FIGS. 12A to 12D show rows 1-23 of a parity check matrix and FIGS. 12E to 12H show rows 24-50 of the same parity check matrix.

[0105] In some cases, it may not be feasible to guarantee orthogonality in the core graph. In recent LDPC designs for 5G NR, the base graphs often include two relatively high-degree punched variable nodes (e.g., columns 1 and 2) that are punched, as illustrated in columns 1210 and 1212 in matrix 1200 in FIGS. 12A and 12E. Graph connectivity optimization often results in high connectivity (many edges) for these nodes, especially in the early HARQ parity layers designed for use in relatively high-rate transmissions. This has led to the notion of 'near orthogonality', meaning that subsequent layers (e.g., subsequent to the core layers of the base graph) are orthogonal except at the high-degree punched nodes (and possibly the core parity bit formed from these two nodes), which may be repeatedly connected in subsequent layers.Most decoder implementations will absorb degradation due to delayed updates for high-degree punctured variable nodes. Petition 870210036966, dated 04 / 23 / 2021, page 53 / 105 50 / 62

[0106] According to aspects of the present disclosure, FIGS. 12A-12H illustrate an example of a raised parity check matrix 1200 that is almost line orthogonal. For example, each row can represent a layer, except the first three rows labeled 1202, 1204, and 1206 (see FIGS. 12A-12D), which represent labels. The first (top) row 1202 contains labels that enumerate the columns of the matrix. The second row 1204 contains labels that are encoding indicators, where 1 indicates a systematic (information) column and 0 indicates a parity column. The third row 1206 contains labels that are transmission indicators, where a 0 indicates punching (i.e., no transmission) and a 1 indicates transmission.

[0107] According to aspects of the present disclosure, the first two columns 1210 and 1212 (see FIGS. 12A and 12E) of the parity check matrix illustrated in FIGS. 12A-12H represent high-degree punched variable nodes and column 23, labeled 1214 (see FIGS. 12B and 12F), represents a special parity bit formed from the two punched columns. The main portion of the graph consists of the first 6 rows (layers) and the HARQ lines begin at the seventh row, labeled 1220 (see FIGS. 12A-12D), below. Note that from the seventh row below, no column has a non-empty entry in two consecutive rows other than columns 1, 2, and 23, labeled 1210, 1212, and 1214. Thus, the parity check matrix illustrated in FIGS. 12 and 12A-12H are almost row orthogonal.

[0108] As HARQ layers are added Petition 870210036966, dated 04 / 23 / 2021, page 54 / 105 51 / 62 and the corresponding transmission rate decreases, the connectivity of these nodes can be relaxed. Frequently, beyond a certain point, as the number of layers increases and the rate of the target code decreases, the connectivity density of the punctured nodes decreases. In particular, at most one of the punctured nodes will normally be connected to each layer. If, in addition, the design has almost balanced connectivity of the two punctured nodes, meaning that each connects to approximately the same number of layers, it is possible to obtain full orthogonality for these layers, for example, as illustrated in FIGS. 13 and 13A to 13H.

[0109] As noted above, FIGS. 13A-13H illustrate, when arranged as shown in FIG. 13, a 1300 parity check matrix similar to the 1200 parity check matrix illustrated in FIGS. 12A-12H, except that the 1300 parity check matrix is ​​fully orthogonal in pairs after row / layer 14 (see FIGS. 13A-13D). For example, as illustrated, row / layer 14 is the last layer in which the two punched variable nodes (columns 1 and 2, labeled 1310 and 1312) are connected. All subsequent rows (layers) are fully orthogonal in pairs. For example, as illustrated, there are no two consecutive rows after row 14, labeled 1322, with an entry in the matrix in the same column, thus making the rows after row 14 fully orthogonal in pairs. Note that the high-degree punched variable nodes are connected alternately, thus allowing the rows to be fully orthogonal.

[0110] According to aspects of the present Petition 870210036966, dated 04 / 23 / 2021, page 55 / 105 52 / 62 disclosure, the use of the parity check matrix illustrated in FIGS. 13A-13H increases the decoder's performance, for example, by allowing the most up-to-date variable checksums to be used in the decoding process of a row of the parity check matrix. For example, since no variable node is connected to two consecutive layers, the decoder has time to calculate the updated variable checksums before the updated variable checksums are needed to process another row.

[0111] Thus, aspects of the present disclosure propose techniques for increasing the availability of updated variable node sums used during decoding without the performance degradation associated with adding additional delays during the decoding process (discussed above), for example, by maintaining full layer orthogonality for all layers below the last layer in which the two base-punched variable nodes are connected to the same layer. Such a constraint (e.g., full row orthogonality) can result in an alternating structure where the two punched nodes alternate connectivity with subsequent layers, for example, as illustrated in FIGS. 13 and 13A-13H (note FIGS. 13A-13H illustrate a 1300 parity check matrix, with FIGS. 13A-13D illustrating rows 1-21 of the 1300 parity check matrix and FIGS.13E-13H illustrating rows 22-50 of the 1300 parity check matrix) and can result in approximately 2 / 3 (e.g., more than 1 / 2) orthogonality of all layers. Petition 870210036966, dated 04 / 23 / 2021, p. 56 / 105 53 / 62

[0112] FIG. 14 illustrates an example of 1400 operations for wireless communications, for example, to reduce processing delays when decoding bits encoded in LDPC. Depending on certain aspects, 1400 operations can be performed by a wireless communication device (e.g., by a receiver and a decoder (e.g., decoder 812) in the wireless communication device), such as a base station (e.g., Node B 110 and / or base station 210), a user equipment (e.g., UE 116 and / or UE 250) and / or wireless device 302.

[0113] Operations 1400 begin in block 1402 by the wireless communications device receiving soft bits associated with an LDPC codeword. For example, UE 116 (e.g., a UE 116 receiver) receives soft bits associated with an LDPC codeword from base station 102.

[0114] In 1404, the wireless communication device performs LDPC decoding of soft bits using a parity check matrix, where: each row of the parity check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity check matrix correspond to punched variable nodes of the raised LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which at least two punched variable nodes are connected. Continuing the example above, the UE 116 (e.g., a UE 116 decoder) performs LDPC decoding of soft bits (i.e., the soft bits received in block 1402) using a parity check matrix (e.g., the parity check matrix). Petition 870210036966, dated 04 / 23 / 2021, p. 57 / 105 54 / 62 parity 1300 illustrated in FIGS. 13 and 13A-13H), where each row of the parity check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity check matrix correspond to punched variable nodes of the raised LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows below a row to which at least two punched variable nodes are connected.

[0115] FIG. 15 illustrates an example of 1400 operations for wireless communications, for example, to perform LDPC encoding. Depending on certain aspects, 1500 operations can be performed by a wireless communication device (for example, by a transmitter and an encoder (for example, encoder 706) in the wireless communication device), such as a base station (for example, Node B 110 and / or base station 210), a user equipment (for example, UE 116 and / or UE 250) and / or wireless device 302.

[0116] Operations 1500 begin in block 1502 by the wireless communication device, obtaining bits of information from a codeword. For example, UE 116 (e.g., a UE 116 encoder) obtains bits of information from a codeword (e.g., from an application running on UE).

[0117] In 1504, the wireless communication device performs the encoding of information bits to calculate the parity bits of an LDPC codeword according to a parity check matrix, where: each row of the parity check matrix corresponds to a parity check raised from an LDPC code. Petition 870210036966, dated 04 / 23 / 2021, p. 58 / 105 55 / 62 raised, in at least two columns of the parity check matrix correspond to the punched variable nodes of the raised LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which at least two punched variable nodes are connected. Continuing the example above, the UE 116 (e.g., a UE 116 encoder) performs the encoding of the information bits (i.e., the information bits obtained in block 1502) according to a parity check matrix (e.g., the 1300 parity check matrix illustrated in FIGS.13 and 13A-13H), where each row of the parity check matrix corresponds to a raised parity check of a raised LDPC code, at least two columns of the parity check matrix correspond to punched variable nodes of the raised LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows below a row to which at least two punched variable nodes are connected.

[0118] The methods disclosed herein comprise one or more steps or actions to achieve the described method. The steps and / or actions of the method may be interchangeable without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0119] As used here, the term determine encompasses a wide variety of actions. For example, Petition 870210036966, dated 04 / 23 / 2021, page 59 / 105 56 / 62 Determining can include calculation, computation, processing, derivation, investigation, research (e.g., searching in a table, database, or other data structure), verification, and the like. Furthermore, determining can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), and the like. Additionally, determining can include resolving, selecting, choosing, establishing, and the like.

[0120] In some cases, instead of actually transmitting a frame, a device may have an interface to emit a frame for transmission. For example, a processor may emit a frame, via a bus interface, to an RF front end for transmission. Similarly, instead of actually receiving a frame, a device may have an interface to obtain a frame received from another device. For example, a processor may obtain (or receive) a frame, via a bus interface, from an RF front end for transmission.

[0121] The various operations of the methods described above can be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including, but not limited to, a circuit, an application-specific integrated circuit (ASIC), or a processor. Generally, where operations illustrated in the figures exist, these operations may have corresponding components of means with similar function and numbering.

[0122] For example, means to compute, means to determine, means to use, means to update, Petition 870210036966, dated 04 / 23 / 2021, pages 60 / 105 57 / 62 means for reading, means for performing and / or means for selecting may comprise a processing system that includes one or more processors, such as processor 230 and / or data processor RX 242 of base station 210 and / or processor 270 and / or data processor RX 260 of user terminal 250. In addition, means for storing may comprise a memory, such as memory 232 of base station 210 and / or memory 272 of user terminal 250. In addition, means for receiving may comprise a receiver and / or antenna, such as receiver 222 and / or antenna 224 of base station 210 and / or receiver 254 and / or antenna 252 of user terminal 250.

[0123] The various logic blocks, modules, and illustrative circuits described in connection with this disclosure may be implemented or realized with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, it may be any commercially available processor, controller, microcontroller, or state machine.A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors together with a DSP core, or any other configuration. Petition 870210036966, dated 04 / 23 / 2021, page 61 / 105 58 / 62

[0124] If implemented in hardware, an example of a hardware configuration might comprise a processing system on a wireless node. The processing system can be implemented with a bus architecture. The bus can include any number of interconnect buses and bridges, depending on the specific application of the processing system and general design constraints. The bus can connect various circuits, including a processor, machine-readable media, and a bus interface. The bus interface can be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter can be used to implement the signal processing functions of the PHY layer. In the case of a wireless node (see FIG. 1), a user interface (e.g., keyboard, monitor, mouse, joystick, etc.) can also be connected to the bus.The bus can also connect various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art and therefore will not be described further. The processor can be implemented with one or more general-purpose and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Skilled individuals will recognize the best way to implement the described functionality for the processing system, depending on the specific application and the general design constraints imposed on the overall system.

[0125] If implemented in software, the functions Petition 870210036966, dated 04 / 23 / 2021, page 62 / 105 59 / 62 can be stored or transmitted as one or more instructions or codes on a computer-readable medium. Software should be broadly interpreted as instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or others. Computer-readable media includes storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. The processor may be responsible for managing the bus and general processing, including the execution of software modules stored on machine-readable storage media. A computer-readable storage medium may be coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be an integral part of the processor.For example, machine-readable media may include a transmission line, a data-modulated carrier wave, and / or a computer-readable storage medium with instructions stored separately from the wireless node, which can be accessed by the processor through the bus interface. Alternatively, or in addition, machine-readable media, or any portion thereof, may be integrated into the processor, as is the case with cache and / or general-purpose register files. Examples of machine-readable storage media may include, by way of example, RAM (Random Access Memory), flash memory, ROM (Read-Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Engine-Free Memory). Petition 870210036966, dated 04 / 23 / 2021, page 63 / 105 60 / 62 read-only programmable electrically erasable discs, records, magnetic disks, optical disks, hard disks, or any other suitable storage medium, or any combination thereof. Machine-readable media may be incorporated into a computer program product.

[0126] A software module can comprise a single instruction, or many instructions, and can be distributed across several different code segments, between different programs, and across various storage media. Computer-readable media can comprise multiple software modules. Software modules include instructions that, when executed by a device such as a processor, cause the processing system to perform various functions. Software modules can include a transmit module and a receive module. Each software module can reside on a single storage device or be distributed across multiple storage devices. For example, a software module can be loaded into RAM from a hard drive when a trigger event occurs. During the execution of the software module, the processor can load some of the instructions into the cache to increase access speed.One or more cache lines can be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that this functionality is implemented by the processor when executing instructions from that software module.

[0127] Furthermore, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server Petition 870210036966, dated 04 / 23 / 2021, pp. 64 / 105 61 / 62 or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks generally reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some respects, computer-readable media may comprise non-transient computer-readable media (e.g., tangible media). Furthermore, in other respects, computer-readable media may comprise transient computer-readable media (e.g., a signal).Combinations of the above items should also be included within the scope of computer-readable media.

[0128] Thus, certain aspects may comprise a computer program product for performing the operations presented here. For example, this computer program product may comprise a computer-readable medium with instructions stored (and / or encoded) therein, the instructions being executable by one or more processors to perform the operations described herein.

[0129] Furthermore, it should be appreciated that the modules and / or other appropriate means to perform the methods and techniques described herein may be downloaded and / or otherwise obtained by a wireless node and / or base station, as applicable. For example, such a device may be Petition 870210036966, dated 04 / 23 / 2021, pages 65 / 105 62 / 62 coupled to a server to facilitate the transfer of media to perform the methods described herein. Alternatively, several methods described in this document may be provided by storage media (e.g., RAM, ROM, a physical storage medium such as a CD or floppy disk, etc.), so that a wireless node and / or base station may obtain the various methods by coupling with or providing the storage media to the device. Furthermore, any other suitable technique for providing the methods and techniques described herein to a device may be used.

[0130] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, alterations, and variations may be made to the arrangement, operation, and details of the methods and apparatus described above, without departing from the scope of the claims. Petition 870210036966, dated 04 / 23 / 2021, page 66 / 105

Claims

1 / 8 CLAIMS 1. Method for performing quasi-cyclic low-density parity check decoding, QC-LDPC, for hybrid auto-repeat request transmission, HARQ, using a rate-compliant QC-LDPC design, the method comprising: receiving soft bits associated with a QC-LDPC codeword (1402) from a QC-LDPC code of the rate-compliant QC-LDPC design; and performing QC-LDPC decoding of the soft bits using a parity check matrix (1300) of the QC-LDPC code obtained by surveying an LDPC base graph, wherein the parity check matrix comprises: a first plurality of rows representing a leading portion (1320) corresponding to a high-rate QC-LDPC code and a second plurality of HARQ rows after the first plurality of rows used to de-rate the high-rate QC-LDPC code;Each row of the first and second row plurality of rows of the parity check matrix comprises non-empty entries, each with an integer value, representing a cyclically rotated ZxZ identity matrix, or empty entries, each representing a ZxZ submatrix entirely of zeros; at least two columns, wherein two columns (1310, 1312) correspond to two high-degree punched variable nodes of the LDPC base graph; at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected, and at least two rows below the lowest row (1322) of said at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected;and Petition 870250040184, dated 05 / 16 / 2025, p. 14 / 22 2 / 8 wherein the parity check matrix has row orthogonality between each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two punctured variable nodes of the LDPC base graph are both connected (1404), wherein no column has a non-empty entry in each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected;and characterized by the fact that: the two high-degree punctured variable nodes of the LDPC base graph alternate, from line to line, their respective line connectivity to all lines in the parity check matrix, below the said lowest line of the said at least one line to which the two high-degree punctured variable nodes of the LDPC base graph are both connected.

2. A method according to claim 1, characterized in that at least 1 / 2 of all consecutive row pairs of the parity check matrix have row orthogonality.

3. A method according to claim 2, characterized in that at least 1 / 2 of all consecutive row pairs comprises the last 1 / 2 of all rows in the parity check matrix, and wherein the last 1 / 2 of all rows in the parity check matrix corresponds to the HARQ rows.

4. Apparatus for performing quasi-cyclic low-density parity check decoding, QC-LDPC, for hybrid auto-repeat request transmission, HARQ, using a rate-compliant QC-LDPC design, comprising: one or more processors configured to: cause the apparatus to receive soft bits associated with a QC-LDPC code word from a rate-compliant QC-LDPC design; and perform QC-LDPC (812) decoding of the soft bits using a parity check matrix (1300) of the QC-LDPC code obtained by surveying an LDPC base graph, wherein: the parity check matrix comprises: a first plurality of rows representing a principal portion (1320) corresponding to a high-rate QC-LDPC code and a second plurality of HARQ rows after the first plurality of rows used to decrease the rate of the high-rate QC-LDPC code;Each row of the first and second row plurality of rows of the parity check matrix comprises non-empty entries, each with an integer value, representing a cyclically rotated ZxZ identity matrix, or empty entries, each representing a ZxZ submatrix entirely of zeros; at least two columns, wherein two columns (1310, 1312) correspond to two high-degree punched variable nodes of the LDPC base graph; at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected, and at least two rows below the lowest row (1322) of said at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected;and wherein the parity check matrix has row orthogonality between each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two punctured variable nodes of the LDPC base graph are both connected, wherein no column has a non-empty entry in each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected; and characterized in that: the two high-degree punctured variable nodes of the LDPC base graph alternate, from row to row, their respective row connectivity for all rows in the parity check matrix, below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected;and one or more memory modules coupled to one or more processors.

5. Apparatus according to claim 4, characterized in that at least 1 / 2 of all consecutive row pairs of the parity check matrix have row orthogonality.

6. Apparatus according to claim 5, characterized in that 1 / 2 of all consecutive row pairs comprises the last 1 / 2 of all rows of the parity check matrix and in that the last 1 / 2 of all rows of the parity check matrix corresponds to the HARQ rows.

7. Method for performing quasi-cyclic low-density parity check coding, QC-LDPC, for hybrid automatic repeat request transmission, HARQ, using a rate-compliant QC-LDPC design, the method comprising: obtaining information bits of a QC-LDPC codeword (1502) from a QC-LDPC code of the rate-compliant QC-LDPC design; and performing encoding of the information bits to calculate parity bits of the QC-LDPC codeword according to a parity check matrix (1300) of the QC-LDPC code obtained by surveying an LDPC base graph, wherein the parity check matrix comprises: a first plurality of rows representing a principal portion Petition 870250040184, dated 05 / 16 / 2025, p. 17 / 22 5 / 8 (1320) corresponding to a high-rate QC-LDPC code and a second plurality of HARQ lines after the first plurality of lines used to decrease the rate of the high-rate QC-LDPC code;each row of the first and second row plurality of the parity check matrix comprises non-empty entries, each with an integer value, representing a cyclically rotated ZxZ identity matrix or empty entries, each representing a ZxZ submatrix entirely of zeros; at least two columns, wherein two columns (1310, 1312) correspond to two high-degree punched variable nodes of the LDPC base graph; and at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected and at least two rows below the lowest row (1322) of said at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected;and wherein the parity check matrix has row orthogonality between each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two punctured variable nodes of the LDPC base graph are both connected (1504), wherein no column has a non-empty entry in each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected;and characterized by the fact that: the two high-degree punctured variable nodes of the LDPC base graph alternate, from line to line, their respective line connectivity to all lines in the parity check matrix, below said lowest line of said at least one line to which the two high-degree punctured variable nodes of the LDPC base graph are both connected.; 8. A method according to claim 7, characterized in that at least 1 / 2 of all consecutive row pairs of the parity check matrix have row orthogonality.

9. A method according to claim 8, characterized in that at least 1 / 2 of all consecutive row pairs comprises the last 1 / 2 of all rows in the parity check matrix, and wherein the last 1 / 2 of all rows in the parity check matrix corresponds to the HARQ rows.

10. Apparatus for performing quasi-cyclic low-density parity check coding, QC-LDPC, for hybrid automatic repeat request transmission, HARQ, using a rate-compliant QC-LDPC design comprising: one or more processors configured to: obtain information bits of a QC-LDPC codeword from a QC-LDPC code of the rate-compliant QC-LDPC design; and perform coding (706) of the information bits to calculate parity bits of the QC-LDPC codeword according to a parity check matrix (1300) of the QC-LDPC code obtained by surveying an LDPC base graph, wherein the parity check matrix comprises: a first plurality of lines representing a principal portion (1320) corresponding to a high-rate QC-LDPC code and a second plurality of HARQ lines after the first plurality of lines used to decrease the rate of the high-rate QC-LDPC code;each row of the first and second row plurality of the parity check matrix comprises non-empty entries, each with an integer value, representing a cyclically rotated ZxZ identity matrix, or empty entries, each representing a ZxZ submatrix entirely of zeros; at least two columns, wherein two columns (1310, 1312) correspond to two high-degree punched variable nodes of the LDPC base graph; at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected and at least two rows below the lowest row (1322) of said at least one row to which the two high-degree punched variable nodes of the LDPC base graph are both connected;and wherein the parity check matrix has row orthogonality between each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two punctured variable nodes of the LDPC base graph are both connected, wherein no column has a non-empty entry in each pair of consecutive rows that are below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected; and characterized in that: the two high-degree punctured variable nodes of the LDPC base graph alternate, from row to row, their respective row connectivity for all rows in the parity check matrix, below the said lowest row of the said at least one row to which the two high-degree punctured variable nodes of the LDPC base graph are both connected;and one or more memory modules coupled to one or more processors.

11. Apparatus, according to claim 10, characterized in that at least 1 / 2 of all consecutive row pairs of the parity check matrix have row orthogonality. Petition 870250040184, dated 05 / 16 / 2025, p. 20 / 22 8 / 8 12. Apparatus, according to claim 11, characterized in that at least 1 / 2 of all consecutive row pairs comprises the last 1 / 2 of all rows of the parity check matrix and in that the last 1 / 2 of all rows of the parity check matrix corresponds to the HARQ rows. Petition 870250040184, dated 05 / 16 / 2025, p. 21 / 22

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