CONTROLLER AND METHOD FOR GENERATING PULSE WIDTH MODULATION SIGNALS

Abstract

A controller (100) may include a memory with computer-readable instructions stored therein; and a processor configured to execute the computer-readable instructions to generate pulse-width modulation (pwm) signals to control power switches of an active front-end (afe) inverter based on at least one synthesized grid voltage vector angle at a terminal of an alternating current (ac) grid without using physical voltage sensors at the ac grid terminal, and control the afe inverter to supply power to a load (700 or 800) based on the pwm signals.

Description

/ 36 CONTROLLER AND METHOD FOR GENERATING PULSE WIDTH MODULATION SIGNALS Fundamentals of the Invention Field of invention

[001] The example embodiments generally refer to an apparatus configured to detect an angle of a network voltage vector at a terminal of an alternating current (AC) network, to a system and / or to a method of carrying them out. Related Technology

[002] In an Active Front End (AFE) control system, a phase-locked loop (PLL) based control method is often used to detect the angle of a mains voltage vector at an alternating current (AC) terminal based on line-to-line mains voltage information. Conventionally, in order to detect the angle of the mains voltage vector from the AC mains, line-to-line mains voltage information may need to be perceived first using external voltage sensors attached to AC mains terminals. Summary of the Invention

[003] Some example embodiments refer to a controller and / or a method of generating Pulse Width Modulation (PWM) signals for power switches of an Active Front End (AFE) inverter.

[004] In some example embodiments, the controller may include a memory with computer-readable instructions stored therein; and a processor configured to execute the computer-readable instructions to generate the Pulse Width Modulation (PWM) signals to control the power switches of an Active Front End (AFE) inverter based on at least one synthesized grid voltage vector angle at a terminal of an alternating current (AC) network. Petition 870240091041, dated 10 / 24 / 2024, page 9 / 115 / 36 without using physical voltage sensors at the AC network terminal, and controlling the AFE inverter to supply power to a load based on PWM signals. Brief Description of the Drawings

[005] At least some exemplary embodiments will be more fully understood from the detailed description provided below and the accompanying drawings, in which identical elements are represented by identical reference numbers, which are given by way of illustration only and thus are not limiting of the exemplary embodiments, and in which: Figure 1 is a block diagram of a system for controlling a load according to some example modes; Figure 2 illustrates a method for controlling a system based on position detection without a voltage sensor, according to some example embodiments; Figure 3 illustrates a method of operation of a controller to perform position detection without a voltage sensor in a system according to some example embodiments; Figure 4 illustrates a position detection module without a voltage sensor according to some example embodiments; Figure 5 illustrates a method of operation of a position detection module without a voltage sensor according to some example embodiments. Figure 6 illustrates a method for estimating the inverter terminal voltage according to some example configurations; Figure 7 illustrates a block diagram of an inverter terminal voltage vector angle detection module included in a voltage sensorless position detection module according to some example embodiments; Figure 8 illustrates a method for making an estimate of Petition 870240091041, dated 10 / 24 / 2024, p. 10 / 115 / 36 inverter terminal voltage vector angle according to some example embodiments; Figure 9 illustrates a method for estimating the network voltage vector angle according to some example modalities; Figure 10 illustrates a method of generating an initial terminal voltage vector angle according to some example embodiments; Figures 11A to 11C are vector diagrams illustrating current and voltage vectors in a direct quadrature (dq) rotating reference frame according to some example embodiments; and Figure 12 is a circuit diagram illustrating an AFE inverter connected to a load according to some example embodiments. Detailed Description

[006] Some example embodiments will now be described more fully in relation to the attached drawings in which some example embodiments are illustrated.

[007] In this way, although the example embodiments are capable of various modifications and alternative forms, the embodiments shown are shown by way of example in the drawings and will be described here in detail. It should be understood, however, that there is no intention to limit the example embodiments to the particular forms described, but, on the contrary, the example embodiments should cover all modifications, equivalents, and alternatives that fall within the scope of the claims. Equal numbers refer to equal elements throughout the description of the figures.

[008] It will be understood that, although the terms first, second, etc. These terms can be used here to describe various elements; these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element Petition 870240091041, dated 10 / 24 / 2024, page 11 / 115 / 36 can be called a second element, and, similarly, a second element can be called a first element, without departing from the scope of the example modalities. As used here, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[009] It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar way (e.g., “between” compared to “directly between”, “adjacent” compared to “directly adjacent”, etc.).

[0010] The terminology used here is for the purpose of describing particular modalities only, and is not intended to be limiting of the modalities exemplified. As used here, the singular forms “a”, “an”, “the” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and / or “including”, when used here, specify the presence of declared resources, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other resources, integers, steps, operations, elements, components and / or groups thereof.

[0011] It should also be noted that, in some alternative implementations, the functions / acts noted may occur out of the order shown in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently or may, at times, Petition 870240091041, dated 10 / 24 / 2024, page 12 / 115 / 36 to be executed in reverse order, depending on the functionality / acts involved.

[0012] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning commonly understood by those skilled in the art to which the exemplary embodiments pertain. It will be further understood that terms, for example, those defined in commonly used dictionaries, are to be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0013] Parts of example embodiments and the corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of the operation on the data bits in a computer memory. These descriptions and representations are those by which those skilled in the art effectively convey the substance of their work to others skilled in the art. An algorithm, as the term is used here, and as it is used in general, is conceived as a self-consistent sequence of steps leading to a result. The steps are those that require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated.It has sometimes proven convenient, mainly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or similar terms.

[0014] In the following description, illustrative modalities will be described in relation to acts and symbolic representations of operations (for example, in the form of flowcharts) that can be implemented as program modules or functional processes that include routines, Petition 870240091041, dated 10 / 24 / 2024, page 13 / 115 / 36 programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and can be implemented using existing hardware. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific integrated circuits, field-programmable gate arrays (FPGAs), computers, or similar devices.

[0015] It should be kept in mind, however, that all these terms and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as becomes apparent from the discussion, terms such as “processing” or “computation” or “calculation” or “determination” or “display” or similar terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as electronic physical quantities in the computer system's records and memories into other data similarly represented as physical quantities in the memories or records of the computer system or other such information storage, transmission or display devices.

[0016] In this application, including the definitions that follow, the term 'module' or the term 'controller' may be replaced with the term 'circuit.' The term 'module' may refer to, be part of, or include the processor hardware (shared, dedicated, or group) that executes the code and the memory hardware (shared, dedicated, or group) that stores the code executed by the processor hardware.

[0017] The module may include one or more interface circuits. In some examples, the interface circuits may include wired or wireless interfaces that are connected to a local area network (LAN), the Internet, Petition 870240091041, dated 10 / 24 / 2024, page 14 / 115 / 36 in a wide area network (WAN) or combinations thereof. The functionality of any given module of the present description may be distributed among multiple modules that are connected via interface circuits. For example, multiple modules may enable load balancing. In a further example, a server module (also known as remote, or cloud) may perform some functionality on behalf of a client module.

[0018] Additionally, at least one embodiment of the invention relates to a non-transient computer-readable storage medium comprising electronically readable control information stored thereon, configured in such a way that, when the storage medium is used in a magnetic resonance imaging device controller, at least one embodiment of the method is realized.

[0019] Furthermore, any of the aforementioned methods may be incorporated in the form of a program. The program may be stored on non-transient computer-readable media and is adapted to perform any of the aforementioned methods when executed on a computer device (a device that includes a processor). Thus, the non-transient tangible computer-readable media is adapted to store the information and is adapted to interact with a data processing facility or a computer device to execute the program of any of the aforementioned embodiments and / or to perform the method of any of the aforementioned embodiments.

[0020] Computer-readable media or storage media may be embedded media installed inside a main body of the computer device or removable media arranged so that it can be separated from the main body of the computer device. The term computer-readable media, as used herein, does not encompass signals Petition 870240091041, dated 10 / 24 / 2024, page 15 / 115 / 36 transient electrical or electromagnetic waves that propagate through a medium (such as in a carrier wave); the term computer-readable media is therefore considered tangible and non-transient. Non-limiting examples of non-transient computer-readable media include, but are not limited to, rewritable non-volatile memory devices (including, for example, flash memory devices, erasable programmable read-only memory devices, or mask read-only memory devices); volatile memory devices (including, for example, static random-access memory devices or dynamic random-access memory devices); magnetic storage media (including, for example, an analog or digital magnetic tape or a hard disk drive); and optical storage media (including, for example, a CD, a DVD, or a Blu-ray disc).Examples of media with embedded rewritable non-volatile memory include, but are not limited to, memory cards; and media with embedded ROM, including, but are not limited to, ROM cassettes; etc. Furthermore, various information relating to the stored images, for example, property information, may be stored in other forms, or may be provided in other ways.

[0021] The term code, as used previously, may include software, embedded software, and / or microcode, and may refer to programs, routines, functions, classes, data structures, and / or objects. Shared processor hardware encompasses a single microprocessor that executes some or all of the code from multiple modules. Grouped processor hardware encompasses a microprocessor that, in combination with additional microprocessors, executes some or all of the code from one or more modules. References to multiple microprocessors encompass multiple microprocessors on chips. Petition 870240091041, dated 10 / 24 / 2024, page 16 / 115 / 36 discrete, multiple microprocessors on a single chip, multiple cores of a single microprocessor, multiple threads of a single microprocessor, or a combination of the above.

[0022] Shared memory hardware encompasses a single memory device that stores some or all of the code from multiple modules. Group memory hardware encompasses a memory device that, in combination with other memory devices, stores some or all of the code from one or more modules.

[0023] The term memory hardware is a subset of the term computer-readable media. The term computer-readable media, as used here, does not encompass transient electrical or electromagnetic signals propagating through a medium (such as in a carrier wave); the term computer-readable media is therefore considered tangible and not transient.Non-transient, but not limited to, computer-readable media include rewritable non-volatile memory devices (including, for example, flash memory devices, erasable programmable read-only memory devices, or mask read-only memory devices); volatile memory devices (including, for example, static random-access memory devices or dynamic random-access memory devices); magnetic storage media (including, for example, an analog or digital magnetic tape or a hard disk drive); and optical storage media (including, for example, a CD, a DVD, or a Blu-ray disc). Examples of media with embedded rewritable non-volatile memory include, but are not limited to, memory cards; and media with embedded ROM, including, but are not limited to, ROM cassettes; etc.Furthermore, various pieces of information regarding the stored images, such as ownership information, may be available. Petition 870240091041, dated 10 / 24 / 2024, page 17 / 115 / 36 to be stored in any other form, or they may be provided in other ways.

[0024] The transmission medium may comprise twisted pairs of wires, coaxial cable, optical fiber, or some other suitable transmission medium known by technology.

[0025] The example modalities may have different forms and / or be combined, and should not be interpreted as being limited to the descriptions presented here.

[0026] In one or more example embodiments, a data processing system can estimate line-to-line input voltage information from the grid directly from the AFE inverter terminals during an inverter self-sensing mode by estimating the inverter terminal voltage (e.g., voltage drops across the inverter switches and diodes) based on the inverter gate drive signals, and subsequently by estimating the angle of the composite voltage vector, which is constructed from the three-phase inverter terminal voltages, using the PLL-based position sensing method.

[0027] To precisely control the power factor of the AFE system at a grid input voltage terminal, the data processing system can compensate for a voltage drop across the impedance between the grid input voltage terminal and the AFE inverter terminals by converting the estimated inverter voltage vector angle from the inverter terminal voltages to the grid voltage vector angle corresponding to the voltage at the grid input terminals.

[0028] Figure 1 is a block diagram of a system for controlling a load according to some example embodiments, and Figure 2 illustrates a method of controlling the system according to some example embodiments.

[0029] With regard to figures 1 and 2, a 1000 system may include a Petition 870240091041, dated 10 / 24 / 2024, page 18 / 115 / 36 data processing system 100, such as a controller, an alternating current (AC) transformer 200 and an inductor resistor (LR) line filter 300 connected to an alternating current (AC) power grid 400, an active front-end (AFE) inverter 500, and an AFE load 800. In some example embodiments, the AFE load 800 may include an inverter 600, and a load 700, such as an internal permanent magnet (IPM) motor.

[0030] The data processing system 100 may be, but is not limited to, a processor, a central processing unit (CPU), a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, or any other device capable of performing operations in a defined manner. In one example embodiment, the data processing system 100 may include a processor and memory to support the storage, processing, and execution of software instructions from one or more software modules.

[0031] In the manner discussed below, the data processing system 100 can control the AFE 500 inverter based on the signals received from the AFE 500 inverter.

[0032] In some example embodiments, the processor of the data processing system 100 can generate Pulse Width Modulation (PWM) signals to control the power switches of an Active Front End (AFE) inverter based on at least one synthesized grid voltage vector angle at a terminal of an alternating current (AC) grid without using physical voltage sensors at the AC grid terminal, and control the AFE inverter to supply power to a load based on the PWM signals. Petition 870240091041, dated 10 / 24 / 2024, page 19 / 115 / 36

[0033] In some example embodiments, the processor can generate the PWM signals by estimating the synthesized mains voltage vector angle at the AC mains terminal without using physical voltage sensors.

[0034] In some example embodiments, the processor is configured to generate the PWM signals by converting the measured current from a three-phase current measured on a stationary reference frame to a direct quadrature axis current (dq) measured on a rotating dq reference frame, by generating a q-axis current reference based on an AC network terminal reference power factor, by generating a d-axis current reference based on an actual DC bus voltage and a reference DC bus voltage, the actual DC bus voltage being connected to a load, the d-axis current reference and the q-axis current reference forming a dq-axis current reference, by generating the dq-axis reference voltages based on the dq-axis current measured on the rotating dq reference frame and the dq-axis current reference,and by generating the three-phase gate drive signals for the AFE inverter by converting the dq-axis reference voltages based on the synthesized grid voltage vector angle, the three-phase gate drive signals being the PWM signals.

[0035] In some example embodiments, the processor is configured to generate the PWM signals in such a way that the AFE inverter maintains a real DC bus voltage connected to the load.

[0036] In some example embodiments, the processor is configured to make an estimate of the synthesized grid voltage vector angle by making an estimate of an AFE inverter terminal voltage when the inverter is enabled, the AFE inverter terminal voltage being a voltage from an AFE inverter terminal, making a Petition 870240091041, dated 10 / 24 / 2024, page 20 / 115 / 36 estimation of a first AFE inverter terminal voltage vector angle when the AFE inverter is disabled, the first AFE inverter terminal voltage vector angle being an angle associated with a voltage vector from the AFE inverter terminal at an initial time, by determining a second AFE inverter terminal voltage vector angle when the AFE inverter is enabled, the second AFE inverter terminal voltage vector angle being an angle associated with a voltage vector from the AFE inverter terminal at a second time subsequent to the initial time, and by making an estimate of the synthesized grid voltage vector angle based on the second AFE inverter terminal voltage vector angle, the synthesized grid voltage vector angle being an angle associated with a voltage vector from the AC grid terminal.

[0037] In some example embodiments, if the inverter is enabled, the processor is configured to make an estimate of the AFE inverter terminal voltage by making an estimate of the three-phase line-to-neutral voltages at the AFE inverter terminal based on status signals associated with the AFE inverter power switches and corresponding voltage drops across the power switches.

[0038] In some example embodiments, the processor is configured to make an estimate of the three-phase line-to-neutral voltages by examining the collector-emitter voltages associated with each of the AFE inverter's power switches.

[0039] In some example embodiments, if the inverter is disabled, the processor is configured to make an estimate of the first AFE inverter terminal voltage vector angle by detecting the zero-crossing instants when the AFE inverter terminal voltage passes through zero, by calculating an AFE inverter terminal voltage vector angular frequency based on the zero-crossing instants, the AFE inverter terminal voltage vector angular frequency Petition 870240091041, dated 10 / 24 / 2024, page 21 / 115 / 36, being an angular frequency in rad / s of the AFE inverter terminal voltage, and by calculating the first AFE inverter terminal voltage vector angle based on the AFE inverter terminal voltage vector angular frequency and a corresponding AFE inverter terminal voltage vector position at one of the most recent zero-crossing instants.

[0040] In some example embodiments, the processor is configured to make an estimate of the second AFE inverter terminal voltage vector angle by initializing a phase-locking loop (PLL) using the first AFE inverter terminal voltage vector angle when the inverter is disabled, and by executing the phase-locking loop (PLL) using the three-phase line-to-neutral voltages of the AFE inverter terminal when the inverter is enabled.

[0041] In some example embodiments, the processor is configured to make an estimate of the second AFE inverter terminal voltage vector angle by executing the PLL to align the second AFE inverter terminal voltage vector angle with an axis d of a rotating reference frame dq.

[0042] In some example embodiments, when the AFE inverter is enabled, the processor is configured to make an estimate of the second AFE inverter terminal voltage vector angle by executing the PLL to continuously calculate a position error between the second AFE inverter terminal voltage vector angle and the d-axis, calculate an angular frequency of the second AFE inverter terminal voltage vector angle by using a PI controller to regulate the position error, and calculate the second AFE inverter terminal voltage vector angle by integrating the angular frequency.

[0043] In some example embodiments, the processor is configured to make an estimate of the network voltage vector angle. Petition 870240091041, dated 10 / 24 / 2024, page 22 / 115 / 36 AC is achieved by compensating for a phase change due to a voltage drop through a filter between the AFE inverter terminal and the AC grid terminal.

[0044] In some example embodiments, the filter is one of an LCL line filter and an LR line filter.

[0045] In some example embodiments, the processor is configured to convert the measured current from the measured three-phase current to the measured dq-axis current based on the synthesized grid voltage vector angle.

[0046] In some example embodiments, the processor is configured to generate the d-axis current reference by comparing the actual DC bus voltage and the reference DC bus voltage, and by generating the d-axis current reference using a PI controller.

[0047] In some example embodiments, the processor is configured to generate the q-axis current reference based on the AC mains terminal reference power factor and the d-axis current reference.

[0048] In some example embodiments, the processor is configured to generate the dq-axis reference voltages by generating a comparison signal based on a result of comparing the d-axis current reference of the q-axis current reference with a measured d-axis value of the dq-axis current and a measured q-axis value of the dq-axis current, respectively, and by generating the dq-axis reference voltages based on the comparison signal.

[0049] In some example embodiments, the processor is configured to refine the synthesized grid voltage vector angle by compensating for a time delay associated with digital processing to generate a refined synthesized grid voltage vector angle; and generate Petition 870240091041, dated 10 / 24 / 2024, page 23 / 115 / 36 the three-phase gate drive signals for the AFE inverter based on the dq axis reference voltages and the refined synthesized grid voltage vector angle, wherein the three-phase gate drive signals are transmitted to the AFE inverter to switch a plurality of half-bridges included in the AFE inverter's power switches.

[0050] The data processing system 100 may include a voltage-less position detection module 110, an abc / dq Transformation Module 120, a PI controller 130, a reactive power control module 140, a current regulation controller 150, and a PWM generation module 160. The voltage-less position detection module 110 is shown in more detail in Figure 4.

[0051] In the manner discussed below, the data processing system 100 can estimate a grid voltage vector angle θg without using the physical voltage sensors attached to the AC grid terminals 400, generate Pulse Width Modulation (PWM) signals to control the AFE inverter power switches 500 based on the estimated grid voltage vector angle θg, and operate the load 800 based on the PWM signals.

[0052] Regarding Figure 2, in operation S100, the AC network 400 can supply or consume AC power to maintain a stable DC bus voltage Vdc on a DC bus. The DC bus electrically connects the AFE 500 inverter and the load inverter 600. The DC bus can be modeled as a capacitor that consumes electrical power from the AC network 400 and supplies electrical power to the load 800. For example, the AC network 400 can supply power to the AFE 500 inverter when the DC bus voltage Vdc is lower than the reference DC bus voltage V*dc because the load 700 draws more power from the DC bus than the AFE 500 inverter can supply. The AC network 400 can also consume AC power when the voltage of Petition 870240091041, dated 10 / 24 / 2024, page 24 / 115 / 36 DC bus Vdc is greater than the reference DC bus voltage V*dc due to load 700, which is operating as a generator, supplying more power to the DC bus.

[0053] In the S200 operation, the 200 three-phase AC transformer can convert between high and low three-phase AC voltage.

[0054] In S300 operation, the LR 300 line filter can eliminate current harmonics on the lines by filtering. For example, the LR 300 line filter can be a pre-designed LR filter. The LR 300 line filter can be incorporated as long cables connected between the AFE 500 inverter and the 200 three-phase AC transformer, the length of which is determined based on the current harmonics on the lines.

[0055] In other example embodiments, system 1000 may include an inductor-capacitor-inductor style filter or LCL filter (not shown) between the AFE inverter 500 and the three-phase AC transformer 200, instead of the LR filter 300, such that the data processing system 100 is configured to compensate for a phase shift due to a voltage drop across the LCL filter (not shown).

[0056] In S400 operation, the data processing system 100 can estimate the grid voltage vector angle θg, generate Pulse Width Modulation (PWM) signals to control the AFE 500 inverter power switches based on the estimated grid voltage vector angle 0g. The S400 operation is discussed in more detail below in relation to the sub-operations illustrated in Figure 4.

[0057] For example, the voltage-sensing position module 110 can estimate the network voltage vector angle 0g defined as the d-axis orientation of the rotating dq-axis frame without using physical voltage sensors attached to the AC network terminals 400. Subsequently, the data processing system 100 can generate Pulse Width Modulation (PWM) signals to control the power switches of Petition 870240091041, dated 10 / 24 / 2024, page 25 / 115 / 36 AFE 500 inverter based on the estimated grid voltage vector angle θg·

[0058] The details of the operation of the data processing system 100 which includes the estimation of the network voltage vector angle 0g by the voltage sensorless position detection module 110 and the generation of PWM signals based on the same will be discussed below in relation to figures 3 to 11.

[0059] In S500 operation, the AFE 500 inverter can supply / consume power to / from the AC 400 grid to regulate the DC bus voltage. For example, the AFE 500 inverter can consume power from the AC 400 grid when the DC bus voltage is less than the reference DC bus voltage V*dc. Alternatively, the AFE 500 inverter can supply power back to the AC 400 grid when the DC bus voltage is greater than the reference DC bus voltage V*dc.

[0060] The AFE 500 inverter may include power electronics components, such as switching semiconductors, to generate, modify and / or control PWM signals or other alternating current signals (e.g., pulse, square wave, sine wave, or other waveforms) applied to the DC bus to operate the 800 load.

[0061] In S600 operation, inverter 600 can supply / consume electrical power to / from load 700. For example, inverter 600 can supply electrical power to load 700. In this case, inverter 600 draws power from the DC bus. Alternatively, inverter 600 can also consume mechanical power from load 700 when load 700 is operating as a generator. In this case, inverter 600 supplies electrical power to the DC bus.

[0062] The 600 inverter may include power electronics components such as switching semiconductors to generate, modify and Petition 870240091041, dated 10 / 24 / 2024, page 26 / 115 / 36 to control pulse-width modulated signals or other alternating current signals (e.g., pulse, square wave, sine wave, or other waveforms) applied to load 700. A separate PWM generation module provides driver stage inputs to inverter 600. An output stage of inverter 600 provides the pulse-width modulated voltage waveform or other voltage signal to control load 700. In one example embodiment, inverter 600 is powered by direct current (DC) Vdc voltage from the bus.

[0063] In S700 operation, load 700 can consume power from inverter 600. In this case, inverter 600 consumes power from the DC bus. Alternatively, load 700 can also supply power to inverter 600, and inverter 600 can supply power back to the DC bus when load 700 operates as a generator.

[0064] Figure 3 illustrates a method of operation of a controller to perform position detection without a voltage sensor in a system according to some example embodiments.

[0065] With regard to figures 1 to 3, in the S400 operation illustrated in figure 2, the data processing system 100 can estimate the grid voltage vector angle θg and generate Pulse Width Modulation (PWM) signals to control the AFE 500 inverter power switches based on the estimated grid voltage vector angle θg by performing operations S110 to S160, discussed below.

[0066] In S110 operation, the voltage-sensing position detection module 110 can receive power switch state information from the AFE 500 inverter when inverter switching is enabled, receive zero-crossing signals of the detected phase voltage from the AFE 500 inverter when inverter switching is disabled, and estimate the grid voltage vector angle θg defined as a Petition 870240091041, dated 10 / 24 / 2024, page 27 / 115 / 36 orientation of the d-axis of the rotary dq axis based on the same without using the physical strain gauges attached to the AC 400 network terminals. Therefore, the bulky and expensive external strain gauges can be removed from the AFE control system. Operation S110 will be discussed in more detail below in relation to figures 4 to 11.

[0067] In S120 operation, the abc / dq 120 Transformation Module can receive the three-phase network currents Ic, Ib, Ia and perform the Clarke / Park (abc-to-dq) transformation based on the estimated network voltage vector angle θg to convert the three-phase network currents into the q-axis current Iq and the d-axis current Id on the rotating reference frame dq.

[0068] The dq shaft current may refer to the direct shaft current and the quadrature shaft current in the dq rotating reference frame as applicable in the context of vector-controlled alternating current machines, such as the 700 load.

[0069] The abc / dq 120 Transformation Module can apply a Clarke transformation and a Park transformation or other conversion equations (for example, certain conversion equations that are suitable and known to those skilled in the art) to convert the measured three-phase representations of the current into two-phase representations of the current based on the current data Ia, Ib, and Ice at the estimated network voltage vector angle θg.

[0070] In the S130 operation, the PI 130 controller can receive a difference between the measured DC bus voltage Vdc and a reference DC bus voltage V*dc, and can generate the d-axis reference current I*d based on the difference between the detected DC bus voltage Vdc and the reference DC bus voltage V*dc. The PI controller is a closed-loop proportional-integral controller used to track the measured DC bus voltage Vdc to the reference DC bus voltage V*dc. Petition 870240091041, dated 10 / 24 / 2024, page 28 / 115 / 36

[0071] In operation S140, the reactive power control module 140 can generate the q-axis reference current I*q based on a reference power factor PF* received from a high-level system control unit (not shown). The reference power factor PF* can be empirically determined for the 1000 system based on the users' system control requirements. The q-axis reference current I*q is generated to ensure that the 1000 system is meeting the requirement at the reference power factor PF* with the d-axis reference current I*d determined from operation S140.

[0072] In S150 operation, the 150 current regulation controller can use the d-axis reference current I*de and the q-axis reference current I*q as reference currents to generate the dq-axis reference voltage V*de V*q. For example, the 150 current regulation controller can receive the difference between Iqe and I*q, and the difference between Id and I*d, and can generate the dq-axis reference voltage V*de V*q from them. The 150 current regulation controller can include two closed-loop PI controllers together with a cross-coupled dq-axis decoupling module to track the d-axis current Id and the q-axis current Iq relative to their respective references Id* and Iq*. The outputs of the d-axis current regulator and the q-axis current regulator are the d-axis reference voltage V*de and the q-axis reference voltage V*q.

[0073] In the S160 operation, the PWM generation module 160 can receive the dq-axis reference voltage V*de V*q on the rotating reference frame dq from the current regulation controller 150, and convert the dq-axis reference voltage V*de V*q on the rotating reference frame dq * V for an axis tension command ααe an axis tension command β * Vβμna stationary frame α-β based on the tension vector angle of * , . ,Λ, V estimated network θge, then converts the axis tension command ααe o Petition 870240091041, dated 10 / 24 / 2024, page 29 / 115 / 36 * ....... v^ , .......· βρ axis voltage command of two-phase data representations into three-phase data representations (e.g., three-phase representations such as PWM function A, function B, and function C for three phases). The PWM 160 generation module can generate the three-phase power switch gate signals for drive control of the AFE 500 inverter power switch gates based on the three-phase PWM function representations.

[0074] In other example embodiments, the PWM 160 generation module can further process the estimated grid voltage vector angle θg to generate a refined estimated grid voltage vector angle 0g' by extrapolating the estimated grid voltage vector angle θg over one and a half control periods using the frequency generated in PLL to compensate for a delay associated with digital processing. Subsequently, the PWM 160 generation module can use the refined estimated grid voltage vector angle 0g' to convert the dq axis reference voltage *V* to the α-β voltage commands on the α-β reference frame.

[0075] Figure 4 illustrates a voltage-less position detection module according to some example embodiments, and Figure 5 illustrates a method of operation of a voltage-less position detection module according to some example embodiments.

[0076] With regard to figures 4 and 5, the voltage sensorless position detection module 110 may include an inverter terminal voltage estimation module 112, an inverter terminal voltage vector angle detection module 114, a grid voltage vector angle estimation module 116, and an initial grid voltage vector angle detection module 118.

[0077] In the S110 operation illustrated in figure 3, the detection module Petition 870240091041, dated 10 / 24 / 2024, page 30 / 115 / 36 of position without voltage sensor 110 of the data processing system 100 can estimate the network voltage vector angle θg, by performing operations S112 to S118 illustrated in figure 5, in the manner discussed below.

[0078] In the S112 operation, the inverter terminal voltage estimation module 112 can estimate the inverter terminal voltages Van, Vbn, and Vcn based on power switch state information (or alternatively, On / Off state signals) and a diode voltage drop across the AFE 500 inverter power switches. The S112 operation will be discussed in more detail below in relation to Figure 6.

[0079] In the S114 operation, the inverter terminal voltage vector angle detection module 114 can generate the inverter terminal voltage vector angle θi based on the inverter terminal voltages Van, Vbn, and Vcn received from the inverter terminal voltage estimation module 112 and the initial inverter voltage vector angle θi_init. The inverter terminal voltage vector angle detection module 114 can include a Proportional and Integration (PI) controller (see Figure 7) to regulate the position error to force the q-axis voltage Vq on the rotating reference frame dq to 0, such that the output of the PI controller is the inverter terminal voltage vector angle frequency ω. The S114 operation will be discussed in more detail below in relation to Figures 7 and 8.

[0080] In operation S116, the grid voltage vector angle estimation module 116 can estimate the grid voltage vector angle θgs without using physical voltage sensors based on the inverter terminal voltage vector angle θi received from the inverter terminal voltage vector angle detection module 114. Operation S116 will be discussed in more detail below in relation to Figure 9.

[0081] As discussed previously, the network voltage vector angle estimation module 116 can provide the vector angle of Petition 870240091041, dated 10 / 24 / 2024, page 31 / 115 / 36 estimated network voltage θg for the abc / dq 120 Transformation Module, and the abc / dq 120 Transformation Module can use the estimated network voltage vector angle θg to perform abc to dq transformation on the three-phase network currents Ia, Ib and Ic to convert the three-phase network currents Ia, Ib and Ic into the q-axis current Iq and the d-axis current Id on the rotating reference frame dq.

[0082] In operation S118, the initial grid voltage vector angle detection module 118 can receive the zero-crossing signals of the phase voltage from the AFE 500 inverter, and can generate an initial inverter voltage vector angle fyjnit to initialize the phase-locked loop (PLL) controller in the inverter terminal voltage phase angle detection module 114. Therefore, the PLL controller can start with the correct initial inverter terminal voltage vector angle θi_init. In the inverter terminal voltage vector angle detection module 114, the PLL controller is used to detect the inverter terminal voltage vector angle θi. Operation S118 will be discussed in more detail below in relation to Figure 10.

[0083] Figure 6 illustrates a method for estimating the inverter terminal voltage according to some example embodiments, and Figure 12 is a circuit diagram illustrating an AFE inverter connected to a load according to some example embodiments.

[0084] With regard to figures 1 to 6 and 12, in operation S112-1, the inverter 112 terminal voltage estimation module can determine the direction of the phase current based on the power switch state information. As an example, the direction of phase A current is defined as positive (+Ia) when the top switching of phase A (see figure 12) is on.

[0085] In the S112-2 operation, the inverter 112 terminal voltage estimation module can calculate the instantaneous phase voltage VaNVbNe Petition 870240091041, dated 10 / 24 / 2024, page 32 / 115 / 36 VcN using the following equations.

[0086] If the phase current Ix (subscript 'X' represents phase a, b, or c) is positive (the case illustrated in Figure 12), the following instantaneous values ​​Vxn (subscript 'X' represents phase a, b, or c) can be calculated: Vxn = (Vdc - Vigbt) = Top switch on OR VXN = (Vdc + Vigbt) = Base switch off Eq. 1

[0087] If the phase current Ix is negative, the following instantaneous values ​​VXN can be calculated: VXN = (Vdc + Vigbt) = Base switch off OR VXN = (Vdiode) = Base switch on Eq. 2

[0088] In operation S112-3, the inverter terminal voltage estimation module 112 can calculate the line-to-line voltage Vab between terminal a and terminal b of the AFE 500 inverter and Vca between terminal ce and terminal a of the AFE 500 inverter using the following equations: V, =V -Eyab ^aNybN Eq. 3

[0089] The voltage VXN (subscript 'X' represents phase a, b or c) in equation 3 between the AFE inverter terminal X and a negative rail of the DC bus is estimated by examining the collector-to-emitter voltages of the inverter power switch.

[0090] However, the line-to-line voltages Vabe Vcasão are only one example of line-to-line voltages, and the inverter terminal voltage estimation module 112 can calculate other line-to-line voltages between various terminals of the AFE 500 inverter.

[0091] In the S112-4 operation, the inverter 112 terminal voltage estimation module can calculate the line voltage to neutral Van, Vbn and Petition 870240091041, dated 10 / 24 / 2024, page 33 / 115 / 36 Vcn using the following equations: Van -V) ca

[0092] V cn Therefore, - 3(2Vab + Va. ) jC- + 2VCa ) Eq. 4: The inverter voltage vector angle θi can be estimated in S114 operation using the line-to-neutral voltage VanVbn and Vcn. Therefore, in one or more example embodiments, the 1000 system can detect the inverter terminal voltages VanVbn and Vcn without using physical voltage sensors at the AC network terminals 400.

[0093] Figure 7 illustrates a block diagram of a module for detecting the inverter terminal voltage vector angle 114, and Figure 8 illustrates a method for estimating the inverter terminal voltage vector angle according to some example embodiments.

[0094] With regard to figures 1 to 5, 7 and 8, in operation S114-1, the inverter terminal voltage vector angle detection module 114 can calculate the d-axis voltage Vd and the q-axis voltage Vq on the rotating dq reference frame based on the line-to-neutral voltage of the inverter terminal Van, Vbn, Vcn and using the Park inverter terminal voltage vector angle transformation Oi in the following equation: Va Van -2(k -v )3bn cn (K -K ) V bn cn /

[0095] Vd= Va · cos(^) + Vβ · sin(^) Vq = Vβ · cos(θ1) - Va · sin(^) Eq. 5 In the S114-2 operation, the inverter 114's terminal voltage vector angle detection module can calculate a position error Δθi. Petition 870240091041, dated 10 / 24 / 2024, page 34 / 115 The 27 / 36 inverter terminal voltage vector angle detection module 114 can calculate the position error ΔΘ using the following equation: = atan(^A0i ) Eq. 6

[0096] In SI 14-3 operation, the inverter 114 terminal voltage vector angle detection module calculates the phase angular frequency ω based on the position error Δθμ

[0097] For example, the inverter 114 terminal voltage vector angle detection module can use a PI controller to regulate the position error AOi to force the q-axis voltage Vqem 0, which means that the d-axis in the rotating dq reference frame will be forced to align with the grid voltage vector, then the output of the PI controller is the angular frequency of the grid voltage vector ω.

[0098] In SI 14-4 operation, the inverter 114 terminal voltage vector angle detection module can use the following equation to calculate the 0i angle of the inverter us voltage vector: Θί I * dt + θι ínit Eq. 7

[0099] Subsequently, the inverter 114 terminal voltage vector angle detection module can resume to SI 14-1 operation, and recalculate the d-axis voltage Vd and the q-axis voltage Vq in such a way that SI 14-1 to SI 14-4 operations are performed iteratively in a phase-locked loop (PLL) to achieve convergence.

[00100] SI operations 14-1 to SI 14-4 are illustrated in Figure 7 in the form of a block diagram.

[00101] Figure 9 illustrates a method for estimating the network voltage vector angle 0g according to some example embodiments. Figures 11A to 11C are vector diagrams illustrating current and voltage vectors in the rotating reference frame dq according to Petition 870240091041, dated 10 / 24 / 2024, p. 35 / 115 / 36 some example modalities.

[00102] Regarding figures 11A to 11C, in figures 11A to 11C, Δν is a voltage vector difference between an inverter terminal voltage vector (use an AFE 500 inverter terminal) and the grid voltage vector Ug at an AC 400 grid terminal, that is, Δν = Us - Ug. The angle β is an angle between a q-axis voltage vector Vq and the voltage vector difference Δν; the angle α is an angle between a d-axis voltage vector V and a jωLis vector. In figures 11A to 11C, the angles α and β are used as intermediate calculation angles to calculate an adjusted angle θ representing the difference between θi and 0g, and the angle ψ is a power factor angle. The angles Ψ, β and α are defined as follows: ψ = cos-1(| PF* |) α =--ψ 2 <= β <=π

[00103] Since 0 <= |PF*| <= 1, λ π =< ψ <= — 2 Eq. 8 Eq. 9

[00104] In Figure 11A, since the absolute value of the reference power factor PF* is 1, the AFE 500 inverter supplies / consumes power to / from the AC 400 grid at a unity reference power factor PF*. In graph A1, the AFE 500 inverter supplies power to the AC 400 grid. In graph A2, the AFE 500 inverter consumes power from the AC 400 grid. In both cases, the power factor angle ψ equals 0 (Is > 0 and Is < 0) and the angle α is: π π . π α = — - ψ = — - 0 = — 2 2 Eq. 10

[00105] In the following equations, R and L are the resistance and inductance values ​​of the LR 300 line filter, respectively; I is the magnitude Petition 870240091041, dated 10 / 24 / 2024, page 36 / 115 29 / 36 signaled from a reference vector of the phase current of the AFE inverter is. Is -Sigul( / ·) when=θ Eq. 11 Γ in quedé is the d-axis current reference generated from Γ of the PI controller 130 and eqé is the q-axis current reference generated from the reactive power control module 140.

[00106] From graph Al, when (Is> 0 & | PF*| = 1), P, Va and Vq can be calculated using the following equations: β = tan_1(Ã / &£) Vd= ug+Is-R = ug+Av-sin(^) = ug+ sin( / ?)·β·^Ρ2+(ω·L)2 XL U · i

[00107] From graph A2, when (Is< 0 & | PF*\ = 1), Va and Vq can be calculated using the following equations: β = tan⁻¹(Ã / ω / β) Vd= Us+1 IsI R = ug- Δν si η I / / 1 = ug- sin( / ?)· | Is| Jã2+ (®-i)2= us+sio^-Is-FF(FF Vg= -ω-L-1 Is|= -Δν · cos(^) = -cos(^)· | Is| •^R2+(a>-L)2= cos(^) ·Is^R2+(a>-L)2Eqj3

[00108] In Figure 11B, the AFE 500 inverter supplies power to the AC 400 grid at a non-unitary reference power factor PF*. In graph B1, the reference power factor PF* is greater than 0, and the inverter current vector is leads the grid voltage vector ug. In graph B2, the reference power factor PF* is less than 0, and the grid voltage vector ug leads the inverter current vector is.

[00109] From graph Bl, when (Is> 0 & PF* > 0), P, Vd and Vq Petition 870240091041, dated 10 / 24 / 2024, pages 37 / 115 / 36 can be calculated using the following equations: β = (π / 2 - α) - tan-1( R / oL) = ψ - tan-1( R / oL) Vd= ug- Δν· sin(β) = ug-sin(e)·Is·7R2+ (o·L)2 Vq = Δν · cos(β) = cos(β) · Is· 7R2+ (o· L)2 Eq. 14

[00110] From graph B2, when (Is > 0 & PF* < 0), β, V and Vq can be calculated using the following equations: β = (π / 2 - α) + tan-1(R / oL) = ψ + tan-1(R / oL) Vd= ug+ Δν·sin(β) = ug+ sin(β) ·Is·R2+ (o·L)2 Vq= Δν·cos(^) = cos(β)·Is·7R2+ (o·L)2 Eq. 15

[00111] In Figure 11C, the AFE 500 inverter consumes power from the AC 400 grid at a non-unitary reference power factor PF*. In graph C1, the reference power factor PF* is greater than 0, and the reversed inverter current vector is drives the grid voltage vector ug. In graph C2, the reference power factor PF* is less than 0, and the grid voltage vector Ug drives the reversed inverter current vector is.

[00112] From graph C1, when (Is < 0 & PF* > 0), Vd and Vq can be calculated using the following equations: β = (π / 2 - α) - tan-1( R / oL) = ψ - tan-1( R / oL) Vd= ug+ Δν·sin(β) = ug+ sin(β) |Is|·R2+ (o·L)2= ug-sin(β) ·Is·7R2+ (o·L)2 Vq = -Δν·cos(β) = -cos(β) |Is |·VR2+ (o·L)2= cos(β)·Is·7R2+ (o·L)2 Eq. 16

[00113] From graph C2, when (Is < 0 & PF* < 0), Vde Vq can be calculated using the following equations: Petition 870240091041, dated 10 / 24 / 2024, p. 38 / 115 31 / 36 β = (π / 2 - cr) + tan \RIojL) = y / + tan \R / (oL) Vd=ug-^vsin(^) = ug-sin(^)· | Is| -^ + 01)2= ug+ sin( / 7)·Is·^R2+ (ω· L)2 Vq= -Δν · cos(^) = -cos(^)· | Is| -^ + (ω·Σγ ​​​​= cos(^)·Is·^R2+ (ú)-L)2EqJ7

[00114] As discussed in more detail below in relation to Figure 9, based on the analysis presented for all cases in Figures 11A to 11C, the network voltage vector angle estimation module 116 can select different equations from the following equations to calculate the adjusted angle Θ from the AFE 500 inverter terminal to the AC 400 network terminal: ψ = cos⁻¹(|PF*|) β - ψ - tan⁻¹(α) when 1 > PF* >= 0 β = ψ + ^11^ when jPF* |= 1 or PF* < 0 = ií? — SÍn(^) X 7$ X when 1 > PF >= 0 = ffg + siu(^) x 7$ x ^7? + (^97) . when |AF=lorPf < 0 Θ = -tairh-—when Λ >= 0 V í?= tan-1(—). when js< Q L Eq. 18

[00115] Therefore, the compensated position that considers the phase change between the inverter terminal voltage vector angle 0i and the grid voltage vector angle 0g can be calculated using the following equation: 0g = 01 + 0 Eq. 19

[00116] With respect to figures 1 to 5, 9 and 11A to 11C, using several equations from Equations 18 and 19, discussed earlier, the module for estimating the network stress vector angle 116 can calculate the network stress vector angle 0g.

[00117] In the SI 16-1 operation, the angle estimation module of Petition 870240091041, dated 10 / 24 / 2024, page 39 / 115 / 36 network voltage vector 116 can calculate the requested power factor angle Ψ based on the reference power factor PF* using the following equation: Ψ = cos⁻¹(|PF*|) Eq. 20

[00118] In operation S116-2, the network voltage vector angle estimation module 116 can determine whether the absolute value of the reference power factor PF* is equal to 1 or whether the reference power factor PF* is less than zero, and the network voltage vector angle estimation module 116 will use this information about the reference power factor PF* to determine which of the equations included in Equation 18 will be used to calculate the intermediate calculation angle β and the d-axis voltage Vd.

[00119] In operation S116-3, the network voltage vector angle estimation module 116 can calculate the intermediate calculation angle β based on the power factor angle Ψ determined in operation S116-1, the angular frequency of the network voltage vector ω calculated in operation S114, and known line filter parameters L and R, which are the inductance and resistance values ​​of the line filter LR 300, respectively. Additionally, the network voltage vector angle estimation module 116 can calculate the d-axis voltage Vd based on the intermediate calculation angle β, the line filter parameters R and L, the angular frequency of the network voltage vector ω calculated in operation S114, the signaled magnitude of the AFE inverter phase current vector reference is, and a network voltage vector magnitude ug.

[00120] The network voltage vector angle estimation module 116 can calculate the angle β and the d-axis voltage V using different equations from the equations included in Equation 18 based on the reference energy factor PF*.

[00121] For example, if the absolute value of the energy factor of Petition 870240091041, dated 10 / 24 / 2024, page 40 / 115 33 / 36 reference PF* equals 1 or the reference power factor is less than zero, the network voltage vector angle estimation module 116 can determine the angle β and Pausing the following equations: β = ψ + tan⁻¹(Ã / oL) Vd = u + sin(β) x Is x s Eq. 20

[00122] Alternatively, if the absolute value of the reference power factor PF* is not equal to 1 or the reference power factor PF* is greater than or equal to zero, the network voltage vector angle estimation module 116 can determine the angle β and Vd using the following two equations: β - ψ - tan-1(Ã / ωΐβ Vd= ug ~ sin(x Isx ^R2+ (ωΕβ Eq. 21

[00123] In SI operation 16-4, the network voltage vector angle estimation module 116 can calculate the q-axis voltage Vq based on the angle β determined in SI operation 16-3, the line filter parameters L and R, the angular frequency of the network voltage vector ω calculated in SI operation 14, and the magnitude of the AFE inverter phase current vector reference Is. For example, the network voltage vector angle estimation module can calculate Vq using the following equation: Eq. 22

[00124] In SI operation 16-5, the network voltage vector angle estimation module 116 can determine whether the signed magnitude of the inverter phase current vector Is is positive or negative, and the network voltage vector angle estimation module 116 can determine which of the equations in Equation 18 to use to calculate the adjusted angle based on the signed magnitude of the inverter phase current vector Is.

[00125] In the SI 16-6 operation, the angle estimation module of Vq= cos( / 7)x | Is| x^R2+ (ωΐβ Petition 870240091041, dated 10 / 24 / 2024, page 41 / 115 / 36 network voltage vector 116 can calculate the adjusted angle θ based on the equation determined in operation S116-5, in such a way that different equations from the equations included in Equation 18 are used to determine the adjusted angle θ based on the signaled magnitude of the inverter phase current vector Is •

[00126] In operation S116-7, the network voltage vector angle estimation module 116 can calculate the network voltage vector angle θg based on the adjusted angle θ determined in operation S116-6 and the inverter terminal voltage vector angle 0i determined in operation S114.

[00127] Figure 10 illustrates a method for generating an initial inverter terminal voltage vector angle according to some example embodiments.

[00128] With regard to figures 1 to 5 and 10, in S118-1 operation, the initial inverter terminal voltage vector angle detection module 118 can detect the zero crossing instants of the inverter terminal voltage and record the time registers when the AFE 500 inverter is disabled. For example, a hardware device, such as a PSoC chip, can be used to detect the zero crossing instants of the inverter terminal voltage us.

[00129] Based on the time record information recorded at each zero crossing instant, the initial inverter terminal voltage vector angle detection module 118 can estimate the 0i angle of the inverter terminal voltage vector before the AFE 500 inverter is enabled, and use the estimated 0i angle of the inverter terminal voltage vector to initialize the PLL controller.

[00130] In the S118-2 operation, the initial terminal voltage vector angle detection module 118 can calculate the angular frequency of the inverter terminal voltage ω based on the zero-crossing instants of the voltage. Petition 870240091041, dated 10 / 24 / 2024, page 42 / 115 / 36 inverter terminal before the AFE 500 inverter is enabled. For example, the initial terminal voltage vector angle detection module 118 can calculate the angular frequency of the inverter terminal voltage ω in rad / s using the following equation: ω = π / Δt, Eq. 23 where Δt is the difference in the time record in seconds between two zero crossing instants.

[00131] In the S118-3 operation, the initial terminal voltage vector angle detection module 118 can calculate the initial inverter terminal voltage vector angle θ^^ based on the inverter terminal voltage angular frequency ω. For example, the initial inverter terminal voltage vector angle detection module 118 can calculate the initial inverter terminal voltage vector angle Oijnit using the following equation: θ. , = Γωdt + θ i init lnzero cros sin g -J 0- Eq. 24 where 0i-jnité is the calculated initial inverter voltage vector angle of the ........ θ™ ........... and -ge is the inverter voltage vector angle corresponding to the most recent zero crossing instant.

[00132] The initial terminal voltage vector angle detection module 118 can provide the initial inverter terminal voltage vector angle Oi-init for the inverter terminal voltage vector angle detection module 114. As discussed previously, the inverter terminal voltage vector angle detection module 114 can use the initial inverter terminal voltage vector angle 0i-init to initialize the PLL controller integrator in the inverter terminal voltage vector angle detection module 114. Therefore, the PLL controller can start with the correct initial inverter terminal voltage vector angle 0i-init without using the volume of the sensors on the AC network terminal 400. Petition 870240091041, dated 10 / 24 / 2024, page 43 / 115 / 36

[00133] As the exemplary embodiments are thus described, it will be obvious that they can be varied in many ways. Such variations should not be considered as a departure from the spirit and scope of the exemplary embodiments, and it is intended that all such modifications that would be obvious to those skilled in the art are included within the scope of the claims. Petition 870240091041, dated 10 / 24 / 2024, p. 44 / 115

Claims

1 / 8 CLAIMS 1. Controller (100), characterized in that it comprises: a memory with computer-readable instructions stored therein; and a processor configured to execute the computer-readable instructions to estimate a synthesized grid voltage vector angle at a terminal of an alternating current grid, AC (400), without using physical voltage sensors at the alternating current grid terminal, AC, by: estimating (S112) a terminal voltage of an Active Front End Inverter, AFE (500), when the inverter is enabled, the AFE inverter terminal voltage (500) being a voltage at a terminal of the AFE inverter (500); estimate (S118) a first AFE inverter terminal voltage vector angle when the AFE inverter (500) is disabled, the first AFE inverter terminal voltage vector angle being an angle associated with an AFE inverter terminal voltage vector at an initial time;determine (S114) a second AFE inverter terminal voltage vector angle when the AFE inverter (500) is enabled, the second AFE inverter terminal voltage vector angle being an angle associated with the AFE inverter terminal voltage vector at a second time subsequent to the initial time; estimate (S116) the synthesized grid voltage vector angle based on the second AFE inverter terminal voltage vector angle, the synthesized grid voltage vector angle being an angle associated with a voltage vector angle at the AC grid terminal (400);generate Pulse Width Modulation (PWM) signals for Petition 870250054706, dated 06 / 27 / 2025, page 13 / 30 2 / 8 control power switches of the AFE inverter (500) based on at least (i) the synthesized grid voltage vector angle at the AC grid terminal (400), and (ii) a reference power factor at the AC grid terminal, the reference power factor at the AC grid terminal representing a desired phase shift between the voltage vector and a current vector at the AC grid terminal; and, control the AFE inverter (500) to supply power to a load (800) based on the PWM signals.; 2. Controller (100) according to claim 1, characterized in that the processor is configured to generate PWM signals by converting the measured current from a three-phase current measured on a stationary reference frame to a direct quadrature axis (dq) current measured on a rotating dq reference frame, generating a q-axis current reference based on the AC network terminal reference power factor (400), generating a d-axis current reference based on an actual DC bus voltage and a reference DC bus voltage, the actual DC bus voltage being connected to the load (800), the d-axis current reference forming a dq-axis current reference, generating dq-axis reference voltages based on the dq-axis current measured on the rotating dq reference frame and the dq-axis current reference,and generate three-phase gate drive signals for the AFE inverter (500) by converting the dq-axis reference voltages based on the synthesized grid voltage vector angle, the three-phase gate drive signals being the PWM signals.

3. Controller (100) according to claim 2, Petition 870250054706, dated 06 / 27 / 2025, page 14 / 30 3 / 8 characterized in that the processor is configured to convert the measured current from the measured three-phase current to the measured dq shaft current based on the synthesized grid voltage vector angle.

4. Controller (100) according to claim 2, characterized in that the processor is configured to generate the d-axis current reference by: comparing the actual DC bus voltage and the reference DC bus voltage, and generating the d-axis current reference using a PI controller.

5. Controller (100) according to claim 2, characterized in that the processor is configured to generate the q-axis current reference based on the AC network terminal reference power factor and the d-axis current reference.

6. Controller (100) according to claim 2, characterized in that the processor is configured to generate dq-axis reference voltages by: generating a comparison signal based on a comparison result of the d-axis current reference of the q-axis current reference with a measured d-axis value of the dq-axis current and a q-axis value of the dq-axis current, respectively, and generating dq-axis reference voltages based on the comparison signal.

7. Controller (100) according to claim 2, characterized in that the processor is configured to: refine the angle of the synthesized grid voltage vector by compensating for a time delay associated with digital processing to generate a refined synthesized grid voltage vector angle, and generate the three-phase gate drive signals for the AFE inverter (500) based on the dq-axis reference voltages and the angle of the refined synthesized grid voltage vector, wherein the three-phase gate drive signals are transmitted to the AFE inverter (500) to switch a plurality of half-bridges in the power switches of the AFE inverter (500).

8. Controller (100) according to claim 1, characterized in that the processor is configured to generate PWM signals so that the inverter maintains a real DC bus voltage connected to the load (800).

9. Controller (100) according to claim 1, characterized in that, if the inverter is enabled, the processor is configured to make an estimate of the AFE (500) inverter terminal voltage by: estimating three-phase line-to-neutral voltages from the AFE (500) inverter terminal based on the status signals associated with the AFE (500) inverter power switches and corresponding voltage drops across the power switches.

10. Controller (100) according to claim 9, characterized in that the processor is configured to estimate the three-phase line-to-neutral voltages by: examining collector-emitter voltages associated with each of the power switches of the AFE inverter (500).

11. Controller (100) according to claim 1, characterized in that, if the inverter is disabled, the processor is configured to make an estimate of the first terminal voltage vector angle of the AFE inverter (500) by: detecting zero crossing instants when the terminal voltage of the AFE inverter (500) passes through zero, calculating a terminal voltage vector angular frequency of Petition 870250054706, dated 06 / 27 / 2025, page.16 / 30 5 / 8 AFE inverter (500) based on zero crossing instants, the angular frequency of the AFE inverter (500) terminal voltage vector being an angular frequency in rad / s of the AFE inverter (500) terminal voltage, and calculate the first AFE inverter (500) terminal voltage vector angle based on the angular frequency of the AFE inverter (500) terminal voltage vector and a position of an AFE inverter (500) terminal voltage vector corresponding to one of the most recent zero crossing instants.

12. Controller (100) according to claim 1, characterized in that the processor is configured to estimate the second terminal voltage vector angle of the AFE inverter (500) by: initializing a phase latch loop (PLL) using the first terminal voltage vector angle of the AFE inverter (500) when the inverter is disabled, and executing the phase latch loop (PLL) using the three-phase line-to-neutral terminal voltages of the AFE inverter (500) when the inverter is enabled.

13. Controller (100) according to claim 12, characterized in that the processor is configured to estimate the second terminal voltage vector angle of the AFE inverter (500) when executing the PLL to align the second terminal voltage vector angle of the AFE inverter (500) with an axis d of a rotating reference frame dq.

14. Controller (100) according to claim 1, characterized in that, if the AFE inverter (500) is enabled, the processor is configured to estimate the second terminal voltage vector angle of the AFE inverter (500) when executing the PLL to continuously: calculate a position error between the second terminal voltage vector angle of the AFE inverter (500) and the d-axis, calculate an angular frequency of the second terminal voltage vector angle of the AFE inverter (500) when using the PI controller to regulate the position error, and calculate the second terminal voltage vector angle of the AFE inverter (500) when integrating the angular frequency.

15. Controller (100) according to claim 1, characterized in that the processor is configured to estimate the AC grid voltage vector angle by compensating for a phase shift due to a voltage drop through a filter between the AFE inverter terminal (500) and the AC grid terminal (400).

16. Controller (100) according to claim 15, characterized in that the filter is one between an LCL line filter and an LR line filter.

17. Method for generating Pulse Width Modulation (PWM) signals for power switches of an Active Front End (AFE) inverter (500), the method characterized in that it comprises: estimating a synthesized grid voltage vector angle at a terminal of an alternating current, AC (400) grid, without using physical voltage sensors at the AC grid terminal, by: estimating (S112) a terminal voltage of an Active Front End, AFE (500) inverter, when the inverter is enabled, the AFE (500) inverter terminal voltage being a voltage at a terminal of the AFE (500) inverter;estimate (S118) a first AFE inverter terminal voltage vector angle when the AFE inverter (500) is disabled, the first AFE inverter terminal voltage vector angle (500) being an angle associated with a voltage vector from the AFE inverter (500) terminal at an initial time; determine (S114) a second AFE inverter terminal voltage vector angle when the AFE inverter (500) is enabled, the second AFE inverter terminal voltage vector angle (500) being an angle associated with the voltage vector from the AFE inverter (500) terminal at a second time subsequent to the initial time; estimate (S116) the synthesized grid voltage vector angle based on the second AFE inverter terminal voltage vector angle (500), the synthesized grid voltage vector angle being an angle associated with a voltage vector angle at the AC grid terminal (400);Generate Pulse Width Modulation (PWM) signals to control the power switches of the AFE inverter (500) based on at least (i) the synthesized grid voltage vector angle at an AC grid terminal (400) and (ii) a reference power factor at the AC grid terminal (400), the reference power factor at the AC grid terminal (400) representing a desired phase shift between the voltage vector and a current vector at the AC grid terminal (400); and control the AFE inverter (500) to supply power to a load (800) based on the PWM signals.

18. Method according to claim 17, characterized in that generating the PWM signal comprises: converting the measured current from a three-phase current measured on a stationary reference frame to a direct quadrature axis current (dq) measured on a rotating dq reference frame, generating a q-axis current reference based on the AC network terminal reference power factor (400), generating a d-axis current reference based on a real DC bus voltage and a DC bus voltage of Petition 870250054706, dated 06 / 27 / 2025, page.19 / 30 8 / 8 reference, the actual DC bus voltage being connected to the load, the current reference of the q-axis forming a dq-axis current reference, generate dq-axis reference voltages based on the dq-axis current measured on the dq rotating reference frame and the dq-axis current reference, and generate three-phase gate drive signals for the AFE inverter (500) by converting the dq-axis reference voltages based on the synthesized grid voltage vector angle, the three-phase gate drive signals being the PWM signals.

19. Method according to claim 17, characterized in that generating the PWM signal generates the PWM signals so that the inverter maintains a real DC bus voltage connected to the load (800). Petition 870250054706, dated 06 / 27 / 2025, page 20 / 30

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