PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE

Description

1 / 16 “PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE” TECHNICAL FIELD

[0001] This application relates to the field of electronic device technologies and, in particular, to a package substrate, a semiconductor package and an electronic device. FUNDAMENTALS

[0002] With the continuous development of computing and communication technologies, the speed of data exchange between a processor and a memory chip in an electronic device is continually increasing. As a result, requirements regarding the bit width of a memory bus, storage density, and similar factors are also continually increasing. This also places a greater demand on chip packaging technology. During the fabrication of a chip package substrate, the pin arrangement on the package substrate needs to be designed. Usually, on the one hand, electromagnetic crosstalk between pins needs to be reduced, and on the other hand, the pin arrangement density needs to be increased. However, an increase in pin arrangement density causes an aggravation of electromagnetic crosstalk.Therefore, how to implement a high-density, low-crosstalk arrangement mode for pins on a packet substrate is an urgent current problem that needs to be solved. SUMMARY

[0003] This application provides a package substrate, a semiconductor package, and an electronic device, to reduce a chip's package area and reduce crosstalk between chip pins, to implement a high-density, low-crosstalk pin layout mode.

[0004] According to a first aspect, this application provides a package substrate. The package substrate includes a substrate body. The substrate body is provided with a plurality of unit regions. The unit region includes at least one group of solder balls. The group of solder balls includes a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged with spacings. The first Petition 870260059067, dated 06 / 17 / 2026, pp. 30 / 48 2 / 16 solder sphere, the second solder sphere, the third solder sphere, and the fourth solder sphere can be located respectively at four vertices of a parallelogram, and the second solder sphere and the third solder sphere are each adjacent to the first solder sphere. The fifth solder sphere can be provided on one side of the parallelogram and is located between the first solder sphere and the third solder sphere. The sixth solder sphere is provided on another side of the parallelogram and is located between the second solder sphere and the fourth solder sphere. The first solder sphere and the fourth solder sphere are located separately on a perpendicular bisector of a connecting line between the fifth solder sphere and the sixth solder sphere.

[0005] In the aforementioned technical solution, the six solder balls included in the solder ball group are arranged in a parallelogram shape. This can increase the density of the solder ball arrangement, thus reducing the area of ​​the solder ball group, thereby reducing the package area and the manufacturing costs of the semiconductor package. Furthermore, the first and fourth solder balls are located separately on the perpendicular bisector of the connection line between the fifth and sixth solder balls, so that the first and fourth solder balls receive signals with the same amplitudes as the fifth and sixth solder balls. This helps reduce crosstalk in the solder ball group to implement a high-density, low-crosstalk pin arrangement mode.

[0006] In a specific arrangement, the six solder balls in the solder ball group can be four single-termination signal solder balls and two differential-signal solder balls. The first, second, third, and fourth solder balls are single-termination signal solder balls, and the fifth and sixth solder balls are differential-signal solder balls. Specifically, in this solution, the four single-termination signal solder balls form the four vertices of the parallelogram, and the two differential-signal solder balls are located on sides of the parallelogram. Based on the aforementioned structure of the solder ball group, two single-termination signal solder balls are located separately on a perpendicular bisector r of a connecting line between the two signal solder balls. Petition 870260059067, dated 06 / 17 / 2026, page 31 / 48 3 / 16 differential. Two signals from the two differential signal solder balls have the same amplitudes and opposite phases. Therefore, the impact of the differential signal solder balls on the two single-terminated signal solder balls at the perpendicular bisector can cause cancellation between them, to reduce electromagnetic interference caused by a differential signal to a single-terminated signal.

[0007] The interior angles of the parallelogram are not specifically limited. For example, in some possible technical solutions, the interior angles of the parallelogram are 60°, 120°, 60°, and 120°, respectively. Alternatively, in some other possible technical solutions, the interior angles of the parallelogram are 45°, 135°, 45°, and 135°, respectively.

[0008] In some technical solutions, a grounding solder ball is provided on the periphery of each group of solder balls, to reduce crosstalk between adjacent groups of solder balls.

[0009] A specific quantity of grounding solder balls is not limited. A plurality of grounding solder balls may be provided on the periphery of the solder ball group, to form a return ground on the periphery of the solder ball group and reduce electromagnetic interference between the solder ball group and another solder ball group.

[0010] During the specific arrangement of grounding solder balls, the grounding solder ball provided on the periphery of the solder ball group may include 12 grounding solder balls and the 12 grounding solder balls are arranged in a hexagonal shape.

[0011] The unit region may additionally include two groups of solder balls and the two groups of solder balls may share a plurality of grounding solder balls. In this way, the number of grounding solder balls supplied is reduced without affecting signal anti-interference capability, to reduce the area of ​​arrangement of the grounding solder balls.

[0012] During the specific arrangement of the unit region, the two groups of solder spheres can be arranged axisymmetrically or centrosymmetrically based on a specific case. Petition 870260059067, dated 06 / 17 / 2026, pp. 32 / 48 4 / 16

[0013] During the arrangement of the package substrate, two adjacent unit regions may also share a plurality of grounding solder balls, to further reduce the number of grounding solder balls supplied and reduce the arrangement area of ​​the grounding solder balls.

[0014] According to a second aspect, this application provides a semiconductor package. The semiconductor package includes a chip and the package substrate according to the first aspect. The chip is arranged on the package substrate, and a signal pin on the chip is electrically connected to a solder ball on the package substrate. A solder ball arrangement mode on the package substrate can increase pin arrangement density, to reduce the chip package area and further reduce crosstalk between chip pins, to implement a high-density, low-crosstalk pin arrangement mode.

[0015] According to a third aspect, this application provides an electronic device. The electronic device includes a circuit board and the semiconductor package according to the second aspect. The semiconductor package is arranged on the circuit board and the semiconductor package is electrically connected to the circuit board. The circuit board is provided with a signal pin for connection to the semiconductor package, so that the semiconductor package can be connected to another component through the signal pin and a wire on the circuit board, to implement a connection between the chip and an external circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram of the structure of an electronic device according to an embodiment of this application;

[0017] Figure 2 is a diagram of a package substrate structure according to an embodiment of this application;

[0018] Figure 3 is a diagram of a solder ball arrangement structure on a package substrate according to an embodiment of this application;

[0019] Figure 4 is a diagram of another arrangement structure of solder balls on a package substrate according to an embodiment of this application; Petition 870260059067, dated 06 / 17 / 2026, pp. 33 / 48 5 / 16

[0020] Figure 5 is a diagram of another arrangement structure of solder balls on a package substrate according to an embodiment of this application;

[0021] Figure 6 is a diagram of another arrangement structure of solder balls in a package substrate according to an embodiment of this application;

[0022] Figure 7 is a diagram of another arrangement structure of solder balls on a package substrate according to an embodiment of this application;

[0023] Figure 8 is a diagram of a unit region arrangement structure on a package substrate according to an embodiment of this application;

[0024] Figure 9 is a diagram of another arrangement structure of unitary regions on a package substrate according to an embodiment of this application;

[0025] Figure 10 is a diagram of a hardware architecture of a synchronous double data rate dynamic random access memory interface of a CPU according to an embodiment of this application; and

[0026] Figure 11 is a diagram of a DDR interface of a CPU according to an embodiment of this application.

[0027] Reference numerals: 10: electronic device; 11: circuit board; 12: semiconductor packet; 011: byte unit; 121: chip; 122: package substrate; 123 - substrate body; 124 - unit region; 125: group of solder balls; 125a: first solder ball; 125b: second solder ball; 125c: third solder ball; 125d: fourth solder ball; 125e: fifth solder ball; 125f: sixth welding sphere; 126: grounding welding sphere. DESCRIPTION OF MODALITIES

[0028] To make the objectives, technical solutions and advantages of this application clearer, the following further describes this application in detail with reference to the attached drawings. Petition 870260059067, dated 06 / 17 / 2026, pp. 34 / 48 6 / 16

[0029] Reference to a modality, some modalities, or similar terms described in this descriptive report indicates that one or more modalities of this application include a specific feature, structure, or characteristic described in reference to the modalities. Therefore, statements such as “in a modality,” “in another modality,” “in some modalities,” “in some other modalities,” and “in other modalities” that appear in different places in this descriptive report do not necessarily mean reference to the same modality. Instead, the statements mean one or more, but not all, modalities, unless specifically emphasized otherwise. The terms “include,” “comprise,” “have,” and their variants mean all include, but without limitation, unless specifically emphasized otherwise.

[0030] During the specific fabrication of a semiconductor package, a chip is usually placed on a package substrate, and a pin on the chip is electrically connected to a solder ball on the package substrate using a gold wire link or flip-chip technology or similar. Then, the chip and the package substrate are packaged to form a semiconductor package. An external pin of the semiconductor package can be electrically connected to a printed circuit board (PCB) to implement a connection between the chip and an external circuit, and the chip can additionally be electrically connected to another component via a wire on the PCB. It should be noted that, in this application, the chip is a wafer formed by cutting a wafer, and the wafer has a pressure solder point for packaging.

[0031] The effect of semiconductor package packaging directly affects the chip's working performance and the package substrate cabling design. Therefore, semiconductor packaging technology occupies an important position in the semiconductor field. Currently, an important indicator for measuring chip packaging technology performance is the ratio of chip area to package area, where chip area is wafer area. When the chip area is determined, a smaller ratio indicates a larger package area, specifically, a larger semiconductor package size. This causes a decrease in semiconductor package manufacturing yield and further increases manufacturing costs. A ratio close to 1 indicates a smaller package area. In this case, a lower package manufacturing yield Petition 870260059067, dated 06 / 17 / 2026, pp. 35 / 48 As the size of a 7 / 16 semiconductor increases, manufacturing costs can also be reduced correspondingly. Therefore, a smaller package area is better. For the package substrate, the pin array density of the package substrate is an important factor affecting the package area. If the package area is reduced, the pin array density needs to be increased to improve chip pin utilization. However, an increase in the pin array density of the package substrate causes electromagnetic crosstalk between pins, affecting chip performance.

[0032] Therefore, this application provides a package substrate, a semiconductor package, and an electronic device, to reduce a chip's package area and reduce crosstalk between chip pins, to implement a high-density, low-crosstalk pin layout mode.

[0033] Figure 1 is a diagram of the structure of an electronic device according to an embodiment of this application. As shown in Figure 1, the electronic device 10 may include a circuit board 11 and a semiconductor package 12. The semiconductor package 12 may be disposed on the circuit board 11 and is electrically connected to the circuit board 11. The semiconductor package 12 may include a chip 121 and a package substrate 122, wherein the chip 121 is disposed on the package substrate 122. During the packaging of the chip 121, the chip 121 is placed on the package substrate 122 and a pin on the chip 121 is electrically connected to a solder ball on the package substrate 122 using a gold wire link or flip-chip technology or similar.

[0034] In this application, the electronic device 10 can be a switch, a router, a computer, a server, a communication device, or similar. The semiconductor package 12 can be attached to the circuit board 11 by soldering. The circuit board 11 is provided with signal pins. The external pins of the semiconductor package 12 can be connected to the signal pins and are electrically connected to a wire from the circuit board 11 and another component through the signal pins, to implement an electrical connection between the chip 121 in the semiconductor package 12 and an external circuit.

[0035] The following specifically describes the package substrate 122 in this application with reference to the attached drawings.

[0036] Figure 2 is a diagram of a package substrate structure according to an embodiment of this application. As shown in Petition 870260059067, dated 06 / 17 / 2026, pages 36 / 48 8 / 16 Figure 2, the packet substrate 122 may include a substrate body 123. The substrate body 123 is provided with a plurality of unit regions 124. Each unit region 124 may include one or more solder ball groups 125. In other words, each unit region 124 may include at least one solder ball group 125. It should be noted that, in descriptions of this application, a plurality of means at least two. In some embodiments, each unit region 124 may include one solder ball group 125. Therefore, two adjacent unit regions 124 may correspond to a single-byte unit data signal. In some other embodiments, each unit region 124 may include two solder ball groups 125. Therefore, one unit region 124 may correspond to a single-byte unit data signal.

[0037] Figure 3 is a diagram of a solder ball arrangement structure on a package substrate according to one embodiment of this application. As shown in Figure 3, the group of solder balls 125 may include six solder balls: a first solder ball 125a, a second solder ball 125b, a third solder ball 125c, a fourth solder ball 125d, a fifth solder ball 125e, and a sixth solder ball 125f. The six solder balls are arranged with spacing. During the specific arrangement of the solder balls, the first solder ball 125a, the second solder ball 125b, the third solder ball 125c, the fourth solder ball 125d, the fifth solder ball 125e, and the sixth solder ball 125f may be arranged in a parallelogram shape.The first solder ball 125a, the second solder ball 125b, the third solder ball 125c, and the fourth solder ball 125d can be located at four vertices of the parallelogram, and the second solder ball 125b and the third solder ball 125c are each adjacent to the first solder ball 125a. Specifically, a connecting line between the first solder ball 125a and the second solder ball 125b, and a connecting line between the third solder ball 125c and the fourth solder ball 125d, form a group of opposite sides of the parallelogram. The fifth solder ball 125e can be provided on one side of the parallelogram and is located between the first solder ball 125a and the third solder ball 125c. Specifically, the fifth 125e solder ball can be supplied on one side, between the first 125a solder ball and the third. Petition 870260059067, dated 06 / 17 / 2026, pp. 37 / 48 9 / 16 solder sphere 125c of the parallelogram. The sixth solder sphere 125f is provided on the other side of the parallelogram and is located between the second solder sphere 125b and the fourth solder sphere 125d. Specifically, the sixth solder sphere 125f can be provided on one side, between the second solder sphere 125b and the fourth solder sphere 125d of the parallelogram. The first solder sphere 125a and the fourth solder sphere 125d are located separately on a perpendicular bisector (indicated by a dashed and dotted line in Figure 3) of a connecting line between the fifth solder sphere 125e and the sixth solder sphere 125f.

[0038] It should be noted that, in drawings attached to this application, a dashed line connecting solder balls merely indicates a relationship between locations of the solder balls, and the solid lines representing unit region 124 merely indicate a location of unit region 124. These dashed lines and solid lines do not exist in a specific structure of package substrate 122 and therefore do not constitute a limitation on the specific structure of package substrate 122.

[0039] In the aforementioned embodiment, the first solder ball 125a and the second solder ball 125b can constitute a first row of solder balls, the fifth solder ball 125e and the sixth solder ball 125f can constitute a second row of solder balls, and the third solder ball 125c and the fourth solder ball 125d can constitute a third row of solder balls. As shown in Figure 3, solder balls in different rows or columns are arranged in a triangular shape. When a distance between solder balls is determined, the total area of ​​the solder ball group 125 can be reduced in this triangular arrangement mode. Therefore, in the mode in which the six solder balls in the solder ball group 125 are arranged in a parallelogram shape, the arrangement density of the solder balls can be increased to reduce the package area and further reduce the manufacturing costs of the semiconductor package 12.

[0040] The first solder ball 125a and the fourth solder ball 125d are located separately on the perpendicular bisector of the connection line between the fifth solder ball 125e and the sixth solder ball 125f, so that the first solder ball 125a and the fourth solder ball 125d receive signals. Petition 870260059067, dated 06 / 17 / 2026, pages 38 / 48 10 / 16 with the same amplitudes as the fifth 125e solder ball and the sixth 125f solder ball. This helps reduce crosstalk in the 125 solder ball group to implement a high-density, low-crosstalk pin arrangement mode. Furthermore, because the first 125a and fourth 125d solder balls are located separately on the perpendicular bisector of the connection line between the fifth 125e and sixth 125f solder balls, according to a triangle congruence criterion, the distance between the first 125a and third 125c solder balls is greater than the distance between the first 125a and second 125b solder balls.

[0041] In a specific design, the internal angles of the parallelogram are not specifically limited. For example, as shown in Figure 3, in a specific embodiment, four internal angles 01, 02, 03, and 04 of the parallelogram can be 60°, 120°, 60°, and 120°, respectively. Figure 4 is a diagram of another solder ball arrangement structure on a package substrate according to an embodiment of this application. As shown in Figure 4, in another specific embodiment, four internal angles 01, 02, 03, and 04 of the parallelogram can be 45°, 135°, 45°, and 135°, respectively. Figure 5 is a diagram of another solder ball arrangement structure on a package substrate according to an embodiment of this application. As shown in Figure 5, in another specific embodiment, four internal angles 01, 02, 03 and 04 of the parallelogram can be 55°, 125°, 55° and 125°, respectively.

[0042] See also Figure 3 and Figure 4. When the four interior angles 01, 02, 03 and 04 of the parallelogram can be 60°, 120°, 60° and 120°, respectively, or when the four interior angles 01, 02, 03 and 04 of the parallelogram can be 45°, 135°, 45° and 135°, respectively, the fifth solder sphere 125e is at an intermediate point location of a distance between the first solder sphere 125a and the third solder sphere 125c, and the sixth solder sphere 125f is at an intermediate point location of a distance between the second solder sphere 125b and the fourth solder sphere 125d. In this application, an intermediate point location of a distance is an intermediate point location of a connecting line. In other words, the fifth solder ball 125e is located at an intermediate point on a connecting line between the first solder ball 125a and the third solder ball. Petition 870260059067, dated 06 / 17 / 2026, pp. 39 / 48 The 11 / 16th solder ball 125c and the sixth solder ball 125f are at an intermediate point location on a connecting line between the second solder ball 125b and the fourth solder ball 125d. In this embodiment, the distance between the first solder ball 125a and the third solder ball 125c is twice that between the first solder ball 125a and the second solder ball 125b. Furthermore, the distances between two adjacent solder balls are equal, so the area of ​​the parallelogram is minimized.

[0043] In some embodiments, a unit region 124 may include two groups of solder balls 125. The unit region 124 may correspond to a data signal of one byte unit. Each byte unit may usually include eight single-terminated signals and four differential signals. The four differential signals may be divided into two pairs of differential signals. The two signals of each pair of differential signals have the same amplitudes and opposite phases.

[0044] Specifically, in the unit region 124, a first solder ball 125a, a second solder ball 125b, a third solder ball 125c, and a fourth solder ball 125d from each group of solder balls 125 can be single-termination signal solder balls, and a fifth solder ball 125e and a sixth solder ball 125f from each group of solder balls 125 can be differential-signal solder balls. Specifically, the eight single-termination signal solder balls are divided into two groups, and four single-termination signal solder balls in each group form four vertices of a parallelogram; and the two pairs of differential-signal solder balls are located respectively on sides of two parallelograms.Based on the aforementioned structure of the 125 solder ball group, in each 125 solder ball group, two single-termination signal solder balls are located separately on a perpendicular bisector of a connecting line between two differential signal solder balls. The two signals from the two differential signal solder balls have the same amplitudes and opposite phases. Therefore, the impact of the differential signal solder balls on the two single-termination signal solder balls on the perpendicular bisector can cause cancellation between them, to reduce electromagnetic interference caused by a differential signal to a single-termination signal. Furthermore, around each single-termination signal solder ball, there is only one... Petition 870260059067, dated 06 / 17 / 2026, pages 40 / 48 12 / 16 single-termination signal solder balls adjacent to each single-termination signal solder ball are provided. Specifically, a small number of single-termination signal solder balls are provided around each single-termination signal solder ball. Therefore, electromagnetic crosstalk between single-termination signal solder balls can also be reduced.

[0045] Figure 6 is a diagram of another arrangement structure of solder balls on a package substrate according to an embodiment of this application. As shown in Figure 6, a grounding solder ball 126 may be provided on the periphery of each group of solder balls 125, to reduce crosstalk between adjacent groups of solder balls 125. Specifically, the number of grounding solder balls 126 is not limited. For example, in some embodiments, a plurality of grounding solder balls 126 may be provided on the periphery of the group of solder balls 125, to form a return ground on the periphery of the group of solder balls 125 and reduce electromagnetic interference between the group of solder balls 125 and another group of solder balls 125.

[0046] See also Figure 6. In a specific embodiment, 12 grounding solder balls 126 are provided on the periphery of the solder ball group 125. The grounding solder balls 126 are arranged in a hexagonal shape. Four sides of the hexagon can be arranged respectively to be parallel to four sides of a parallelogram of the solder ball group 125. This hexagonal arrangement mode can correspond well to the quadrilateral arrangement mode of the solder ball group 125, so that the 12 grounding solder balls 126 can be densely provided on an outer side of the solder ball group 125. This can reduce the arrangement area of ​​the grounding solder balls 126, so that the package substrate 122 can accommodate more solder balls.In addition, at least three 126 grounding solder balls are provided around each single-termination signal solder ball to effectively reduce electromagnetic interference between signals.

[0047] Figure 7 is a diagram of another solder ball arrangement structure on a package substrate according to an embodiment of this application. As shown in Figure 7, two groups of solder balls Petition 870260059067, dated 06 / 17 / 2026, pp. 41 / 48 13 / 16 adjacent 125 can share a plurality of grounding solder balls 126. In this way, the number of grounding solder balls 126 supplied can be reduced without affecting signal anti-interference capability, to reduce the area of ​​arrangement of the grounding solder balls 126. It should be noted that, in this embodiment, two groups of adjacent solder balls 125 can be located in a unit region 124, or they can be located respectively in two adjacent unit regions 124.

[0048] During a specific arrangement, the spacing between solder balls is not limited in embodiments of this application and can be specifically designed according to an actual use requirement. In some embodiments, the spacing between adjacent solder balls can be in the range of 0.8 mm to 1.2 mm. For example, the spacing between adjacent solder balls can be 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, or 1.2 mm.

[0049] Figure 8 is a diagram of a unit region arrangement structure on a package substrate according to an embodiment of this application. Figure 9 is a diagram of another unit region arrangement structure on a package substrate according to an embodiment of this application. As shown in Figure 8 and Figure 9, in this embodiment of this application, the unit regions 124 can be combined and extended horizontally or vertically to form a pin region of a package substrate 122. The outermost grounding solder balls 126 in the unit region 124 are arranged in a hexagonal shape. Therefore, in a specific design, along a row direction or a column direction, two adjacent unit regions 124 can be arranged in a staggered manner and can share a plurality of grounding solder balls 126 in adjacent parts.Specifically, a right-side vertical edge of a left-side unit region 124a and a left-side vertical edge of a right-side unit region 124b can share four grounding solder balls 126, and a lower angled edge of an upper unit region 124c and an upper angled edge of a lower unit region 124d can share two grounding solder balls 126. This can reduce the area of ​​grounding solder balls 126. Furthermore, as... Petition 870260059067, dated 06 / 17 / 2026, pages 42 / 48 14 / 16 left-side and right-side unit regions 124 can share some grounding solder balls 126, and the upper and lower unit regions 124 can share some grounding solder balls 126, so that the number of grounding solder balls 126 arranged can be reduced without affecting signal anti-interference capability. During the specific arrangement of the unit regions 124, as shown in Figure 8, two groups of solder balls 125 in two adjacent unit regions 124 can be arranged axisymmetrically, specifically, arranged in a butterfly shape. Alternatively, as shown in Figure 9, two groups of solder balls 125 in two adjacent unit regions 124 can be arranged centrosymmetrically.

[0050] In the aforementioned embodiments of this application, chip 121 may be a central processing unit (CPU) chip. Specifically, package substrate 122 may be configured to package a CPU.

[0051] Figure 10 is a diagram of a hardware architecture of a CPU's synchronous dynamic random access memory interface with a double data rate (DDR SDRAM), according to one embodiment of this application. As shown in Figure 10, the CPU side typically includes a plurality of DDR channels, and each DDR channel can drive and be connected to one or more memory modules, for example, dual in-line memory modules (DIMMs). The channel can be a CPU-configurable memory channel, and the memory bandwidth of a channel is typically 32 bits or 64 bits.

[0052] In a specific embodiment, the CPU may include six DDR channels: a channel 0, a channel 1, a channel 2, a channel 3, a channel 4, and a channel 5. Channel 0 may be connected to two memory modules: a DIMM 00 and a DIMM 01. Channel 1 may be connected to two memory modules: a DIMM 10 and a DIMM 11. Channel 2 may be connected to two memory modules: a DIMM 20 and a DIMM 21. Channel 3 may be connected to two memory modules: a DIMM 30 and a DIMM 31. Channel 4 may be connected to two memory modules: a DIMM 40 and a DIMM 41. Channel 5 may be connected to two memory modules: a DIMM 50 and a DIMM 51. It should be understood that the CPU in this embodiment of this application is not limited to the architecture shown in Figure 10. A number of CPU channels and a number Petition 870260059067, dated 06 / 17 / 2026, pages 43 / 48 15 / 16 memory modules connected correspondingly to each channel can be configured according to actual requirements. Details are not described in this document.

[0053] Figure 11 is a diagram of a CPU DDR interface according to one embodiment of this application. As shown in Figure 11, a DDR channel on the CPU side can include a plurality of 011-byte units, each containing 8 bits. It can be understood that when the memory bandwidth of the DDR channel is 32 bits, the DDR channel can include four 011-byte units; or when the memory bandwidth of the DDR channel is 64 bits, the DDR channel can include eight 011-byte units. The embodiment shown in Figure 11 is described using an example in which the memory bandwidth of the DDR channel is 64 bits.

[0054] In this mode, each byte unit 011 can correspond to a unit region 124, in other words, each byte unit 011 can correspond to two groups of solder balls 125. For a DDR channel whose memory bandwidth is 64 bits, each DDR channel corresponds to eight unit regions 124 and the eight unit regions 124 can be arranged in a 4x2 arrangement (4 indicates the number of rows in which the eight unit regions 124 are arranged and 2 indicates the number of columns in which the eight unit regions 124 are arranged) shown in Figure 11 or can be arranged in a 2x4 arrangement (2 indicates the number of rows in which the eight unit regions 124 are arranged and 4 indicates the number of columns in which the eight unit regions 124 are arranged) or can be arranged in a row or a column.Specifically, the layout can be performed based on space division in the 122 package substrate. This is not limited to this application.

[0055] An experiment shows that when the package substrate 122 provided in embodiments of this application is used to package a CPU and a parallelogram-shaped pin arrangement solution is used for the solder ball cluster 125, the electromagnetic crosstalk between DDR data signals can be reduced to -33.5 dB. Furthermore, if a usage area of ​​a unit region 124 arranged in a trapezoidal shape is defined as 1, a usage area of ​​the unit region 124 arranged in the mode in embodiments of this application is approximately 0.95. Therefore, an area of Petition 870260059067, dated 06 / 17 / 2026, pp. 44 / 48 16 / 16 package can be effectively reduced. If a usage area of ​​a unit region 124 arranged in an arrow format is defined as 1, a usage area of ​​the unit region 124 arranged in the mode in the embodiments of this application is approximately 0.92.

[0056] Therefore, in the pin layout solution used for the 122 package substrate in embodiments of this application, electromagnetic crosstalk between DDR data signals can be reduced to enable a CPU to support a higher DDR operating rate, and the pin utilization on the 122 package substrate can also be improved to effectively reduce package area and thus help reduce manufacturing costs of a semiconductor device.

[0057] The terms used in the aforementioned embodiments are intended merely to describe specific embodiments, but are not intended to limit this application. The singular expressions a (numeral), an indefinite article, the, the aforementioned, that and those used in this descriptive report and in the attached claims of this application are also intended to include an expression such as “a or more”, unless explicitly indicated otherwise in the context thereof.

[0058] The above descriptions are merely specific implementations of this application, but are not intended to limit the scope of protection of this application. Any variation or substitution readily understood by an element skilled in the art within the scope of the art disclosed in this application shall fall within the scope of protection of this application. Therefore, the scope of protection of this application shall be subject to the scope of protection of claims. Petition 870260059067, dated 06 / 17 / 2026, pp. 45 / 48

Claims

1 / 2 CLAIMS 1. Package substrate (122), comprising a substrate body (123), wherein the substrate body (123) is provided with a plurality of unit regions, wherein the unit region comprises at least one group of solder balls (125), and the group of solder balls (125) comprises a first solder ball (125a), a second solder ball (125b), a third solder ball (125c), a fourth solder ball (125d), a fifth solder ball (125e), and a sixth solder ball (125f) which are arranged at spacings, wherein the first solder ball (125a), the second solder ball (125b), the third solder ball (125c), and the fourth solder ball (125d) are located respectively at four vertices of a parallelogram, and the second solder ball (125b) and the third solder sphere (125c) are each adjacent to the first solder sphere (125a);and the fifth solder ball (125e) is provided on one side of the parallelogram and is located between the first solder ball (125a) and the third solder ball (125c), the sixth solder ball (125f) is provided on the other side of the parallelogram and is located between the second solder ball (125b) and the fourth solder ball (125d), and the first solder ball (125a) and the fourth solder ball (125d) are located separately on a perpendicular bisector of a connecting line between the fifth solder ball (125e) and the sixth solder ball (125f), CHARACTERIZED in that the first solder ball (125a), the second solder ball (125b), the third solder ball (125c), and the fourth solder ball (125d) are used as single-termination signal solder balls, and the fifth solder ball (125e) and the sixth solder ball (125f) are used as single-termination signal solder balls, and the fifth solder ball (125e) and the sixth solder ball (125f) are used as single-termination signal solder balls. (125f) are used as differential signal welding spheres.; 2. Package substrate (122), according to claim 1, CHARACTERIZED in that the interior angles of the parallelogram are 60°, 120°, 60°, and 120° respectively.

3. Package substrate (122), according to any one of claims 1 to 2, CHARACTERIZED in that a grounding solder ball (126) is provided on the periphery of each group of solder balls (125). Petition 870260059067, dated 06 / 17 / 2026, pp. 46 / 48 2 / 2 4. Package substrate (122), according to claim 3, CHARACTERIZED in that the grounding solder sphere (126) provided on the periphery of the solder sphere group (125) comprises 12 grounding solder spheres, and the 12 grounding solder spheres are arranged in a hexagonal shape.

5. Package substrate (122), according to claim 3 or 4, CHARACTERIZED in that the unit region comprises two groups of solder balls, and the two groups of solder balls share a plurality of grounding solder balls.

6. Package substrate (122), according to claim 5, CHARACTERIZED in that the two groups of solder balls are arranged axisymmetrically or centrosymmetrically.

7. Package substrate (122), according to any one of claims 3 to 6, CHARACTERIZED in that two adjacent unit regions share a plurality of grounding solder spheres.

8. Semiconductor package (12), CHARACTERIZED in that it comprises a chip and the package substrate (122), as defined in any one of claims 1 to 7, wherein the chip is disposed on the package substrate (122).

9. Electronic device (10), CHARACTERIZED in that it comprises a circuit board (11) and a semiconductor package (12), as defined in claim 8, wherein the semiconductor package (12) is disposed on the circuit board (11), and the semiconductor package (12) is electrically connected to the circuit board (11). Petition 870260059067, dated 06 / 17 / 2026, pp. 47 / 48

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