APPARATUS AND METHODS

Abstract

This disclosure provides systems, methods, and devices for memory systems that support updating a configuration of a physical layer interface (PHY) using information stored in a buffer of a connected memory system. In a first aspect, a method of accessing data in a flash memory system includes initializing, by a memory controller of a host device, a PHY for connecting the host device to a memory system to operate at a first speed, receiving PHY configuration information for configuring the PHY to operate at a second speed, greater than the first speed, from a first buffer of the memory system, and adjusting, by the memory controller, a configuration of the PHY in accordance with the PHY configuration information to operate at the second speed. Other aspects and features are also claimed and described.

Description

1 / 70 “APPARATUS AND METHODS CROSS-REFERENCE TO RELATED DEPOSIT REQUESTS

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 187,259, entitled PHYSICAL INTERFACE CONFIGURATION BUFFER IN A FLASH MEMORY SYSTEM, filed March 21, 2023, which is expressly incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Aspects of the present disclosure relate generally to an apparatus and method for controlling a memory device. Some aspects may relate more particularly to an apparatus and method for controlling operations to update a physical interface (PHY) configuration using information from a PHY configuration buffer. INTRODUCTION

[0003] As the value and use of information continue to increase, individuals and businesses are seeking additional ways to process and store information. Furthermore, the use of information in multiple locations and the desired portability of information are increasing daily. For this reason, users are increasingly turning to the use of portable electronic devices such as cell phones, digital cameras, laptops, and the like. Portable electronic devices generally employ a memory system using a memory device to store data. A memory system can be used as either main memory or auxiliary memory for a portable electronic device. Petition 870250080096, dated 08 / 09 / 2025, page 7 / 167 2 / 70

[0004] The memory device of the memory system may include one type or a combination of storage types. For example, magnetic-based memory systems, such as hard disk drives (HDDs), store data by encoding data as a combination of small magnets. As another example, optical-based memory systems, such as digital versatile discs (DVDs) and Blu-ray media, store data by encoding data as physical bits that cause different reflections when illuminated by a light source. As a further example, electronic memory devices store data as collections of electrons that can be detected through voltage and / or current measurements.

[0005] Electronic memory devices can be advantageous in certain systems because they can access data quickly and consume a small amount of power. Examples of an electronic memory device that has these advantages include Universal Serial Bus (USB) memory devices (sometimes called memory sticks), a memory card (as used in some cameras and gaming systems), and a solid-state drive (SSD) (as used in laptops). NAND flash memory is a type of memory device that can be used in electronic memory devices. NAND flash memory is manufactured in memory cards or flash disks. Examples of memory cards include compact flash cards (CF), embedded multimedia cards (eMMCs), smart media cards (SM), and Petition 870250080096, dated 08 / 09 / 2025, page 8 / 167 3 / 70 Secure Digital (SD) cards.

[0006] A memory system can, in some cases, be integrated into, or otherwise connected to, an electronic system. For example, a flash memory system, which may be a universal flash storage (UFS) system, can be integrated into an electronic system such as an access point (AP), a station (STA), user equipment (UE), a base station, a modem, a camera, or another system. A brief summary of some examples.

[0007] The following summarizes some aspects of this disclosure to provide a basic understanding of the technology discussed. This summary is not an extensive overview of all contemplated attributes of the disclosure and is intended to identify key or critically important elements of all aspects of the disclosure, nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in summary form, as an introduction to the more detailed description that is presented later.

[0008] A buffer located in flash memory can be used to store configuration information to perform patching on a PHY to operate at improved speeds. For example, a PHY that connects a memory system, such as a memory system that includes flash memory, to a host device can be configured to operate at a lower speed during host device initialization, which may include the Petition 870250080096, dated 08 / 09 / 2025, page 9 / 167 4 / 70 PHY and Memory System Initialization. The configuration information stored in the PHY can be accessed during host device initialization, such as before flash memory initialization is complete. The host device can read the PHY configuration information from the flash memory and can adjust a PHY setting to operate at a higher speed according to the PHY configuration information. In this way, a memory controller on the host device can access the configuration information at the beginning of an initialization process to perform patching on the PHY to operate at an improved speed. Such improved speeds can allow for faster host device initialization. Additionally, the buffer can allow for the storage of other PHY configuration information to facilitate post-silicon patching of bugs or operational efficiency improvements of the PHY at the beginning of the initialization process.

[0009] In one aspect of the disclosure, a memory device includes a memory controller coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel; and coupled to a host device through a first physical interface (PHY) and configured to communicate with the host device through the first interface. The memory controller of the memory device may be configured to perform operations that include receiving, from the host device, after the PHY is initialized to operate at a first speed, a request for PHY configuration information to configure the PHY to operate at a second, higher speed. Petition 870250080096, dated 08 / 09 / 2025, page 10 / 167 5 / 70 that the first speed, from a first buffer of the memory module and transmit the PHY configuration information to the host device. In another aspect of the disclosure, a method is also disclosed for performing these operations by a processor executing instructions stored in a memory coupled to the processor. In a further aspect of the disclosure, a non-transient, computer-readable medium stores instructions which, when executed by a processor, cause the processor to perform these operations.

[0010] In a further aspect of the disclosure, an apparatus includes a memory controller of a host device configured to couple the host device to a memory system through a first physical interface (PHY), wherein the memory controller is configured to perform operations that include initializing the PHY to operate at a first speed, receiving PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first memory system buffer, and adjusting a PHY configuration according to the PHY configuration information to operate at the second speed. In another aspect of the disclosure, a method is also disclosed for performing these operations by a processor executing instructions stored in a memory coupled to the processor.In a further aspect of disclosure, a non-transient, computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform those operations.

[0011] The previously mentioned described Petition 870250080096, dated 08 / 09 / 2025, page 11 / 167 6 / 70 The attributes and technical advantages of the examples disclosed are broadly described so that the detailed description that follows may be better understood. Additional attributes and advantages will be described hereafter. The specific design and examples disclosed may be readily used as a basis for modifying or designing other structures to accomplish the same purposes as the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed in the present invention, both their organization and method of operation, together with associated advantages, will be better understood from the following description when considered in conjunction with the accompanying figures. Each of the figures is provided for the purpose of illustration and description, and not as a definition of the limits of the claims.

[0012] Although aspects and implementations are described in this application by way of illustration to a few examples, those skilled in the art will understand that additional specific implementations and use cases may arise in many different arrangements and scenarios. The innovations described in the present invention can be implemented in many different types of platforms, devices, systems, formats, sizes, and packaging arrangements. For example, aspects and / or uses may occur via chip implementations and other non-module and component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / shopping devices, medical devices, enabled devices for Petition 870250080096, dated 08 / 09 / 2025, page 12 / 167 7 / 70 artificial intelligence (AI), etc.). Although some examples may or may not be specifically targeted to use cases or applications, there may be a wide range of applicability of the innovations described. Implementations may vary in spectrum from chip-level or modular components to non-modular, non-chip-level implementations that additionally aggregate distributed devices or original equipment manufacturer (OEM) devices or systems that incorporate one or more aspects of the innovations described. In some practical environments, devices incorporating the aspects and attributes described may necessarily also include other components and attributes for the implementation and practice of the claimed and described aspects.For example, the transmission and reception of wireless signals necessarily involve various components for analog and digital purposes (e.g., hardware components including antenna, radio frequency (RF) chains, power amplifiers, modulators, buffer, processor(s), interleaver, adder / summer circuits, etc.). It is intended that the innovations described in the present invention can be implemented in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc., of varying sizes, shapes, and construction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A further understanding of the nature and advantages of the present disclosure can be obtained by reference to the following drawings. In the accompanying figures, Petition 870250080096, dated 08 / 09 / 2025, page 13 / 167 8 / 70 Similar components or attributes may have the same reference label. Additionally, several components of the same type may be distinguished by placing, after the reference label, a dash and a second label that distinguishes them from similar components. If only the first reference label is used in the descriptive report, the description will apply to any of the similar components that have the same first reference label, regardless of the second reference label.

[0014] Figure 1 is a block diagram illustrating a data processing system that includes a memory system, according to an embodiment of the present invention.

[0015] Figure 2 is a block diagram illustrating an example electronic device that includes the memory system, according to one or more aspects of the disclosure.

[0016] Figure 3 is a block diagram illustrating components to facilitate access to a flash memory device from a host device, according to some embodiments of the disclosure.

[0017] Figure 4A is a timing flow diagram that illustrates an initialization process for a host device, according to some dissemination modalities.

[0018] Figure 4B is a timing flow diagram that illustrates an initialization process for a host device, according to some dissemination modalities. Petition 870250080096, dated 09 / 08 / 2025, p. 14 / 167 9 / 70

[0019] Figure 5 is a flowchart that illustrates a method for initializing a host device, according to some disclosure modalities.

[0020] Figure 6 is a flowchart illustrating a method for initializing a host device using PHY configuration information stored in a flash buffer, according to some disclosure modalities.

[0021] Figure 7 is a flowchart illustrating a method for initializing a host device using PHY configuration information stored in a flash buffer by a host controller, according to some embodiments of disclosure.

[0022] Figure 8 is a flowchart illustrating a method for initializing a host device using PHY configuration information stored in a flash buffer by a flash memory device, according to some embodiments of the disclosure.

[0023] Figure 9 is a block diagram that illustrates details of an example wireless communication system, according to one or more aspects.

[0024] Similar reference numbers and designations in the various drawings indicate similar elements. DETAILED DESCRIPTION

[0025] The detailed description presented below, in connection with the accompanying drawings, is intended to be a description of various configurations and is not intended to limit the scope of disclosure. Instead, the detailed description includes specific details for the purpose of providing a complete understanding of the subject matter of the invention. Petition 870250080096, dated 08 / 09 / 2025, page 15 / 167 10 / 70 It will become evident to those skilled in the art that these specific details are not necessary in all cases and that, in some cases, well-known structures and components are shown in block diagram form for the sake of clarity.

[0026] This disclosure provides computer-readable systems, apparatus, methods, and means supporting data processing, including techniques for storing, retrieving, and organizing data in a memory system. Aspects of this disclosure provide operations and data structures used in those operations to perform patching on a PHY that connects a host device to a memory system to operate at a higher speed using PHY configuration information stored in a buffer of a memory subsystem memory.

[0027] The particular implementations of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages or benefits. In some respects, this disclosure provides techniques for improved memory system performance, such as improved speed during a host device initialization process and reduced initialization time. Improved speed during initialization and reduced initialization times can be particularly advantageous in the context of automotive computer systems, where initialization times of less than 50 ms may be desirable.

[0028] Memory can be used in a computer system that is organized as illustrated in Figure 1. Figure 1 illustrates a data processing system. Petition 870250080096, dated 08 / 09 / 2025, page 16 / 167 11 / 70 100, as it may be included in a mobile computing device, according to one or more aspects of the disclosure. A memory system 110 may couple to a host device 102 through one or more channels. For example, the host device 102 and the memory system 110 may be coupled through a serial interface that includes a single channel for data transport or a parallel interface that includes two or more channels for data transport. In some aspects, control data may be transferred through the same channel(s) as the data, or control data may be transferred through additional channels. The host device 102 may be, for example, a portable electronic device such as a mobile phone, an MP3 player, a laptop computer, or a non-portable electronic device such as a desktop computer, a gaming console, a television (TV), a media player, or a projector.As another example, host device 102 could be a self-propelled computer system. Additional example host devices are illustrated and described with reference to Figure 6.

[0029] Memory system 110 can perform operations in response to commands (e.g., a request) from host device 102. For example, memory system 110 can store data provided by host device 102, and memory system 110 can also provide stored data to host device 102. Memory system 110 can be used as main memory, short-term memory, or long-term memory by host device 102. As an example of main memory, host device 102 can use memory system 110 to supplement Petition 870250080096, dated 08 / 09 / 2025, page 17 / 167 12 / 70 or replace system memory with the use of system memory 110 to store temporary data, such as data relating to operating systems and / or threads running in the operating system. As an example of short-term memory, the host device 102 can use system memory 110 to store a page file for an operating system. As an example of long-term memory, the host device 102 can use system memory 110 to store user files (e.g., documents, videos, images) and / or application files (e.g., executable word processing element, game application).

[0030] The 110 memory system can be implemented with any of several storage devices, according to the protocol of a host interface for the one or more channels that couple the 110 memory system to the 102 host device. The 110 memory system can be implemented with any of several storage devices, such as a solid-state drive (SSD), a multimedia card (MMC), an integrated MMC (eMMC), a reduced-size multimedia card (RS-MMC), a micro-MMC, a secure digital card (SD), a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash card (CF), a smart media card (SM), or a memory stick.

[0031] The memory system 110 may include a memory module 150 and a controller 130 coupled to the memory module 150 through one or more channels. The module of Petition 870250080096, dated 09 / 08 / 2025, p. 18 / 167 Memory module 150 can store and retrieve data in memory blocks 152, 154, and 156 under the control of controller 130, which can execute commands received from host device 102. Controller 130 is configured to control the data exchange between memory module 150 and host device 102.Storage components, such as blocks 152, 154, and 156 in memory module 150, can be implemented as volatile memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), or as non-volatile memory devices, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (SCRAM), or NAND flash memory.

[0032] The controller 130 and the memory module 150 may be formed as integrated circuits on one or more semiconductor wafers (or other substrate). In some respects, the controller 130 and the memory module 150 may be integrated into a single chip. In some respects, the memory module 150 may include one or more chips coupled in series or parallel with each other and coupled to the controller 130. Petition 870250080096, dated 08 / 09 / 2025, page 19 / 167 14 / 70 which is on a separate chip. In some respects, the memory module 150 and the controller chips 130 are integrated into a single package, as in a package-on-package (PoP) system. In some respects, the memory system 110 is integrated into a single chip with one or more or all of the components (e.g., application processor, system memory, digital signal processor, modem, graphics processing unit, memory interface, input / output interface, network adapter) of the host device 102, as in a system-on-chip (SoC) system.The controller 130 and the memory module 150 can be integrated into a semiconductor device to form a memory card, such as, for example, a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash Card (CF), a Smart Media Card (SMC), a memory stick, a Multimedia Card (MMC), an RS-MMC, a micro-MMC, a Secure Digital Card (SD), a mini-SD, a micro-SD, a Secure Digital High Capacity (SDHC) card, and a Universal Flash Storage (UFS) device.

[0033] The memory system controller 130 can control the memory module 150 in response to commands from the host device 102. The controller 130 can execute read commands to provide data from the memory module 150 to the host device 102. The controller 130 can execute write commands to store data provided by the host device 102 in the memory module 150. The controller 130 can execute other commands to Petition 870250080096, dated 08 / 09 / 2025, page 20 / 167 15 / 70 manages data in memory module 150, such as programming and erasing commands. Controller 130 can also execute other commands to manage the control of memory system 110, such as setting configuration registers for memory system 110. By executing commands according to the configuration specified in the configuration registers, controller 130 can control operations of memory module 150, such as read, write, programming, and erase operations.

[0034] The controller 130 may include various components configured to perform the received commands. For example, the controller 130 may include a host interface (I / F) unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit (PMU) 140, a NAND flash controller (NFC) 142, and / or a memory module 144. The power management unit (PMU) 140 may provide and manage power to components in the controller 130 and / or the memory module 150.

[0035] Host interface unit 132 can process commands and data provided by host device 102 and can communicate with host device 102 through at least one of several interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-e), Serial Attached Small Computer System Interface (SAS), Advanced Technology Accessory Petition 870250080096, dated 08 / 09 / 2025, page 21 / 167 16 / 70 serial (SATA - serial advanced technology attachment), parallel advanced technology attachment (PATA - parallel advanced technology attachment), small computer system interface (SCSI), enhanced small disk interface (ESDI - enhanced small disk interface), and integrated drive electronics (IDE - integrated drive electronics). For example, the 132 host interface could be a parallel interface, such as an MMC interface, or a serial interface, such as an ultra-high speed class 1 (UHS-I - ultra-high speed class 1) / ultra-high speed class 2 (UHS-II - ultra-high speed class 2) interface or a universal flash storage interface (UFS).

[0036] The ECC 138 unit can detect and correct errors in the data read from the memory module 150 during the read operation. The ECC 138 unit may not correct error bits when the number of error bits is greater than a threshold number of correctable error bits, which may result in the ECC 138 unit emitting an error correction failure signal indicating failure to correct the error bits. In some respects, no ECC 138 unit may be provided or the ECC 138 unit may be configurable to be active for part or all of the memory module 150.The ECC 138 unit can perform an error correction operation using a coded modulation, such as a low-density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or... Petition 870250080096, dated 08 / 09 / 2025, page 22 / 167 17 / 70 is a block-coded modulation (BCM).

[0037] The NFC 142 provides an interface between the controller 130 and the memory module 150 to allow the controller 130 to control the memory module 150 in response to commands received from the host device 102. The NFC 142 can generate control signals for the memory module 150, such as signals for row lines and bit lines, and can process data under the control of the processor 134. Although the NFC 142 is described as a NAND flash controller, other controllers can perform a similar function for other types of memory used as memory module 150.

[0038] Memory 144 can serve as working memory for memory system 110 and controller 130. Memory 144 can store data to drive memory system 110 and controller 130. When controller 130 controls an operation of memory module 150, such as a read, write, program, or erase operation, memory 144 can store data that is used by controller 130 and memory module 150 for the operation. Memory 144 can be implemented with volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some respects, memory 144 can store address mappings, program memory, data memory, a write buffer, a read buffer, a map buffer, and the like.

[0039] Processor 134 can control general system memory operations 110 and an operation of Petition 870250080096, dated 08 / 09 / 2025, page 23 / 167 18 / 70 write or read operation to memory module 150, in response to a write request or a read request received from the host device 102, respectively. For example, processor 134 may execute firmware, which may be called a flash translation layer (FTL), to control the general operations of the memory system 110. Processor 134 may be implemented, for example, with a microprocessor, or a central processing unit (CPU), or an application-specific integrated circuit (ASIC).

[0040] Figure 2 is a block diagram illustrating an example electronic device that includes the memory system 100, according to one or more aspects of the disclosure. The electronic device 200 may include a user interface 210, a memory 220, an application processor 230, a network adapter 240, and a storage system 250 (which may be an embodiment of the memory system 100 of Figure 1). The application processor 230 may be coupled to the other components via a bus, such as a Peripheral Component Interface (PCI) bus, including a PCI Express (PCIe) bus.

[0041] The application processor 230 can execute computer program code, including applications, drivers, and operating systems, to coordinate the execution of tasks by components included in the electronic device 200. For example, the application processor 230 can execute a storage driver for Petition 870250080096, dated 08 / 09 / 2025, page 24 / 167 19 / 70 access the storage system 250. The application processor 230 may be part of a system on a chip (SoC) that includes one or more of the other components shown in the electronic device 200.

[0042] Memory 220 can operate as main memory, working memory, buffer memory, or cache memory of the electronic device 200. Memory 220 can include volatile random access memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR), DDR2 SDRAM, DDR3 SDRAM, low power double data rate SDRAM (LPDDR), LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM, or non-volatile random access memory, such as phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).In some respects, the 230 application processor and 220 memory can be combined using a packet-on-package (POP) approach.

[0043] The 240 network adapter can communicate with external devices. For example, the 240 network adapter can support wired and / or various wireless communications, such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA). Petition 870250080096, dated 08 / 09 / 2025, page 25 / 167 20 / 70 wideband code division multiple access), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (WiMAX), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (Wi-Di), and so on, and can thus communicate with wired and / or wireless electronic devices, for example, a mobile electronic device.

[0044] Storage system 250 can store data, for example, data received from application processor 230, and transmit data stored in it to application processor 230. Storage system 250 can be a non-volatile semiconductor memory device, such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash memory, a NOR flash memory, or a three-dimensional (3-D) NAND flash memory. Storage system 250 can be a removable storage medium, such as a memory card or an external drive. For example, storage system 250 can correspond to memory system 110 described above with reference to Figure 1 and can be an SSD, an eMMC, a UFS, or another flash memory system.

[0045] The user interface 210 provides one or more graphical user interfaces (GUIs) for entering data or commands into the application processor 230 or for sending data to a device. Petition 870250080096, dated 08 / 09 / 2025, page 26 / 167 21 / 70 external. For example, the 210 user interface may include user input interfaces such as a virtual keyboard, a touchscreen, a camera, a microphone, a gyroscope sensor, or a vibration sensor, and user output interfaces such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, an active matrix organic light-emitting diode (AMOLED) display device, a light-emitting diode (LED), a loudspeaker, or a haptic motor.

[0046] Figure 3 is a block diagram illustrating components to facilitate access to a flash memory system from a host device, according to some embodiments of the disclosure. The host device 102 accesses the memory system 110 through the first interface 310. The first interface may, for example, be a physical interface (PHY). The host device 102 may include a physical layer access block 312, which is configured to generate signals for output to the first interface 310 and to process signals received through the first interface 310. The memory system 110 includes a similarly configured physical layer access block 322 for communication on the first interface 310. An example physical layer specification for communication on the first interface 310 is the MIPI M-PHY™ physical layer specification.

[0047] Host device 102 also includes a data link layer block 314 configured to format data frames for transmission on the first interface 310. Frames can be provided to the block of Petition 870250080096, dated 08 / 09 / 2025, page 27 / 167 22 / 70 physical layer access 312 for transmission. Data link layer block 314 can receive frames from physical layer access block 312 and decode data frames received on the first interface 310. Memory system 110 includes a similarly configured data link layer block 324 to process frames transmitted or received on the first interface 310 by physical layer access block 322. An example data link protocol for communication on a MIPI M-PHY™ physical link is the MIPI UNIPRO™ specification.

[0048] The 110 memory system includes N logical units 350a to 350n comprising logical memory blocks for storing information that includes user data (e.g., user documents, application data) and configuration data (e.g., information about the operation of the 110 memory system). Logical units 350a to 350n can map portions of physical memory blocks 152, 154, and 156. Some of the logical units 350a to 350n, or portions of the logical units 350a to 350n, can be configured with write protection, initialization capability, as a specific memory type (e.g., standard, system code, non-persistent, enhanced), priority access, or replay protection as a replay-protected memory block (RPMB).Physical layer access block 322 and data link layer block 324 perform memory controller operations for system memory 110 to store and retrieve data in logical units 350a to 350n. As a particular example, one or more logical units of logical units 350a to 350n. Petition 870250080096, dated 09 / 08 / 2025, p. 28 / 167 23 / 70 can be configured as a buffer for storing PHY configuration information, as described in the present invention, as one or more patches to configure interface 310 to operate at different speeds. The logical units of the buffer can be configured to be accessible before the memory system 110 is fully initialized, such as before an fDeviceInit operation for the memory system is complete, to allow a communication speed through interface 310 to be increased at the beginning of a host device initialization process 102. An fDeviceInit operation can be an initialization operation for the memory system. In some embodiments, an fDeviceInit flag can be set at the beginning of an initialization operation for a UFS memory system and can be reset when the memory system initialization is complete.In some modes, the logical buffer units can be locked or configured as read-only to prevent changes to the PHY configuration information.

[0049] The 110 memory system also includes 352 configuration structures. 352 configuration structures can include information such as configuration descriptors for boot enable (bBootEnable), initial power mode (bInitPowerMode), active RPMB (bRPMBRegionEnable), and / or RPMB region sizes (bRPMBRegion1Size, bRPMBRegion2Size, bRPMBRegion3Size). Such configuration structures can, for example, be specified by the UFS standard.

[0050] Host device 102 can be configured to run one or more applications 334, such as Petition 870250080096, dated 08 / 09 / 2025, page 29 / 167 24 / 70 user applications run by an operating system under the control of a user to receive user input and provide information stored in the memory system 110 to the user. The host device 102 may include various components to interface the application 334 with the memory system 110 through the first interface 310. For example, a SCSI driver 332 and a UFS driver 330 may interface the application 334 with a host memory controller that includes the data link layer block 314 and the physical layer access block 312. The SCSI driver 332 may run in an application layer to handle transactions requested by the application 334 with the memory system 110. The UFS driver 330 may run in a transport layer and manage the operation of the data link layer block 314 in order to operate the first interface 310 in one of a plurality of operating modes.The operating modes may include two or more gear configurations, such as one or more PWM-GEAR configurations and four or more HS-GEAR configurations that specify a bit rate of 182 MBps, 364 MBps, 728 MBps, and 1457 MBps.

[0051] The first interface 310 may include one or more lines that include an RST reset line, a reference clock REF_CLK line, a data input DIN line (for data transmissions from host device 102 to memory system 110), and a data output DOUT line (for data transmissions from memory system 110 to host device 102). The DIN and DOUT lines may be two separate conductors, or the DIN and DOUT lines may include multiple conductors. In some embodiments, the DIN and DOUT lines may be asymmetrical in Petition 870250080096, dated 09 / 08 / 2025, p. 30 / 167 25 / 70 in relation to the DIN line which includes N conductors and the DOUT line which includes M conductors, where N > M or M > N.

[0052] The UFS driver 330 can generate and decode packets to process transactions requested by the application 334. The packets are transmitted through the first interface 310. The packets can be formatted as UFS protocol information units (Universal Flash Storage Protocol Information Units). In a transaction with the memory system 110, the host device 102 is an initiator and the memory system 110 is a target. The UFS driver 330, based on the transaction type, can form one of several types of UPIUs to handle SCSI commands, data operations, task management operations, and / or query operations. Each transaction can include a command UPIU, zero or more data input or data output UPIUs, and a response UPIU. Each UPIU can include a header followed by optional fields, depending on the UPIU type.

[0053] An example transaction is a read operation. A read transaction may include the initiator (e.g., host device 102) that transmits a command UPIU to cause the target (e.g., memory system 110) to perform a read operation requested by application 334. The target provides one or more input UPIUs in response to the command UPIU, where the input UPIUs include the requested data. The read transaction is completed by the target transmitting a response UPIU.

[0054] Another example transaction is a write operation. A write operation can include Petition 870250080096, dated 08 / 09 / 2025, page 31 / 167 26 / 70 The initiator (e.g., host device 102) transmits a command UPIU to cause the target (e.g., memory system 110) to perform a write operation requested by application 334. The target provides a ready-to-transfer UPIU that signals the initiator to begin the write data transfer. The initiator then transmits one or more data-out UPIUs, which are followed by a ready-to-transfer UPIU that signals the initiator to continue the write data transfer. The sequence of data-out UPIUs and ready-to-transfer UPIUs continues until all write data is provided to the target, at which point the target provides a response UPIU to the initiator.

[0055] An additional example transaction is a query operation. A query operation may include the initiator (e.g., host device 102) requesting information about the target (e.g., memory system 110). The initiator may transmit a query request UPIU to request information such as configuration, enumeration, device descriptor, flags, and / or attributes of the target. Examples of query operations include read descriptor, write descriptor, read attribute, write attribute, read flag, set flag, purge flag, and / or toggle flag. Examples of descriptors include device, configuration, unit, interconnect, chain, geometry, power, and / or device health. Examples of flags include fDeviceInit, fPermanenetWPEn, fPowerOnWPEn, fBackgroundOpsEn, fDeviceLifeSpanModeEn, fPurgeEnable, fRefreshEnable, fPhyResourceRemoval, fBusyRTC, and / or Petition 870250080096, dated 08 / 09 / 2025, page 32 / 167 27 / 70 fPermanentlyDisableFwUpdate. Examples of attributes include bBootLunEn, bCurrentPowerMode, bActiveICCLevel, bOutOfORderDataEn, bBackgroundOpStatus, bPurgeStatus, bMaxDataInSize, bMaxDataOutSize, dDynCapNeeded, bRefClkFreq. Such flags may, for example, be flags specified by the UFS standard.

[0056] The operations and capabilities described above can be used for a memory system that supports adjusting a PHY configuration according to PHY configuration information stored in a memory system memory connected to a host device by the PHY to enable enhanced communication speeds through the PHY. Using a memory system memory buffer to store PHY configuration information can allow a PHY configuration to be updated before the host device initialization process is complete, such as before the initialization of the memory in which the buffer is located is complete, so that PHY configuration information is retrieved from memory before the memory is fully initialized.

[0057] As described in the present invention, a host device can be connected to a memory system, such as a UFS flash memory system, via a PHY. In some cases, the host device, the memory system, and the PHY can be integrated into a single SoC. During the initialization, or startup, of the host device, the PHY can be configured to operate at different speeds during different parts of the startup process. In some systems, such as systems where a host device is Petition 870250080096, dated 08 / 09 / 2025, page 33 / 167 When a 28 / 70 device is connected to a UFS or NVMe memory system, initialization can require a substantial amount of time, such as between 34 and 150 ms, due to PHY initialization that connects the host device to the memory system, link start requirements such as link initialization and negotiation between the host device and the memory system, and firmware initialization such as logical-to-physical (L2P) table preparation and other background activities for the host device and / or memory system. Initialization times may vary based on vendor and device types. In particular, different devices manufactured by different vendors may require different amounts of time for different stages and initialization operations, such as link start, no-operation messaging (NOP), fDeviceInit, and other operations.Boot times can be impacted by PHY initialization times, link start times, slow PHY operating speeds during boot ROM read time, and multiple UFS initialization processes performed during the boot process. In some use cases, such as automotive use cases, a reduced boot time, such as a boot time of less than 50 ms, may be desirable.

[0058] During the initialization of a host device, a PHY that connects the host device to a memory system may operate at different link speeds at different times. Such initialization may include the initialization of the PHY that connects the host device to the memory system, the initialization of the device Petition 870250080096, dated 08 / 09 / 2025, page 34 / 167 29 / 70 host and memory system initialization. Increasing the speed at which the PHY is configured to operate during one or more times of the initialization process can reduce the amount of time required for the initialization process. An example 400 initialization process might include the initialization of the PHY, the memory system, and other systems and / or devices. The 400 initialization process, which may also be called an initialization process, can be divided into a plurality of stages, as shown in Figure 4A. In a first stage 402, which may be a pre-boot loader (PBL) stage, a PBL might configure the PHY to operate at a lower speed, such as a high-speed gear one (HS-G1) speed.For example, the PHY can be configured by the PBL, in the first 402 stage, to operate at HS-G1 speed to minimize post-silicon changes in the PHY, which may require PBL patching. At the beginning of the first 402 stage, the PHY can be configured to operate at a pulse width modulation 1 (PWM-1) speed, which may be slower than an HS-G1 speed. In 418 operation, the host device, PHY, and memory system can be motor-equipped and initialized to operate at a low speed, such as PWM1. For example, such operations may include a power-on reset, a hardware reset, and an endpoint reset. After such resets have been performed, there may be no active tasks in the device UFS descriptors, and attributes and flags may be set to their default values. Additionally, the UniPro attributes... Petition 870250080096, dated 08 / 09 / 2025, page 35 / 167 30 / 70 can be reset. The memory system can be minimally initialized to allow the memory system to begin communicating with the host device via the PHY, and a link start procedure can be performed. Such a link start procedure can initialize an older link between the host device and the memory system via the PHY. When operation 418 is completed, a PHY speed can increase to an HS-G1 speed. In operation 420, the host device can read from one or more initialization lookup numbers (LUNs). In a second stage 404, a complete reset of the memory system can be performed, and a PHY operating speed can be increased to a high-speed gear 4 (HS-G4) speed.For example, in operation 422, the memory system, which may be a UFS memory system, and the PHY may be reset, and a link startup procedure may be performed. After the reset, a PHY speed may be reduced to a PWM-1 speed until, in operation 424, the UFS is restarted, a NOP output is transmitted by the host device, a NOP input is received by the host device, and a memory system initialization stage, such as fDeviceInit, is completed. After operation 424 is complete, the PHY may be configured to operate at an HS-G4 speed, where the PHY may, in operation 426, read from all LUNs in the memory system. Speeds such as PWM-1, HS-G1, HS-G2, HS-G3, and HS-G4 may, for example, be speeds specified by the UFS standard.

[0059] During the initialization process 400, Petition 870250080096, dated 08 / 09 / 2025, page 36 / 167 Multiple system memory resets and initializations can be performed on the 31 / 70 model. For example, a first reset and initialization during the first 402 stage and a second reset and initialization during the second 404 stage. Such resets and associated link start and initialization operations can contribute substantially to the initialization time. For example, the link starts associated with the resets can contribute up to and may exceed 80 ms of initialization time, where each link start adds 20 to 30 ms to the initialization time. Furthermore, during later initialization stages, a full reset can be performed on the PHY and system memory, including setting the PHY to operate at an HS-G4 speed, a link start procedure, an fDeviceInit procedure, and other initialization operations.The link departure performed in operation 422 may invalidate and / or reset any initialization performed by the memory system prior to operation 422.

[0060] To reduce startup time, such as startup time, a host device may perform a system memory and PHY initialization during the initialization procedure. However, to allow the PHY to be initialized to operate at a higher speed during the PBL 402 stage, PHY configuration information stored in memory, such as flash memory, of the system memory may be used to perform patching on the PHY for operation at a higher speed, such as HS-G4 speed. For example, one or more of the link startup procedures and Petition 870250080096, dated 08 / 09 / 2025, page 37 / 167 32 / 70 initialization for the memory system can be eliminated, where a PHY and a link initialization procedure are performed only once during a complete initialization procedure. In some cases, two link initializations and a device initialization procedure can be eliminated. Eliminating one or more initialization procedures for the PHY and / or the memory system can reduce initialization time by up to or exceeding 70 ms. Additionally, the memory system can be configured to complete initialization in the background during the second 404 stage and subsequent stages, which may allow skipping one or more NOP and fDeviceInit operations performed during the second 404 initialization stage. The PHY can also be initialized, during a PBL stage, to operate at a higher speed, such as HS-G4, instead of HS-G1, further reducing initialization time.For example, as shown in process 450 of Figure 4B, a PHY speed can be increased from a PWM-1 speed at the start of the first stage 402 of the initialization process to an HS-G4 speed. The host device can read from the initialization LUN in 420 at an HSG4 speed instead of HS-G1, as shown in Figure 4A. Furthermore, operation 422 can be bypassed, and operation 452 can include a full memory system initialization that includes an fDeviceInit operation while the PHY remains configured to operate at HS-G4 speed through the second stage 404 and subsequent stages.

[0061] Configuring a PHY to operate at a high speed at the start of the initialization process, such as Petition 870250080096, dated 08 / 09 / 2025, page 38 / 167 Enabling PHY configuration to operate at speeds higher than HS-G1 (33 / 70) may involve updating a PHY configuration. Such an update can present challenges due to limitations in post-silicon updates for PHY firmware and PBL ROM patching. Configuring the PHY to operate at a high speed early in the initialization process, such as during the PBL 402 stage, may increase the risk of PBL patching requirements due to post-silicon PHY characterization and may also increase the risk of post-silicon PHY changes due to specific client board adjustments. Enabling PHY configuration updates to facilitate PHY operation at speeds higher than HS-G1 during the PBL 402 stage may involve the use of additional PBL patch space allocation to support such patching and to support UFS PHY updates that may occur after post-silicon characterization.Such additional PBL patch space can increase the cost of a SoC that includes the host device, the PHY, and the system memory. Such problems can be mitigated, however, through the use of a buffer located in a memory, such as flash memory, of the system memory for storing PHY configuration information, as one or more PHY patches, to update the PHY to operate at a higher speed. For example, a PHY can be patched using PHY configuration information stored in a system memory buffer that is accessible early in the boot process, such as after performing a minimal system memory initialization on operation 418 and before the system memory initialization is complete, such as before an fDeviceInit operation on 452. Petition 870250080096, dated 08 / 09 / 2025, page 39 / 167 34 / 70 complete. Updating a PHY configuration to operate at enhanced speeds at the start of a startup process can reduce the amount of time required to complete the startup process. For example, in process 400 of Figure 4A, the PHY can be configured to operate at an HS-G1 speed during the PBL 402 stage, while in process 450 of Figure 4B, the PHY can be configured to operate at an HS-G4 speed, or another higher speed, during the PBL 402 stage. The speed at which the PHY can be reconfigured to operate may be limited by the version of the UFS specification supported by the PHY. For example, if the PHY supports UFS 2.x, a maximum speed of high-speed gear three (HS-G3), B ratio, 2L can be supported; if the PHY supports UFS 3.1, a speed of HS-G4, B ratio, 2L can be supported; and if the PHY supports UFS 4...0, a five-speed high-speed gear (HS-G5), B ratio, 2L can be supported.

[0062] As a particular example, Figure 5 is a flowchart illustrating an example initialization process, which may be similar to the initialization process 400 of Figure 4A. In some embodiments, the steps of method 500 may be performed by a host device connected to a memory system by a PHY. In some embodiments, one or more of the steps may be performed by the PHY and / or the memory system. Method 500 may include, in block 502, configuring a PHY that connects a host device to a memory system to operate at a first speed, such as a reliable high-speed mode. Such a speed mode may, for example, be an HS-G1 speed. Petition 870250080096, dated 09 / 08 / 2025, p. 40 / 167 35 / 70 This configuration can be performed by a PBL (Progressive Learning Block) on the host device.

[0063] In block 504, an initial link start-up can be performed. For example, a link between the host device and the memory system can be initialized. During such a stage, the PHY can operate at a speed of PWM-1. Such a link start-up can include transmitting an outgoing NOP message to a memory system controller and receiving an incoming NOP message from the memory system controller.

[0064] In block 506, a gear switch can be implemented for the PHY to operate at a speed of HS-G1. Such a gear switch can, for example, be implemented based on the configuration of block 502.

[0065] In block 508, a device query can be transmitted from the host device and received by the memory system, and the host device can receive a response from the memory system. The response can, for example, include information about the memory system, such as a memory system class, a memory system initialization process configuration, one or more memory system LUNs where initialization information is stored, an initialization sequence ID, and other information for initialization of the host device, PHY, and memory system.

[0066] In block 510, the host device can read information from one or more initialization LUNs. This information may, for example, include initialization code for initialization of the host device, the PHY, and / or the memory system. In particular, the host device may Petition 870250080096, dated 08 / 09 / 2025, page 41 / 167 36 / 70 transmit one or more small computer system interface (SCSI) read requests to the system memory to read the initialization code of a well-known logical initialization unit.

[0067] In block 512, a UFS reset can be performed on the memory system. For example, the host device can completely reset the memory system to facilitate configuring the PHY to operate at a higher speed.

[0068] In block 514, the PHY can be configured to operate at an increased speed, such as in a high-speed mode. For example, the PHY can be configured to operate in a higher-speed mode, such as HS-G4 speed. Such configuration can, for example, be performed by software.

[0069] In block 516, a link start procedure can be performed. The link start procedure in block 516 can, for example, be a second or third link start procedure of an initialization process.

[0070] In block 518, an fDeviceInit operation can be performed to complete the memory system initialization.

[0071] In block 520, a gear switch can be implemented for the PHY to operate in a high-speed mode, such as in an HS-G4 speed mode. In some embodiments, such a configuration may include setting to operate in a higher speed mode supported by the memory system. For example, a PHY operating speed can increase from PWM-1 to Petition 870250080096, dated 09 / 08 / 2025, p. 42 / 167 37 / 70 HS-G4.

[0072] In block 522, a device query can be transmitted from the host device and received by the memory system, and the host device can receive a response from the memory system. Such operations may be similar to the operations described in block 508.

[0073] In block 524, the host device can read information from one or more startup LUNs.

[0074] The use of PHY configuration information from a memory system buffer can, however, allow for a reduction in startup time, enabling the PHY configuration to operate at a higher speed at the beginning of the startup process and allowing it to bypass one or more reset, initialization, and link departure operations. For example, the operations in blocks 512 to 516 of method 500 can be bypassed through the use of such configuration information. Figure 6 shows an example method 600 that includes using PHY configuration information stored in a memory system buffer connected to a host device by the PHY to increase the PHY speed at the beginning of the startup process. Method 600 may include, in block 602, configuring a PHY that connects a host device to a memory system to operate at a higher speed, such as to operate in a reliable low-speed mode.The first gear could, for example, be an HS-G1 or PWM-1 gear. Such a configuration can be implemented by a PBL from the host device to allow the host device to read from one. Petition 870250080096, dated 09 / 08 / 2025, p. 43 / 167 38 / 70 buffer, like a SoC buffer, which stores PHY configuration information.

[0075] In block 604, a link startup can be performed. For example, a link can be initialized between the host device and the memory system. During such a stage, the PHY can operate at a speed of PWM-1. The link startup of block 604 can, for example, be the only link startup procedure performed during method 600, where multiple link startup procedures can be performed in method 500.

[0076] In block 606, the host device can read PHY configuration information from a buffer, such as a memory system buffer. As described in the present invention, the PHY configuration information may include one or more patches to perform patching on a PHY. The PHY configuration information may, for example, include instructions to perform patching on the PHY to operate at a higher speed. In some embodiments, the PHY configuration information may include information that identifies a patch application timing to the PHY, a PHY clock speed, and other information to configure the PHY. The PHY configuration information may, for example, be transferred from the memory system to the host device by the PHY while the PHY is operating at a speed of PWM-1 or HS-G1. The buffer may, in some embodiments, be a SoC buffer.In some embodiments, the buffer may be located in an original equipment manufacturer (OEM) customization data region of a memory. For example, the buffer may be located in a descriptor field data region. Petition 870250080096, dated 09 / 08 / 2025, p. 44 / 167 Configuration 39 / 70 allows the host device to program and / or lock any host-specific data. This buffer can be located in a read-only memory on the host device. The host device may be able to access such data with minimal latency at the start and during memory device initialization, such as at the beginning of a PBL initialization stage. For example, in some embodiments, such data may be accessible within 5 ms of the start of an initialization process. For instance, such data may be accessible by the host device before the host device begins reading from one or more memory system initialization LUNs. However, such data may be protected to prevent modifications after the device leaves the factory, and thus, this region may be marked as read-only.Storing PHY configuration data in a read-only memory buffer on the host device may, however, require an increased amount of read-only memory, which can increase the device cost.

[0077] As another example, the buffer may be located in non-volatile memory, such as flash memory, of the memory system. The buffer may be identified as SoC_BUFFER. The data stored in the buffer may be accessible at any time after an RST_n function is performed at the beginning of an initialization process. The buffer may be available for writing PHY configuration information, such as for writing one or more PHY patches, during a device provisioning phase using a write buffer command. The buffer may Petition 870250080096, dated 08 / 09 / 2025, page 45 / 167 40 / 70 can be subsequently locked using a bConfigDescrLock command, which can result in a read-only buffer. Such a buffer can provide low-latency access to PHY configuration information. In some embodiments, the latency of such a buffer can be lower than the latency of a buffer stored in NAND memory. As a particular example, the host can determine that a PHY configuration buffer in a system memory is supported when a mode variable is set to 02 and a buffer ID is set to F0h. PHY configuration information can be read from the buffer and by the host device using a read buffer command during initialization. In some embodiments, PHY configuration information can be read from the buffer and by the host device before system memory initialization is complete, such as the initialization of the flash memory in which the buffer is located.The PHY configuration information stored in the buffer may include information to adjust a PHY setting to operate at a higher speed. For example, the PHY configuration information may include information to perform patching on the PHY to operate at a higher speed supported by a UFS version of the memory system. In some embodiments, the buffer may include a library of PHY patches for different maximum PHY speeds, and a PHY patch may be selected based on a UFS version of the memory system. In some embodiments, the buffer label, commands, and functions may be labels, functions, and commands identified by the UFS standard. Petition 870250080096, dated 08 / 09 / 2025, page 46 / 167 41 / 70

[0078] In block 608, the PHY can be configured to operate at a second higher speed based on PHY configuration information. For example, a PHY configuration can be updated based on PHY configuration information stored in a buffer, such as the SoC buffer. For example, a PHY configuration can be updated to adjust a PHY speed from a first, slower speed, such as PWM-1 or HS-G1, to a higher speed, such as high-speed gear 2 (HS-G2), HS-G3, HS-G4, HS-G5, or another higher speed. Such an adjustment might, for example, include applying a patch to the PHY.

[0079] In block 610, a second link re-establishment procedure can be performed. For example, a link between the host device and the memory system can be re-established via the PHY.

[0080] In block 612, a gear change can be performed on the PHY and the PHY can start operating at the highest speed supported by the adjustment relative to the PHY configuration. For example, the PHY can start operating at a speed of HS-G2, HS-G3, HS-G4, HS-G5.

[0081] In block 614, a device query can be transmitted from the host device and received by the memory system, and the host device can receive a response from the memory system. Such operations may be similar to the operations described in block 508.

[0082] In block 616, the host device can read from one or more system boot LUNs of memory at the highest speed supported by the PHY, as per HSPetition 870250080096, dated 08 / 09 / 2025, page 47 / 167 42 / 70 G4.

[0083] In block 618, an fDeviceInit operation can be performed and a memory system initialization can be completed. In this way, PHY configuration information can be read from a memory system memory and the PHY can be configured to operate at a higher speed based on the PHY configuration information, before the memory system initialization is complete. For example, in the method described in relation to Figure 5, without the buffer containing PHY configuration information, the PHY may not operate at maximum speed until after the fDeviceInit operation is complete, whereas using a buffer containing PHY configuration information to update a PHY configuration, as described in relation to Figure 6, can allow the PHY to operate at a higher speed, such as HS-G4, even before the memory initialization that includes the buffer is complete.

[0084] In block 620, a device query can be transmitted from the host device and received by the memory system, and the host device can receive a response from the memory system. Such operations may be similar to the operations described in block 508.

[0085] In block 622, the host device can proceed with reading from all LUNs. For example, data can be read from all LUNs in the memory system at the highest supported speed. In this way, the use of PHY configuration information stored in a buffer to perform patching on a PHY to operate in Petition 870250080096, dated 08 / 09 / 2025, page 48 / 167 43 / 70 A higher speed at the start of the startup process can reduce startup time.

[0086] Figure 7 is a flowchart illustrating a method for updating a PHY configuration to operate at a high speed at the start of a startup process by a host controller, according to some embodiments of the disclosure. A method 700 includes, in block 702, the startup, by the host controller of a host device, of a PHY that connects the host device's memory controller to a memory system to operate at a first speed. For example, the host device, the PHY, and the memory system may be included in a SoC. A startup process for the host device may include the startup of the PHY and the memory system. The memory system may, for example, be a UFS memory system that includes one or more flash memories. The startup process may also be called a startup process.The PHY can, for example, be initialized after the completion of power-up and minimum memory system initialization to operate at a first speed. The first gear can, for example, be a low gear, such as a PWM-1 gear or HS-G1 speed. The initialization process can, for example, include a link start process, also called a link-start process, to initialize a link between the host device's memory controller and the memory system via the PHY. Such initialization can, for example, be performed by a host device PBL during a host device initialization PBL stage.

[0087] In block 704, the memory controller Petition 870250080096, dated 09 / 08 / 2025, p. 49 / 167 44 / 70 from the host device can transmit a PHY configuration information request to configure the PHY to operate at a second speed. For example, the memory controller can transmit a request, via the PHY, to the memory system for PHY configuration information to configure the PHY to operate at a second speed from a first memory system buffer. The PHY configuration information might, for example, include a PHY patch associated with a second speed, higher than the first speed. For example, the PHY configuration information might include higher gear parameters for PHY reconfiguration.As another example, PHY configuration information may include one or more post-silicon updates to a PHY configuration, such as updates to increase PHY speed, patch one or more PHY bugs, optimize the PHY for operation with a particular host device and / or memory system, or otherwise tune PHY operation. For example, PHY configuration information may include one or more PHY tuning parameters. The first buffer may, for example, be a SoC buffer stored in a memory system flash memory. The buffer may, for example, be a portion of memory in the memory system, such as flash memory allocated for use by the host device to store PHY configuration information and, in some embodiments, other information.Other information stored by the buffer may, for example, include other information for configuring the host device and / or SoC, such as information for use by the host device before initialization. Petition 870250080096, dated 08 / 09 / 2025, page 50 / 167 45 / 70 system memory is complete. For example, other information stored by the buffer may include SoC or host configuration information to enable or disable hardware or software interfaces and / or adjust other hardware or software configuration parameters. The buffer may, for example, include PHY configuration information to configure the PHY to operate at one or more speeds higher than the first speed, such as HS-G2, HS-G3, HS-G4, HS-G5, or another higher speed. In some embodiments, the request may, for example, include a read buffer command. Such a command may be used to access information stored in the buffer before the host device is fully initialized and after the host device is fully initialized. A buffer size may, for example, be 4 kB.In some embodiments, the buffer may store one or more PHY patches to perform patching on the PHY to operate at one or more higher speeds. In some embodiments, the request may specify a particular PHY patch to be retrieved from the buffer. For example, the request may specify a PHY patch to configure the PHY to operate at a higher speed supported by a UFS version of the memory system. Such a request may, for example, be transmitted via a host device PBL during a host device initialization PBL stage. In some embodiments, the buffer may be configured as read-only to prevent review of PHY configuration information. In some embodiments, the request may be transmitted after receiving a first NOP entry from the memory system and before transmitting a second one. Petition 870250080096, dated 08 / 09 / 2025, page 51 / 167 46 / 70 first device lookup for the memory system.

[0088] In some embodiments, the buffer can be updated using a write buffer command after the host device is fully initialized. For example, if a bConfigDescrLock variable is set to 00h, the memory system can process write buffer commands that set the buffer as the target. In some embodiments, however, the buffer can be locked and can be read-only. In such embodiments, the bConfigDescrLock variable can be set to a value of 01h and the memory system, as a memory controller of the memory system, can interrupt received write buffer commands that set the buffer as the target with a check condition status with a detection key variable set for data protection. In some embodiments, the buffer variables and commands can be the variables and commands identified by the UFS standard.

[0089] In block 706, the host device memory controller can receive PHY configuration information from the memory system. For example, the requested PHY configuration information can be received by the memory controller via the PHY that connects the host device memory controller to the memory system. The requested PHY configuration information can, for example, be received by a host device PBL during a host device initialization PBL stage.

[0090] In block 708, the host device's memory controller can adjust a PHY setting according to the PHY configuration information to operate. Petition 870250080096, dated 08 / 09 / 2025, page 52 / 167 47 / 70 at the second speed. For example, the memory controller can apply a patch of configuration information to the PHY to adjust a PHY setting so that the PHY starts operating at the second higher speed. The memory controller can then proceed to communicate with the memory system via the PHY at the second higher speed. The PHY configuration can, for example, be adjusted by a host device PBL during a host device initialization PBL stage. In some embodiments, the host device memory controller can be configured to complete memory system initialization, such as flash memory initialization which includes the buffer that stores PHY configuration information, after adjusting the PHY configuration to operate at the second speed.For example, part or all of an fDeviceInit operation can be performed and completed after the PHY configuration is updated to operate at the second speed. In this way, a PHY configuration can be updated to increase the PHY speed during a PBL phase of an initialization process, and the PHY can proceed to facilitate communication between the host device and the system memory at the higher speed during the PBL phase of the initialization process and during subsequent phases of the initialization process. The use of such a buffer can allow post-silicon updates to facilitate enhanced PHY speeds without requiring additional initialization read-only memory for the host device. Such a buffer can thus allow for an optimized initialization process, reduce initialization time, and allow for the storage of more gear parameters. Petition 870250080096, dated 08 / 09 / 2025, page 53 / 167 48 / 70 high and PHY reconfiguration to operate at higher speeds during the PBL initialization and bootloader stages. Including the buffer in the system memory can allow for optimization of the host device's boot read-only memory. For example, instead of requiring a new chip rotation when inefficiencies or read-only memory errors are found in the host device's read-only memory, the buffer can store patches in the ROM code to resolve errors and / or improve performance. Furthermore, such a buffer can be used to store one or more custom operations for one or more host device initialization stages.

[0091] Figure 8 is a flowchart illustrating an 800 method for updating a PHY configuration to operate at a high speed at the beginning of an initialization process by a flash memory system, according to some embodiments of the disclosure. The memory system can, for example, be connected to a memory controller of the host device via a PHY. The 800 method can be performed by a memory controller of the flash memory system. The 800 method includes, in block 802, receiving, by a memory controller of the memory system of a host device, after a PHY connecting the memory controller to the host device is initialized to operate at a first speed, a request for PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first buffer. The request can, for example, be the request described in relation to block 704 of Figure 7, and Petition 870250080096, dated 08 / 09 / 2025, page 54 / 167 49 / 70 The buffer can be a buffer that stores PHY configuration information, such as one or more PHY patches, as described in relation to Figure 7.

[0092] In block 804, the memory controller can transmit PHY configuration information to the host device. For example, the memory system's memory controller can transmit the requested PHY configuration information to update the PHY to a host device memory controller, as described in relation to block 706 of Figure 7. In this way, the memory controller can receive the request and can transmit the PHY configuration information before the memory system is fully initialized, such as before an fDeviceInit operation to the memory system is complete. The host device can then adjust a PHY configuration according to the PHY configuration information, so that the PHY is configured to operate at second speed. The host device can then proceed to communicate with the memory system's memory controller via the PHY at second speed.

[0093] The operations of method 500, method 600, method 700, or method 800 can be performed by a UE, such as a UE described with reference to Figure 9. For example, the example operations (also called blocks) of method 500, method 600, method 700, or method 800 can enable UE 915 to support greater confidentiality of user data. Figure 9 is a block diagram illustrating details of an example wireless communication system, according to one or more aspects. The wireless communication system may include a network Petition 870250080096, dated 08 / 09 / 2025, page 55 / 167 50 / 70 wireless 900. The 900 wireless network may, for example, include a 5G wireless network. As recognized by those skilled in the art, the components appearing in Figure 9 are likely to have related counterparts in other network arrangements, including, for example, cellular-style network arrangements and non-cellular-style network arrangements (e.g., device-to-device, or point-to-point, or ad hoc network arrangements, etc.).

[0094] The 900 wireless network illustrated in Figure 9 includes multiple 905 base stations and other network entities. A base station can be a station that communicates with the UEs and can also be called an evolved node B (eNB), a next-generation eNB (gNB), an access point, and the like. Each 905 base station can provide communication coverage for a particular geographic area. In the 3GPP (3rd Generation Partnership Project), the term cell can refer to this particular geographic coverage area of ​​a base station or a base station subsystem that serves the coverage area, depending on the context in which the term is used. In implementations of the 900 wireless network in the present invention, the 905 base stations may be associated with the same operator or different operators (for example, the 900 wireless network may include a plurality of operator wireless networks).Additionally, in implementations of the 900 wireless network of the present invention, the 905 base station can provide wireless communications using one or more of the same frequencies (for example, one or more frequency bands in the licensed spectrum, an unlicensed spectrum, or a combination thereof) as a cell. Petition 870250080096, dated 08 / 09 / 2025, page 56 / 167 51 / 70 neighbor. In some examples, an individual 905 base station or a 915 UE may be operated by more than one network operating entity. In some other examples, each of the 905 base station and the 915 UE may be operated by a single network operating entity.

[0095] A base station can provide communication coverage for a macrocell or a small cell, such as a picocell or a femtocell or other cell types. A macrocell generally covers a relatively large geographic area (e.g., a radius of several kilometers) and can allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a picocell, would generally cover a relatively smaller geographic area and could allow unrestricted access by UEs with service subscriptions with the network provider. A small cell, such as a femtocell, would also generally cover a relatively small geographic area (e.g., a house) and, in addition to unrestricted access, could also provide restricted access by UEs that have an association with the femtocell (e.g., UEs in a closed subscriber group (CSG), UEs for users in the home, and the like).A base station for a macrocell can be called a macrobase station. A base station for a small cell can be called a small cell base station, a picobase station, a femtobase station, or a domestic base station. In the example shown in Figure 9, base stations 905d and 905e can be regular macrobase stations, while base stations 905a to 905c can be macrobase stations enabled with one of the following: 3 dimensions (3D), full dimension. Petition 870250080096, dated 08 / 09 / 2025, page 57 / 167 52 / 70 (FD - full dimension) or massive MIMO. Base stations 905a to 905c take advantage of their higher dimension MIMO capabilities to exploit 3D beamforming in both elevation and azimuth beamforming to increase coverage and capacity. The 905f base station is a small cell base station that can be a home node or a portable access point. A base station can support one or multiple cells (e.g., two, three, four, and so on).

[0096] The 900 wireless network can support synchronous or asynchronous operation. For synchronous operation, base stations can have similar frame timing, and transmissions from different base stations can be approximately time-aligned. For asynchronous operation, base stations can have different frame timing, and transmissions from different base stations can be time-aligned. In some scenarios, networks can be enabled or configured to handle dynamic switching between synchronous and asynchronous operations.

[0097] The UEs 915 are spread throughout the 900 wireless network, and each UE can be stationary or mobile. It should be noted that, although a mobile device is commonly referred to as UE equipment in the standards and specifications promulgated by 3GPP, such equipment may additionally or otherwise be known by those skilled in the art as a mobile station (MS), a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, or a wireless communications device. Petition 870250080096, dated 09 / 08 / 2025, p. 58 / 167 53 / 70 wire, a remote device, a mobile subscriber station, an access terminal (AT), a mobile terminal, a wireless terminal, a remote terminal, a handset, a terminal, a user agent, a mobile client, a client, a gaming device, an augmented reality device, a vehicular component or vehicular module, or some other suitable terminology. Within the present document, a mobile or UE device does not necessarily need to have the ability to move, and may be stationary.Some non-limiting examples of a mobile device, which may include implementations of one or more of the UEs 915, include a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a laptop computer, a personal computer (PC), a notebook computer, a netbook, a smartbook, a tablet, and a personal digital assistant (PDA).A mobile device can additionally be an Internet of Things (IoT) or Internet of Everything (IoE) device, such as a motor vehicle or other transport vehicle, a satellite radio, a Global Positioning System (GPS) device, a Global Navigation Satellite System (GNSS) device, a logistics controller, an aviation device, a smart energy or security device, a solar panel or solar array, municipal lighting, water or other infrastructure; industrial automation and enterprise devices. Petition 870250080096, dated 08 / 09 / 2025, page 59 / 167 54 / 70 wearable and consumer devices, such as eyeglasses, a wearable camera, a smartwatch, a health or fitness tracker, a mammalian implantable device, a gesture tracking device, a medical device, a digital audio player (e.g., MP3 player), a camera, a game console, etc.; and digital or smart home devices, such as a home audio, video, and multimedia device, an appliance, a sensor, a vending machine, smart lighting, a home security system, a smart meter, etc. In one aspect, a UE may be a device that includes a universal integrated circuit card (UICC). In another aspect, a UE may be a device that does not include a UICC. In some respects, UEs that do not include UICCs may also be called IoE devices.The UEs 915a to 915d of the implementation illustrated in Figure 9 are examples of mobile smartphone-type devices accessing the 900 wireless network. A UE can also be a machine specifically configured for connected communication, including machine-type communication (MTC), enhanced machine-type communication (eMTC), narrowband Internet of Things (NB-IoT), and the like. The UEs 915e to 915k illustrated in Figure 9 are examples of various machines configured for communication that access the 900 wireless network.

[0098] A mobile device, such as the UEs 915, may be able to communicate with any type of base station, whether macro base stations, pico base stations, femto base stations, repeaters, and the like. In Figure 9, a Petition 870250080096, dated 08 / 09 / 2025, page 60 / 167 The 55 / 70 communication link (represented as a lightning bolt) indicates wireless transmissions between a UE and a serving base station, which is a base station designated to serve the UE with respect to the downlink or uplink, or desired transmission between base stations and backhaul transmissions between base stations. UEs can operate as base stations or other network nodes in some scenarios. Backhaul communication between base stations in the 900 wireless network can occur using wired or wireless communication links.

[0099] Operating on the 900 wireless network, base stations 905a to 905c serve UEs 915a and 915b using 3D beamforming and coordinated spatial techniques, such as coordinated multipoint (CoMP) or multiconnectivity. Macro base station 905d performs backhaul communications with base stations 905a to 905c, as well as small cells, base station 905f. Macro base station 905d also transmits multicast services that are subscribed to and received by UEs 915c and 915d. Such multicast services may include mobile television or video streaming, or may include other services to provide community information, such as weather alerts or emergencies, such as Amber alerts or grey alerts.

[00100] The 900 wireless network deployments support mission-critical communications with ultra-reliable and redundant links to mission-critical devices such as the UE 915e, which is an aircraft vehicle. The redundant communication links with the UE 915e include macro base stations 905d and 905e, as well as a base station of Petition 870250080096, dated 08 / 09 / 2025, page 61 / 167 56 / 70 small cell 905f. Other machine-type devices, such as the UE 915f (a thermometer), the UE 915g (smart meter), and the UE 915h (e.g., wearable device), can communicate via the 900 wireless network directly with base stations, such as the small cell base station 905f and the macro base station 905e, or in multi-hop configurations by communicating with another user device that relays its information to the network, such as the UE 915f communicating temperature measurement information to the smart meter, the UE 915g, which is then reported to the network via the small cell base station 905f.The 900 wireless network can also provide additional network efficiency through dynamic, low-latency time division duplexing (TDD) communications or low-latency frequency division duplexing (FDD) communications, such as in a vehicle-to-vehicle (V2V) mesh network between the 915i to 915k UEs communicating with the 905e macro base station.

[00101] In various implementations, techniques and devices can be used for wireless communication networks, such as code division multiple access (CDMA) networks, time division multiple access (TDMA) networks, frequency division multiple access (FDMA) networks, orthogonal frequency division multiple access (OFDMA) networks, single-carrier frequency division multiple access (SC-FDMA) networks, long-term evolution (LTE) networks, and global system networks for communication. Petition 870250080096, dated 08 / 09 / 2025, page 62 / 167 5G mobile (GSM), 5th generation (5G) or New Radio (NR) networks (sometimes referred to as 5G NR networks, systems or devices), as well as other communication networks. As described in the present invention, the terms networks and systems can be used interchangeably. A CDMA network, for example, may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), CDMA2000 and the like. UTRA includes wideband CDMA (W-CDMA) and low chip rate (LCR). CDMA2000 encompasses the IS-2000, IS-95 and IS-856 standards. A TDMA network may, for example, implement a radio technology such as the Global System for Mobile Communication (GSM). The Third Generation Partnership Project (3GPP) defines standards for GSM EDGE (enhanced data rates for GSM evolution), a radio access network (RAN), also called GERAN.An OFDMA network can implement radio technologies such as evolved universal terrestrial radio access (E-UTRA), Institute of Electrical and Electronics Engineers (IEEE) 802.11, IEEE 802.16, IEEE 802.20, flash-OFDM, and similar technologies. UTRA, E-UTRA, and GSM are part of the Universal Mobile Telecommunication System (UMTS). In particular, Long Term Evolution (LTE) is a version of UMTS that uses E-UTRA. The various different network types can use different radio access technologies (RATs) and RANs.

[00102] Although aspects and implementations are described in this application by way of illustration with some examples, the Petition 870250080096, dated 08 / 09 / 2025, page 63 / 167 58 / 70 people skilled in the art will understand that additional implementations and specific use cases may arise in many different arrangements and scenarios. The innovations described in the present invention can be implemented in many different types of platforms, devices, systems, formats, sizes, and packaging arrangements. For example, implementations or uses may occur via chip implementations or other non-module and component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail devices, shopping devices, medical devices, AI-enabled devices, etc.). While some examples may or may not be specifically targeted to use cases or applications, there may be a wide range of applicability of the innovations described.Implementations can range from chip-level or modular components to non-modular, non-chip-level implementations that additionally incorporate distributed devices or original equipment manufacturers (OEMs) or systems that incorporate one or more of the described aspects. In some practical environments, devices incorporating the described aspects and attributes may necessarily also include other components and attributes for the implementation and practice of the claimed and described aspects. It is intended that the innovations described in the present invention can be practiced in a wide variety of implementations, including both large and small devices, chip-level components, multi-component systems (e.g., radio frequency (RF) chain), etc. Petition 870250080096, dated 08 / 09 / 2025, page 64 / 167 59 / 70 communication interface, processor), distributed layouts, end-user devices, etc., of varying sizes, shapes and constitution.

[00103] In one or more aspects, the techniques for supporting data storage and / or data transmission may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more of the other processes or devices described elsewhere in the present invention. In one aspect, an electronic device, such as a UE, may be an apparatus, such as a host device that includes a memory controller configured to couple, via a physical interface (PHY), to a memory system, wherein the memory system may be integrated with the host device or externally coupled to the host device.The memory system may include a memory controller coupled to a memory system via a first channel and configured to access data stored in the memory system via the first channel, and coupled to a host device via a first interface, such as a PHY, and configured to communicate with the host device via the first interface. Operations may be performed as part of a startup operation, a read operation, or a write operation.

[00104] In one aspect, the memory controller of the memory system can be configured to perform operations that include receiving, from the host device, after the PHY is initialized to operate at a first speed, a request for PHY configuration information to configure the PHY to operate at a second speed. Petition 870250080096, dated 08 / 09 / 2025, page 65 / 167 60 / 70 speed, higher than the first speed, of a first buffer of the memory module and transmit the PHY configuration information to the host device.

[00105] In a second aspect, in combination with the first aspect, the first buffer is located in a flash memory of the memory module.

[00106] In a third aspect, in combination with one or more of the first or second aspects, the transmission of PHY configuration information is performed before the flash memory initialization is complete.

[00107] In a fourth aspect, in combination with one or more of the first to third aspects, the PHY is initialized to operate at the first speed during a host device initialization link initialization stage.

[00108] In a fifth aspect, in combination with one or more of the first to fourth aspects, the PHY configuration information comprises a PHY patch associated with the second speed.

[00109] In a sixth aspect, in combination with one or more of the first to fifth aspects, the buffer stores a plurality of PHY patches associated with a plurality of speeds.

[00110] In a seventh aspect, in combination with one or more of the first to sixth aspects, the first buffer is configured as read-only.

[00111] In an eighth aspect, the host device's memory controller can be configured to perform operations that include initializing the PHY to operate. Petition 870250080096, dated 09 / 08 / 2025, p. 66 / 167 61 / 70 at a first speed, receive PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first memory system buffer and adjust a PHY setting according to the PHY configuration information to operate at the second speed.

[00112] In a ninth aspect, in combination with the eighth aspect, the first buffer is located in a flash memory of the memory system.

[00113] In a tenth aspect, in combination with one or more of the eighth to ninth aspects, the memory controller is additionally configured to complete flash memory initialization after adjusting the PHY configuration.

[00114] In an eleventh aspect, in combination with one or more of the eighth to tenth aspects, the initialization of the PHY to operate at the first speed comprises completing a link initialization stage of the host device initialization.

[00115] In a twelfth aspect, in combination with one or more of the eighth to eleventh aspects, the memory system's memory controller may be further configured to perform operations that include transmitting, after initializing the PHY to operate at first speed, a request for PHY configuration information to the memory system.

[00116] In a thirteenth aspect, in combination with one or more of the eighth to twelfth aspects, the PHY configuration information comprises a PHY patch associated with the second speed, Petition 870250080096, dated 09 / 08 / 2025, p. 67 / 167 62 / 70 and where adjusting the PHY configuration involves applying the PHY patch.

[00117] In a fourteenth aspect, in combination with one or more from the eighth to the thirteenth aspect, the buffer stores a plurality of PHY patches associated with a plurality of speeds.

[00118] In a fifteenth aspect, in combination with one or more of the eighth to fourteenth aspects, the first buffer is configured as read-only.

[00119] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the description above can be represented by voltages, currents, electromagnetic waves, magnetic particles or fields, optical particles or fields, or any combination thereof.

[00120] The components, functional blocks, and modules described in the present invention in relation to Figures 1 to 8 include processors, electronic devices, hardware devices, electronic components, logic circuits, memories, software code, firmware code, among other examples, or any combination thereof. Software should be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, Petition 870250080096, dated 08 / 09 / 2025, page 68 / 167 63 / 70 applications, software applications, software packages, routines, subroutines, objects, executable portions, execution threads, procedures and / or functions, among other examples, whether called software, firmware, middleware, microcode, hardware description language or otherwise. Furthermore, the attributes discussed in the present invention can be implemented by means of a set of specialized processor circuits, via executable instructions, or combinations thereof.

[00121] Those skilled in the art know that one or more blocks (or operations) described with reference to Figures 4A to 4E, 5, 6, 7, or 8 can be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks (or operations) in Figure 1 can be combined with one or more blocks (or operations) in Figure 3. As another example, one or more blocks associated with Figure 1 can be combined with one or more blocks (or operations) associated with Figures 4A to 4E, 5, 6, 7, or 8. Additionally or alternatively, one or more operations described above with reference to Figures 1 to 3 can be combined with one or more operations described with reference to Figures 4 to 8.

[00122] Those skilled in the art will further recognize that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the present disclosure in the present invention can be implemented in the form of electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various components, blocks, modules, circuits, and steps Petition 870250080096, dated 08 / 09 / 2025, page 69 / 167 The 64 / 70 illustrative examples described above in terms of their functionality have been shown. The possibility of such functionality being implemented as hardware or software depends on the particular application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a deviation from the scope of the present disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described in the present invention are merely examples, and that the components, methods, or interactions of the various aspects of the present disclosure may be combined or implemented in ways different from those illustrated and described in the present invention.

[00123] Different illustrative logics, logic blocks, modules, circuits, and algorithm processes described in connection with the implementations disclosed in the present invention may be implemented in the form of electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described in general terms of functionality and illustrated in the various components, blocks, modules, circuits, and illustrative processes described above. Whether such functionality will be implemented in hardware or software depends on the particular application and the design limitations imposed on the system as a whole.

[00124] The hardware and data processing equipment used to implement the various logics Petition 870250080096, dated 08 / 09 / 2025, page 70 / 167 65 / 70 illustrative, logic blocks, modules and circuits described in connection with the aspects disclosed in the present invention may be implemented or realized with a general-purpose processor with a single chip or multiple chips, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described in the present invention. The general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller or state machine.In some implementations, a processor can be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors together with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by a set of circuits that is specific to a given function.

[00125] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this descriptive report and their structural equivalents, or in any combination thereof. Implementations of the subject matter described in this descriptive report may also be Petition 870250080096, dated 08 / 09 / 2025, page 71 / 167 66 / 70 implemented as one or more computer programs, which are one or more modules of computer program instructions, encoded in computer storage media for execution by, or to control the operation of, a data processing device.

[00126] If implemented in software, the functions can be stored or transmitted in the form of one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed in the present invention can be implemented in a processor-executable software module, which may reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any means that can be enabled to transfer a computer program from one place to another. Storage media can be any available media that can be accessed by a computer.By way of example, and not limitation, such computer-readable media may include random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures, and that can be accessed by a computer. Furthermore, any connection may properly be called a computer-readable medium. Disks. Petition 870250080096, dated 08 / 09 / 2025, page 72 / 167 67 / 70 (disk and disc), as used in the present invention, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically by means of lasers. Combinations of the above items should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one, or any, combination or set of codes and instructions in machine-readable and computer-readable media, which may be incorporated into a computer program product.

[00127] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined in the present invention may be applied to some other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown in the present invention, but rather to be given the broadest scope consistent with the present disclosure, the principles and the innovative attributes disclosed in the present invention.

[00128] Additionally, a person skilled in the art will readily recognize that opposite terms such as top and bottom, or front and back, or top and bottom, or front and back are sometimes used for ease of description of figures and indicate relative positions corresponding to the orientation of the figure on a properly oriented page and may not reflect the Petition 870250080096, dated 08 / 09 / 2025, page 73 / 167 68 / 70 proper orientation of any device, as implemented.

[00129] Certain attributes described in this descriptive report, in the context of separate implementations, may also be implemented in combination in a single implementation. Conversely, several attributes described in the context of a single implementation may also be implemented separately in multiple implementations, or in any suitable subcombination. Furthermore, although attributes may be described above as acting in certain combinations and even initially claimed in that way, one or more attributes of a claimed combination may, in some cases, be removed from the combination, and the claimed combination may be directed to a subcombination or a variation of a subcombination.

[00130] Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order depicted or in sequential order, or that all illustrated operations be performed in order to achieve desirable results. Additionally, the drawings may schematically depict one or more example processes in the form of a flow diagram. However, other operations not depicted may be incorporated into the example processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. Under certain circumstances, processing in Petition 870250080096, dated 08 / 09 / 2025, page 74 / 167 Parallel or multitasking implementations (69 / 70) may be advantageous. Furthermore, the separation of various system components in the implementations described above should not be understood as a requirement for such separation in all implementations, and it should be understood that the described program and system components can generally be integrated into a single software product or provided as packages in multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions mentioned in the claims can be performed in a different order and still achieve the desired results.

[00131] As used in the present invention, including in the claims, the term "or," when used in a list of two or more items, means that any one of the items mentioned may be used alone, or any combination of two or more of the items mentioned may be used. For example, if a composition is described as containing components A, B, or C, the composition may contain only A; only B; only C; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination. Also as used in the present invention, including in the claims, "or," as used in a list of items preceded by "at least one of," indicates a disjunctive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (that is, A and B and C), or any of these in any combination thereof.The term substantially defined as broadly, but not necessarily entirely, what is specified (and includes). Petition 870250080096, dated 08 / 09 / 2025, page 75 / 167 70 / 70 as specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel), as understood by a person skilled in the art. In any disclosed implementations, the term substantially may be replaced by within [a percentage] of what is specified, where the percentage includes 0.1, 1, 5, or 10 percent.

[00132] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined in the present invention can be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described in the present invention, but rather to be given the broadest scope consistent with the innovative principles and attributes disclosed in the present invention. Petition 870250080096, dated 09 / 08 / 2025, p. 76 / 167

Claims

1 / 6 CLAIMS 1. Apparatus characterized by comprising: a memory controller of a host device configured to couple the host device to a memory system through a physical layer interface (PHY), wherein the memory controller is configured to perform operations that include: initializing the PHY to operate at a first speed; receiving PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first memory system buffer; and adjusting a PHY configuration according to the PHY configuration information to operate at the second speed.

2. Device according to claim 1, characterized in that the first buffer is located in a flash memory of the memory system.

3. Device according to claim 2, characterized in that the memory controller is additionally configured to complete flash memory initialization after adjusting the PHY configuration.

4. Device according to claim 3, characterized in that the PHY initialization to operate at the first speed comprises completing a link initialization stage of the host device initialization.

5. Device, according to claim 1, characterized in that the memory controller is further configured to perform operations that include: transmitting, after initializing the PHY to operate at first speed, a request for PHY configuration information to the memory system.

6. Device according to claim 1, characterized in that the PHY configuration information comprises a PHY patch associated with the second speed and the PHY configuration adjustment comprises applying the PHY patch.

7. Device according to claim 6, characterized in that the buffer stores a plurality of PHY patches associated with a plurality of speeds.

8. Device according to claim 1, characterized in that the first buffer is configured as read-only.

9. A method characterized by comprising: initializing, by a memory controller of a host device, a physical interface (PHY) to connect the host device to a memory system to operate at a first speed; receiving PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first buffer of the memory system; and adjusting, by the memory controller, a PHY configuration according to the PHY configuration information to operate at the second speed.

10. Method, according to claim 9, characterized in that the first buffer is located in a system memory flash memory.

11. Method according to claim 10, characterized by further comprising completing the flash memory initialization after adjusting the PHY configuration.

12. Method, according to claim 11, characterized in that the initialization of the PHY to operate at the first speed comprises completing a link initialization stage of the host device initialization.

13. Method according to claim 9, characterized by further comprising: transmitting, after initializing the PHY to operate at first speed, a request for PHY configuration information to the memory system.

14. A method according to claim 9, characterized in that the PHY configuration information comprises a PHY patch associated with the second speed and the PHY configuration adjustment comprises applying the PHY patch.

15. Method according to claim 14, characterized in that the buffer stores a plurality of PHY patches associated with a plurality of speeds.

16. Method according to claim 9, characterized in that the first buffer is configured as read-only.

17. Device characterized by comprising: a memory controller: coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel; and coupled to a host device through a first physical interface (PHY) and configured to communicate with the host device through the first PHY, wherein the memory controller is configured to perform operations comprising: receiving, from the host device, after the PHY is initialized to operate at a first speed, a request for PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first buffer of the memory module; and transmitting the PHY configuration information to the host device.

18. Device according to claim 17, characterized in that the first buffer is located in a flash memory of the memory module.

19. Device according to claim 18, characterized in that the transmission of PHY configuration information is performed before the flash memory initialization is complete.

20. Device according to claim 19, characterized in that the PHY is initialized to operate at the first speed during a link initialization stage of the host device.

21. Device according to claim 17, characterized in that the PHY configuration information comprises a PHY patch associated with the second speed.

22. Device according to claim 21, characterized in that the buffer stores a plurality of PHY patches associated with a plurality of speeds.

23. Device according to claim 17, characterized in that the first buffer is configured as read-only.

24. A method characterized by comprising: receiving, in a memory controller of a host device, after a physical interface (PHY) connecting the memory controller to the host device is initialized to operate at a first speed, a request for PHY configuration information to configure the PHY to operate at a second speed, higher than the first speed, from a first buffer of a memory module coupled to the memory controller; and transmitting, through the memory controller, the PHY configuration information to the host device.

25. Method according to claim 24, characterized in that the first buffer is located in a flash memory of the memory module.

26. Method according to claim 25, characterized in that the transmission of PHY configuration information is performed before the flash memory initialization is complete.

27. Method according to claim 26, characterized in that the PHY is initialized to operate at the first speed during a link initialization stage of the host device initialization.

28. Method according to claim 24, characterized in that the PHY configuration information comprises a PHY patch associated with the second speed.

29. Method according to claim 28, Petition 870250080096, dated 08 / 09 / 2025, p. 152 / 167 6 / 6 characterized in that the buffer stores a plurality of PHY patches associated with a plurality of speeds.

30. Method according to claim 24, characterized in that the first buffer is configured as read-only. Petition 870250080096, dated 09 / 08 / 2025, pp. 153 / 167

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