DISPLAY DEVICE

Abstract

A display device according to an embodiment comprises: a substrate including a display area and a non-display area; a transistor disposed on the display area of the substrate and including a semiconductor layer; and at least one inspection pattern disposed on the non-display area of the substrate and including a semiconductor pattern, wherein: the inspection pattern includes a first conductive pattern and a second conductive pattern spaced apart in a thickness direction with the semiconductor pattern interposed therebetween, an inspection source electrode connected to a portion of the semiconductor pattern, and an inspection drain electrode connected to another portion of the semiconductor pattern; and the second conductive pattern is in contact with the semiconductor pattern.

Description

1 / 57 DISPLAY DEVICE FIELD OF TECHNIQUE

[001] The present invention relates to a display device. BACKGROUND OF THE TECHNIQUE

[002] As the information society develops, the demand for a display device to show an image is increasing in various forms. For example, the display device has been applied to various electronic devices, such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions.

[003] The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, or a light-emitting display device. The light-emitting display device includes an organic light-emitting display device, which includes an organic light-emitting element, an inorganic light-emitting display device, which includes an inorganic light-emitting element, such as an inorganic semiconductor, and a subminiature light-emitting display device, which includes a subminiature light-emitting element.

[004] The organic light-emitting element may include two opposing electrodes and a light-emitting layer interposed between them. The light-emitting layer receives electrons and holes from the two electrodes and recombines the electrons and holes to generate excitons, and the generated excitons change from an excited state to a ground state, thereby emitting light.

[005] The organic light-emitting display device, which includes the organic light-emitting element, can be configured in a lightweight and thin form, with low power consumption, as it does not require a light source, such as a backlight unit, and tam Petition 870250081403, dated 10 / 09 / 2025, page 7 / 90 2 / 57 also attracted attention as a next-generation display device due to its high-quality features, such as a wide viewing angle, high luminance and contrast, and fast response speed. TECHNICAL PROBLEM DESCRIPTION

[006] Aspects of the present invention provide a display device capable of managing thin-film transistor characteristics in a display area using an inspection pattern placed over a non-display area.

[007] However, aspects of the present invention are not limited to those presented here. The above and other aspects of the present invention will become more apparent to one skilled in the art to which the present invention pertains, by referring to the detailed description of the present invention given below. TECHNICAL SOLUTION

[008] According to one aspect of the present invention, a display device comprises a substrate that includes a display area and a non-display area, a transistor disposed on the display area of ​​the substrate and which includes a semiconductor layer, and at least one inspection pattern disposed on the non-display area of ​​the substrate and which includes a semiconductor pattern, wherein the inspection pattern includes a first conductive pattern and a second conductive pattern spaced from each other in a thickness direction with the semiconductor pattern interposed between them, and an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to the other portion of the semiconductor pattern, and the second conductive pattern is in contact with the semiconductor pattern.

[009] The first conductor standard still includes a first ca Petition 870250081403, dated 10 / 09 / 2025, page 8 / 90 3 / 57 an insulating layer and a second insulating layer that are placed on the substrate and interposed between the semiconductor pattern and the first conductive pattern.

[0010] The semiconductor pattern includes a pattern channel region and a first conductive region and a second conductive region spaced apart with the pattern channel region interposed between them.

[0011] The first conductive pattern overlaps the channel region of the pattern.

[0012] The inspection source electrode is connected to the first conductive area, and the inspection drain electrode is connected to the second conductive area.

[0013] The second conductive pattern is arranged in the semiconductor pattern and superimposed on the first conductive pattern.

[0014] The display device further comprises a third insulating layer disposed between the second conductor pattern and the semiconductor pattern, wherein the second conductor pattern is in contact with the semiconductor pattern through a first wayhole that penetrates through the third insulating layer.

[0015] The display device further comprises a fourth insulating layer disposed between the inspection source electrode and the inspection drain electrode, and the second conductive pattern, wherein the inspection source electrode and the inspection drain electrode are connected to the semiconductor pattern through a second via hole and a third via hole that penetrates through the fourth insulating layer.

[0016] The display device further comprises a fourth insulating layer disposed over the second conductive pattern and a first inspection electrode, a second inspection electrode, a third inspection electrode and a fourth inspection electrode disposed Petition 870250081403, dated 10 / 09 / 2025, page 9 / 90 4 / 57 on the fourth insulating layer and spaced apart from each other.

[0017] The first inspection electrode is connected to the first conductor standard and the second inspection electrode is connected to the second conductor standard.

[0018] The third inspection electrode extends from the inspection source electrode and the fourth inspection electrode extends from the inspection drain electrode.

[0019] The transistor semiconductor layer in the display area includes the same material as the semiconductor standard of the inspection standard.

[0020] The transistor semiconductor layer in the display area and the semiconductor pattern of the inspection pattern include an oxide semiconductor.

[0021] The display device further comprises a connection pattern disposed between the first conductor pattern and the semiconductor pattern, wherein the first conductor pattern is electrically connected to the semiconductor pattern through the connection pattern.

[0022] According to one aspect of the present invention, a display device comprises a substrate that includes a display area and a non-display area, a transistor disposed on the display area of ​​the substrate and which includes a semiconductor layer, and an inspection pattern disposed on the non-display area of ​​the substrate and which includes a semiconductor pattern, wherein the inspection pattern includes a first conductive pattern and a second conductive pattern spaced apart in a thickness direction with the semiconductor pattern interposed between them, an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to the other portion of the semiconductor pattern, and a connection pattern disposed between the first conductive pattern and the semiconductor pattern, and the connection pattern Petition 870250081403, dated 10 / 09 / 2025, page 10 / 90 5 / 57 is in contact with the first conductor standard and the semiconductor standard.

[0023] The transistor semiconductor layer in the display area and the semiconductor pattern of the inspection pattern include an oxide semiconductor.

[0024] The display device further comprises a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductor pattern, wherein the connection pattern is disposed in a first via hole that penetrates through the first insulating layer and the second insulating layer, and the first via hole overlaps the first conductor pattern and the semiconductor pattern.

[0025] The semiconductor pattern includes a pattern channel region, a first conductive region and a second conductive region spaced apart from each other, with the pattern channel region interposed between them, and the connection pattern is in contact with the pattern channel region.

[0026] The first conductor pattern, the second conductor pattern, and the connection pattern overlap the pattern channel region of the semiconductor pattern.

[0027] The display device further comprises a third insulating layer disposed between the first conductive pattern and the second conductive pattern, wherein the second conductive pattern is spaced from the semiconductor pattern.

[0028] Other features and configurations may be apparent from the detailed description and drawings that follow. ADVANTAGEOUS EFFECTS

[0029] The display device, according to one embodiment, can infer the hydrogen content of a semiconductor layer of a pixel transistor in a display area by forming a Petition 870250081403, dated 10 / 09 / 2025, page 11 / 90 6 / 57 inspection pattern that includes placing a semiconductor pattern in a non-display area and measuring the capacitance of the semiconductor pattern. Consequently, the quality of the display device can be improved by monitoring the characteristics of the pixel transistors of the display device.

[0030] The effects, according to the modalities, are not limited by the content exemplified above, and several more effects are included in this description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a plan view illustrating a display device, according to an embodiment;

[0032] Figure 2 is a plan view illustrating a display panel of Figure 1;

[0033] Figure 3 is a circuit diagram that illustrates a pixel according to a mode;

[0034] Figure 4 is a circuit diagram that illustrates a PX pixel according to a mode;

[0035] Figure 5 is a cross-sectional view illustrating a display panel 110 according to an embodiment;

[0036] Figure 6 is a plan view that illustrates an inspection pattern according to a modality;

[0037] Figure 7 is a cross-sectional view taken along line Q1-Q1' of Figure 6;

[0038] Figure 8 is a graph that illustrates the changes in the characteristics of a transistor depending on the hydrogen content of a semiconductor layer;

[0039] Figure 9 is a graph that illustrates the changes in the characteristics of a transistor that has a hydrogen-free semiconductor layer;

[0040] Figure 10 is a graph that illustrates the changes in the characteristics Petition 870250081403, dated 10 / 09 / 2025, page 12 / 90 7 / 57 characteristics of a transistor that has a semiconductor layer containing hydrogen;

[0041] Figure 11 is a graph that illustrates the capacitance of a semiconductor standard as a function of frequency;

[0042] Figure 12 is a cross-sectional view illustrating an inspection pattern of a display device according to another embodiment;

[0043] Figure 13 is a cross-sectional view illustrating an inspection pattern of a display device according to yet another embodiment; and

[0044] Figure 14 is a plan view illustrating a display panel according to yet another embodiment. MODES OF INVENTION

[0045] The present invention will now be described in more detail hereafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be interpreted as limited to the embodiments presented herein. Rather, these embodiments are provided so that this description is extensive and complete, and fully conveys the scope of the invention to those skilled in the art.

[0046] It will also be understood that when a layer is referred to as being on top of another layer or substrate, it may be directly on top of the other layer or substrate, or intervening layers may also be present. The same part numbers indicate the same components throughout the specification.

[0047] It will be understood that, although the terms first, second, etc. may be used here to describe various elements, these elements should not be limited by these terms. These Petition 870250081403, dated 10 / 09 / 2025, p. 13 / 90 8 / 57 terms are used only to distinguish one element from another element. For example, a first element discussed below could be called a second element without departing from the teachings of the present invention. Similarly, the second element could also be called a first element.

[0048] Hereafter, exemplary embodiments of the present invention will be described with reference to the drawings.

[0049] Figure 1 is a plan view illustrating a display device according to an embodiment. Figure 2 is a plan view illustrating a display panel of Figure 1.

[0050] Referring to Figures 1 and 2, a display device 10 is a device that displays a moving image or a static image, and can be used as a display screen for each of several products, such as a television, a laptop computer, a monitor, a billboard and an Internet of Things (IoT) device, as well as portable electronic devices, such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watch phone, a mobile communication terminal, an electronic organizer, an e-book, a portable multimedia player (PMP), a navigation device and an ultra-mobile PC (UMPC). These are presented merely as examples, and the display device 10 can also be employed in other electronic devices.

[0051] In one embodiment, the display device 10 may be a light-emitting display device, such as an organic light-emitting display device utilizing an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro or nano device. Petition 870250081403, dated 10 / 09 / 2025, page 14 / 90 9 / 57 light-emitting display that utilizes a micro or nano light-emitting diode (LED), but is not limited to these. For example, display device 10 may be a type of display device other than a light-emitting display device. Hereafter, embodiments in which display device 10 is an organic light-emitting display device will be described.

[0052] The display device 10 may include a display panel 110 which includes PX pixels and a first driver 120 and a second driver 130 which supply drive signals to the PX pixels. The display device 10 may also include additional components. For example, the display device 10 may also include a power supply unit to supply power voltages to the PX pixels, the first driver 120 and the second driver 130, and a timing control unit to control the operations of the first driver 120 and the second driver 130.

[0053] Display panel 110 may include a DA display area and a NDA non-display area. The DA display area may be an area that includes the PX pixels and displays an image. The NDA non-display area is the remaining area, excluding the DA display area, and an image may not be displayed in the NDA non-display area. In one embodiment, the NDA non-display area may be positioned around the DA display area and encircle the DA display area.

[0054] In Figures 1 and 2, a first direction DR1, a second direction DR2, and a third direction DR3 can be defined. In one embodiment, the first direction DR1 and the second direction DR2 can be perpendicular to each other, the first direction DR1 and the third direction DR3 can be perpendicular to each other, and the second direction DR2 and the third direction DR3 can be perpendicular to each other. For example, the first direction DR1 can be a horizontal direction of the display panel 110, and the second direction DR2 Petition 870250081403, dated 10 / 09 / 2025, page 15 / 90 10 / 57 can be a vertical direction of the 110 display panel. The third direction, DR3, can be a thickness direction of the 110 display panel.

[0055] In one embodiment, the display panel 110 may have a rectangular shape in plan view. For example, the display panel 110 may include two first sides extending in the first direction DR1 and two second sides extending in the second direction DR2, intersecting the first direction DR1. Figures 1 and 2 illustrate a display panel 110 in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel 110 is not limited to this. For example, the display panel 110 may also have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or a shape in which the first and second sides are substantially the same length.

[0056] In one embodiment, display panel 110 may include a slanted corner in a portion where the first side and second side meet, but is not limited to this. For example, display panel 110 may also include a rounded corner in a portion where the first side and second side meet.

[0057] The planar form of display panel 110 is not limited to the rectangular form illustrated, and other forms may also be applied. For example, display panel 110 may have a square form, another non-square polygonal form, a circular form, an oval form, an irregular form, or another form in plan view.

[0058] In one embodiment, the display panel 110 may be substantially flat in a plane defined by the first direction DR1 and the second direction DR2 and may have a uniform thickness in the third direction DR3. In another embodiment, the display panel Petition 870250081403, dated 10 / 09 / 2025, page 16 / 90 11 / 57 110 can also be provided in a three-dimensional form having a curved surface, etc.

[0059] The display panel 110 may be provided as a panel with rigid characteristics so as not to be substantially deformed, or it may be provided as a flexible panel that may be deformed in a way such as being bent, curved or rolled up at least in a portion. The display panel 110 may be provided to the display device 10 in an unfolded state or it may be provided in a state bent in some sections.

[0060] Display panel 110 may include a SUB substrate and PX pixels arranged on the SUB substrate. The PX pixels may be arranged in the DA display area on the SUB substrate.

[0061] The SUB substrate is a base member for the manufacture or provision of the display panel 110 and may form a base surface of the display panel 110. The SUB substrate may include a display area DA and a non-display area NDA positioned around the display area DA.

[0062] The DA display area can have various shapes depending on the embodiment. For example, the DA display area can have a square shape, another non-square polygonal shape, a circular shape, an oval shape, an irregular shape, or another shape. In one embodiment, the DA display area can have a shape that corresponds to the shape of display panel 110, but is not limited to this.

[0063] The DA display area may include pixel areas in which PX pixels are provided and / or arranged. For example, each PX pixel may be arranged in each pixel area positioned in the DA display area. In one embodiment, the display device 10 may be a light-emitting display device, and each PX pixel may include a light-emitting element positioned in each area. Petition 870250081403, dated 10 / 09 / 2025, page 17 / 90 12 / 57 light emitting element and a pixel circuit connected to the light-emitting element. When describing the embodiments, connection may include electrical connection and / or physical connection.

[0064] In each pixel area, a light-emitting element of the corresponding pixel is positioned, and each pixel area may include a light-emitting area in which the pixel emits light and a pixel circuit area in which the circuit elements that constitute a pixel circuit of the corresponding pixel are positioned. In one embodiment, the light-emitting area and the pixel circuit area of ​​each PX pixel may overlap each other, but are not limited to this.

[0065] PX pixels can be arranged in the DA display area. For example, PX pixels can be arranged in the DA display area in a strip structure, delta structure, PenTile™ structure, or other arrangement structure.

[0066] The non-display NDA area may include a driver circuit area positioned on at least one side of the display DA area and a PA block area in which the PD blocks are arranged. At least one driver, PD blocks and / or lines may be arranged in the non-display NDA area.

[0067] At least one driver for actuating the PX pixels, or a portion of the driver, may be disposed on the drive circuit area. As an example, the circuit elements that constitute the first driver 120 may be disposed on the drive circuit area on the SUB substrate. In one embodiment, the circuit elements of the first driver 120 may be formed on the display panel 110 together with the PX pixels.

[0068] PD blocks may be arranged in the PA block area. At least one 140 circuit board may be arranged and / or connected in the PA block area. In one embodiment, a plurality of boards Petition 870250081403, dated 10 / 09 / 2025, page 18 / 90 13 / 57 of circuit 140 connected to different PD blocks can be arranged over the PA block area. The PD blocks may include signal blocks and power blocks to transmit drive signals and power voltages needed to drive the PX pixels and / or the first driver 120 into the display panel 110.

[0069] The first driver 120 and the second driver 130 can generate drive signals to control the operating time and luminance of the PX pixels and supply the drive signals to the PX pixels. For example, the first driver 120 can be a gate driver, which includes a scan driver, and can be connected to the PX pixels via the respective gate line. The first driver 120 can supply the respective gate signals (e.g., drive signals that control the operating time of the PX pixels, including a first GW gate signal in Figure 3) to the PX pixels. The second driver 130 can be a data driver, which includes source driver circuitry, and can be connected to the PX pixels via the respective data lines. The second driver 130 can supply the respective data signals to the PX pixels.

[0070] In one embodiment, at least one of the first driver 120 and the second driver 130, or a portion of at least one driver, may be incorporated into the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed on the SUB substrate of the display panel 110 and may be disposed and / or formed in the non-display NDA area.

[0071] Figure 1 illustrates that the first driver 120 is formed on one side of the DA display area (e.g., the non-display NDA area on the right side of the DA display area), but the possibilities are not limited to this. For example, the first driver 120 can be positioned only on the other side of the DA display area (e.g., the non-display NDA area on the left side of the DA display area). Petition 870250081403, dated 10 / 09 / 2025, page 19 / 90 14 / 57 or it can be positioned on either side of the DA display area (e.g., the non-display NDA areas on the left and right sides of the DA display area). Alternatively, a portion of the first 120 driver (e.g., some of the circuit elements that make up the first 120 driver) can be positioned in the non-display NDA area, and the other portion of the first 120 driver (e.g., the remaining circuit elements of the circuit elements that make up the first 120 driver) can be positioned in a non-light-emitting area (e.g., an area between the light-emitting areas of the PX pixels) within the DA display area.

[0072] In one embodiment, the other of the first driver 120 and the second driver 130, or a portion of the other driver, may be arranged or formed outside the display panel 110 and may be electrically connected to the display panel 110. For example, the second driver 130 or a portion of the second driver 130 may be implemented with a plurality of integrated circuit chips and may be arranged on the circuit board 140 electrically connected to the PX pixels of the display panel 110. In one embodiment, the second driver 130 may be integrated into a separate integrated circuit chip from the timing control unit, or it may be integrated into each integrated circuit chip together with the timing control unit. The second driver 130 may be implemented with at least one integrated circuit chip and may be mounted in the non-NDA display area of ​​the display panel 110.

[0073] Circuit board 140 can be connected to display panel 110 via PD blocks. In one embodiment, circuit board 140 can be a flexible film, such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip-on-film (COF), but is not limited to these. In one embodiment, circuit board 140 can be connected to the unit Petition 870250081403, dated 10 / 09 / 2025, page 20 / 90 15 / 57 of time control and / or to the power supply unit via another circuit board or connector.

[0074] In one embodiment, a TAG inspection standard can be placed over the non-display NDA area. The TAG inspection standard is used to inspect the thin-film transistor characteristics, and an inspection can be performed by connecting a measuring device to the TAG inspection standard. Consequently, the hydrogen content of the thin-film transistor, etc., can be inferred by inspecting the thin-film transistor characteristics of the TAG inspection standard. With this, the quality of the display device can be improved through process evaluation and compensation.

[0075] At least one TAG inspection pattern may be placed over the non-display NDA area. For example, the TAG inspection pattern may be placed in a space between the first driver 120 and the PA block area. In some embodiments, a plurality of TAG inspection patterns may also be placed.

[0076] The TAG inspection pattern can be used to infer the characteristics of thin-film transistors in the DA display area, for example, the hydrogen content of the semiconductor layer. Because the TAG inspection pattern is placed over the non-DA display area, the TAG inspection pattern remains even after the display device 10 is completed. Consequently, thin-film transistors can be evaluated not only during the manufacturing process of the display device, but also after the display device is completed, and the quality of the display device 10 can be improved through corresponding compensation. The TAG inspection pattern will be described in detail later.

[0077] Figure 3 is a circuit diagram illustrating a pixel according to a modality. The pixel PX in Figure 3 is shown Petition 870250081403, dated 10 / 09 / 2025, page 21 / 90 16 / 57 is merely an example, and the structure or type of PX pixel may vary depending on the modalities.

[0078] Referring to Figure 3, in addition to Figures 1 and 2, the PX pixel may include an ED light-emitting element and a PC pixel circuit connected to the ED light-emitting element. The ED light-emitting element is a light source of the PX pixel and may be, for example, an organic light-emitting diode, but is not limited to this. The PC pixel circuit may control the light emission time and luminance of the ED light-emitting element.

[0079] The PC pixel circuit may include TRS pixel transistors and at least one CST pixel capacitor. For example, the PC pixel circuit may include the first to fifth transistors T1 to T5, and the first and second capacitors C1 and C2. The structure of the PC pixel circuit or the types of circuit elements that constitute the PC pixel circuit may be altered in various ways depending on the embodiments. Figure 3 illustrates an embodiment in which the TRS pixel transistors are N-type transistors, but the TRS pixel transistor type is not limited to this. For example, at least one TRS pixel transistor may also be formed as a P-type transistor.

[0080] The PC pixel circuit may supply a drive current Id to the light-emitting element ED in response to the drive signals supplied by the first driver 120 and the second driver 130.For example, the PC pixel circuit can supply the drive current Id to the light-emitting element ED in response to each GS gate signal supplied by the first driver 120 through each GL gate line, and a DATA data signal supplied by the second driver 130 through the DL data line.

[0081] The second transistor T2 can be a pixel drive transistor PX, whose drain-source current size (e.g., drive current Id) is determined depending Petition 870250081403, dated 10 / 09 / 2025, p. 22 / 90 17 / 57 of a gate-source voltage. The first, third, fourth, and fifth transistors T1, T3, T4, and T5 may be switching transistors that are switched on or off depending on their respective gate-source voltages (substantially, their respective gate voltages). Depending on the type (e.g., P-type or N-type transistor) and / or the operating conditions of each of the first through fifth transistors T1 to T5, a first electrode of each of the first through fifth transistors T1 to T5 may be a drain electrode (or a drain region) or a source electrode (or source region), and a second electrode of the same may be a different electrode from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0082] The PX pixel can be connected to a first GWL gate line that transmits a first GW gate signal (e.g., a scan signal), a second GIL gate line that transmits a second GI gate signal, a third GRL gate line that transmits a third GR gate signal, an ECL emission control line that transmits an EM emission control signal, and a DL data line that transmits a DATA data signal. Additionally, the PX pixel can be connected to a first VDL pixel power line that transmits a first ELVDD pixel voltage (also referred to as first pixel power voltage) and a second VSL pixel power line that transmits a second ELVSS pixel voltage (also referred to as second pixel power voltage).In one embodiment, the pixel PX can be further connected to a startup power line VIL that transmits a startup voltage VINT (also referred to as the third pixel power voltage) and to a reference power line VRL that transmits a reference voltage (also referred to as the fourth pixel power voltage). Petition 870250081403, dated 10 / 09 / 2025, p. 23 / 90 18 / 57

[0083] In one embodiment, the first through fifth transistors T1 to T5 can be positioned in each pixel area (e.g., a pixel area PXA of a pixel PX provided in display area DA in Figure 5) and can be oxide transistors (also referred to as oxide semiconductor transistors) that includes an oxide semiconductor (e.g., an oxide semiconductor material). For example, one semiconductor layer of each of the first through fifth transistors T1 to T5 can be formed from an oxide semiconductor. However, the embodiments are not limited to this. For example, at least one pixel transistor TRS can also be formed from a semiconductor material (e.g., amorphous silicon or polysilicon) other than the oxide semiconductor.

[0084] The oxide semiconductor can have high carrier mobility (e.g., high electron mobility in the case of an N-type transistor) and low leakage current, and consequently, even if the drive time of the oxide transistor becomes longer, a voltage drop may not occur significantly. For example, the PX pixel, which includes the oxide transistor, can be driven at a low frequency because the luminance and / or color of an image do not change significantly due to a voltage drop, even when driven at a low frequency. In the case of display device 10, in which the first to fifth pixel transistors T1 to T5 include the oxide semiconductor, the leakage current of the PX pixel can be reduced or avoided, and power consumption can be reduced.

[0085] Because the oxide semiconductor is sensitive to light, the amount of current, etc., may vary due to external light. In one embodiment, a light-blocking pattern or a bottom electrode (e.g., bottom gate electrode) may be disposed below the semiconductor layer that constitutes at least one TRS pixel transistor (e.g., at least one of the first through fifth transistors). Petition 870250081403, dated 10 / 09 / 2025, p. 24 / 90 19 / 57 pixel resolutions T1 to T5). Consequently, it is possible to prevent or reduce the variation in the amount of current in the TRS pixel transistor due to light and stabilize the operating characteristics of the TRS pixel transistor.

[0086] The first transistor T1 (also referred to as the first pixel transistor) may include a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to a first node N1. The first transistor T1 may be turned on by the first gate signal GW (e.g., the first gate signal GW of a gate-on voltage) transmitted to the first gate line GWL and connect the data line DL and the first node N1 to each other. Consequently, the data signal DATA transmitted to the data line DL may be transmitted to the first node N1.

[0087] The second transistor T2 (also referred to as the second pixel transistor) may include a gate electrode connected to the first node N1 (or gate node), a first electrode (e.g., drain electrode or drain region) connected to a second node N2, and a second electrode (e.g., source electrode or source region) connected to a third node N3. The first electrode of the second transistor T2 may be connected to the first pixel power line VDL via the fifth transistor T5, and the second electrode of the same may be connected to the light-emitting element ED. The second transistor T2 may function as a pixel drive transistor PX and may control the size (e.g., the amount of current) of the drive current Id flowing to the light-emitting element ED in response to the transmitted data signal DATA according to a switching operation of the first transistor T1.

[0088] In one embodiment, the second transistor T2 can still Petition 870250081403, dated 10 / 09 / 2025, page 25 / 90 20 / 57 include a bottom gate electrode BG (also referred to as the back gate electrode of the second transistor T2 or second bottom gate electrode) connected to the third node N3. When the second transistor T2 is formed as a transistor with a dual-gate structure (e.g., a dual-gate transistor with a source-sink structure), by connecting the bottom gate electrode BG of the second transistor T2 to the third node N3 to which the second electrode (e.g., source electrode) of the second transistor T2 is connected, the operating characteristics of the second transistor T2 can be improved.

[0089] The third transistor T3 (also referred to as the third pixel transistor) may include a gate electrode connected to the third gate line GRL, a first electrode connected to the reference power line VRL, and a second electrode connected to the first node N1. The third transistor T3 may be connected by the third gate signal GR transmitted to the third gate line GRL and transmit the reference voltage VREF transmitted to the reference power line VRL to the first node N1.

[0090] The fourth transistor T4 (also referred to as the fourth pixel transistor) may include a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3, and a second electrode connected to the startup power line VIL. The fourth transistor T4 may be turned on by the second gate signal GI transmitted to the second gate line GIL and transmit the startup voltage VINT transmitted to the startup power line VIL to the third node N3.

[0091] The fifth transistor T5 (also referred to as the fifth pixel transistor) may include a gate electrode connected to the ECL emission control line, a first electrode connected to the VDL first pixel power line, and a second electrode connected to the Petition 870250081403, dated 10 / 09 / 2025, page 26 / 90 21 / 57 second node (or to the first electrode of the second transistor T2). The fifth transistor T5 can be turned on by the EM emission control signal (e.g., an EM emission control signal from a gate-on voltage) transmitted to the ECL emission control line and control a light emission time of the PX pixel.

[0092] The first capacitor C1 can be connected between the first node N1 and the third node N3. For example, the first capacitor C1 can be connected between the gate electrode and the second electrode of the second transistor T2. The first capacitor C1 is a storage capacitor for the PX pixel and can store a threshold voltage from the second transistor T2 and a voltage that corresponds to the DATA data signal (e.g., data voltage).

[0093] The second capacitor C2 can be connected between the first VDL pixel power line and the third node N3. In one embodiment, the capacitance of the second capacitor C2 can be less than the capacitance of the first capacitor C1.

[0094] The light-emitting element (ED) can be connected between the third node N3 and the second pixel power line VSL. For example, the ED light-emitting element may include a first electrode (e.g., an anode electrode or a pixel electrode) connected to the third node N3, a second electrode (e.g., a cathode electrode or a counter electrode) facing the first electrode and connected to the second pixel power line VSL, and a light-emitting layer interposed between the first electrode and the second electrode. In one embodiment, the first electrode of the ED light-emitting element may be an individual electrode provided individually to each pixel PX, and the second electrode of the ED light-emitting element may be a common electrode shared by the plurality of pixels PX. The ED light-emitting element may emit light with a luminance that corresponds to the drive current. Petition 870250081403, dated 10 / 09 / 2025, page 27 / 90 22 / 57 for Id, while the drive current Id is supplied by the PC pixel circuit.

[0095] Figure 4 is a circuit diagram illustrating a PX pixel according to one embodiment. For example, Figure 4 illustrates an additional embodiment relating to the switching transistors between the TRS pixel transistors in Figure 3.

[0096] Referring to Figure 4, in addition to Figures 1 to 3, at least one of the switching transistors provided in pixel PX may include a bottom gate electrode BG (or back gate electrode) facing a gate electrode (e.g., a top gate electrode) with a semiconductor layer interposed between them. For example, at least one of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may include a bottom gate electrode BG.

[0097] Figure 4 describes an embodiment in which the respective bottom gate electrodes BG are provided to all pixel transistors TRS, and a reference symbol will be used only for the bottom gate electrode BG provided to a pixel transistor TRS (e.g., the second transistor T2). However, embodiments are not limited to this. For example, at least one pixel transistor TRS may not include the bottom gate electrode BG and / or may not be formed in a gate-sink structure or a source-sink structure.

[0098] In one embodiment, the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may include the respective bottom gate electrodes BG. In another embodiment, the bottom gate electrode BG of each of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may be connected to the gate electrode of the corresponding TRS pixel. For example, each of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may be formed as a dual-gate transistor with a gate-sink structure. Petition 870250081403, dated 10 / 09 / 2025, p. 28 / 90 23 / 57

[0099] By providing the respective lower gate electrodes BG for the first, third, fourth, and fifth transistors T1, T3, T4, and T5, it is possible to prevent or reduce the variation in the amount of current of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 due to light. Furthermore, when the lower gate electrode BG of each of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 is connected to the gate electrode (also referred to as the upper gate electrode) of each of the first, third, fourth, and fifth transistors T1, T3, T4, and T5, the operating characteristics (e.g., switching characteristics) of each of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 can be improved and / or stabilized.For example, by forming at least one switching transistor in the dual-gate structure of a heatsink-gate design, the turn-off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be ensured, leakage current can be reduced, and voltage stability can be improved. As an example, by forming a small-sized switching transistor, such as an oxide transistor with a short channel length, in a dual-gate structure, such as a heatsink-gate design, the operating characteristics of the switching transistor can be improved.

[00100] Figure 5 is a cross-sectional view illustrating a display panel 110 according to an embodiment.

[00101] Figure 5 illustrates the first transistor T1 and the second transistor T2 arranged in any pixel area PXA, as an example of circuit elements that can be provided or arranged in the panel circuit layer of the display panel 110. Furthermore, Figure 5 illustrates a light-emitting display panel that includes an emitting element ED (e.g., a light-emitting diode). Petition 870250081403, dated 10 / 09 / 2025, page 29 / 90 24 / 57 organic), as an example of the 110 display panel to which the modalities can be applied. However, the types and / or structures of the 110 display panel according to the modalities are not limited to this. For example, the 110 display panel may include a light-emitting element of another type and / or structure, or it may be a display panel of other types and / or structures other than the light-emitting display panel.

[00102] Referring to Figure 5, along with Figures 1 to 4, the display panel 110 may include a SUB substrate, a PCL panel circuit layer, a LEL light-emitting element layer, and a TFEL thin-film package layer. The PCL panel circuit layer, the LEL light-emitting element layer, and the TFEL thin-film package layer may be arranged or provided to overlap each other on the SUB substrate. As an example, based on the display area DA, the PCL panel circuit layer, the LEL light-emitting element layer, and the TFEL thin-film encapsulation layer may be sequentially arranged or formed on the SUB substrate along the third direction DR3. However, the embodiments are not limited to this, and the mutual position of the PCL panel circuit layer, the LEL light-emitting element layer, and the TFEL thin-film package layer may be altered.As an example, the PCL panel circuit layer and the LEL light-emitting element layer can be integrated into each other, or the LEL light-emitting element layer can be arranged on an upper side of the PCL panel circuit layer.

[00103] In one embodiment, the display panel 110 may further include additional elements provided on the upper and lower sides of the TFEL thin-film encapsulation layer. For example, the display panel 110 may further include at least one of a ca Petition 870250081403, dated 10 / 09 / 2025, p. 30 / 90 25 / 57 sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, a top substrate, and / or a window). Each of the sensor layer, optical layer, and / or protective layer may be provided on the top side of the TFEL thin-film encapsulation layer or may be provided between the LEL light-emitting element layer and the TFEL thin-film encapsulation layer. In one embodiment, the sensor layer, optical layer, and / or protective layer may be provided over the display panel 110. For example, the sensor layer, optical layer, and / or protective layer may be manufactured integrally with the display panel 110.In another embodiment, the sensor layer, the optical layer and / or the protective layer may be manufactured separately from the display panel 110 and attached to the display panel 110 by means of an adhesive layer or similar.

[00104] The SUB substrate is a basic member for forming the display panel 110 and can be a substrate (or film) that has rigid or flexible characteristics. In one embodiment, the SUB substrate can be a substrate that includes an insulating material such as glass, and has rigid characteristics and may not be bent. In another embodiment, the SUB substrate can be a flexible substrate that includes polyimide or another insulating material and is capable of deformation, such as bending, folding or rolling, and may or may not be bent. The type and / or material of the SUB substrate can be changed depending on the embodiments.

[00105] The SUB substrate may include at least one DA display area. In one embodiment, the DA display area may include PXA pixel areas, each corresponding to PX pixels. By Petition 870250081403, dated 10 / 09 / 2025, page 31 / 90 26 / 57 For example, in the DA display area, each PXA pixel area in which each PX pixel is arranged can be defined.

[00106] In one embodiment, a BUF buffer layer may be placed over the SUB substrate. In another embodiment, the display panel 110 may not include the BUF buffer layer, and in this case, the PCL panel circuit layer may be placed directly over the SUB substrate.

[00107] The BUF buffer layer may include at least one inorganic insulating layer, which includes an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials). The BUF buffer layer may protect the PX pixels from moisture permeating the SUB substrate, which is vulnerable to moisture permeation. The material of the BUF buffer layer may be variously altered depending on the embodiments.

[00108] The PCL panel circuit layer can be arranged on top of the BUF buffer layer. The PCL panel circuit layer can include circuit elements, which include TRS pixel transistors and a CST pixel capacitor, and lines (e.g., signal lines and power lines).

[00109] The PCL panel circuit layer may also include insulating layers arranged on the SUB substrate. For example, the PCL panel circuit layer may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, and a first passivation layer PVX1, which are sequentially arranged on the SUB substrate along the third direction DR3.

[00110] In one embodiment, the PCL panel circuit layer may further include a CNE connection electrode and a second PVX2 passivation layer disposed over the first passivation layer. Petition 870250081403, dated 10 / 09 / 2025, page 32 / 90 27 / 57 sivação PVX1, as illustrated in Figure 5.

[00111] In one embodiment, each of the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3 and the fourth insulating layer INS4 may include at least one inorganic insulating layer that includes an inorganic insulating material (for example, silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide or other inorganic insulating materials).

[00112] Each of a first via layer VIA1 and a second via layer VIA2 may include at least one organic insulating layer comprising an organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or other organic insulating materials). The surfaces (e.g., top surfaces) of the first via layer VIA1 and the second via layer VIA2 may be substantially flat. The type, material, shape, and / or structure of the insulating layers provided over the PCL panel circuit layer may be variously altered depending on the embodiments.

[00113] The TRS pixel transistors can be included in the PC pixel circuit of each PX pixel and can be positioned in the DA display area. For example, the first transistor T1 and the second transistor T2 provided to each PX pixel can be arranged in each PXA pixel area in which the corresponding PX pixel is positioned. In addition, at least one other TRS pixel transistor and / or at least one CST pixel capacitor can be additionally arranged in each PXA pixel area.

[00114] In one embodiment, at least one pixel transistor TRS may include a bottom gate electrode BG. For example, the first transistor T1 may include a first bottom gate electrode BG1, and the second transistor T2 may include a second bottom gate electrode BG1. Petition 870250081403, dated 10 / 09 / 2025, page 33 / 90 28 / 57 bottom gate BG2. In one embodiment, the first bottom gate electrode BG1 and the second bottom gate electrode BG2 can be arranged on the same layer in the PCL panel circuit layer.

[00115] The first transistor T1 may include a first bottom gate electrode BG1 disposed on the substrate SUB, a first semiconductor layer ACT1 disposed on the first bottom gate electrode BG1 and which includes a first channel region CH1, a first drain region DR1 and a first source region SR1, and a first gate electrode GE1 (hereinafter referred to as the first top gate electrode GE1) disposed on the first semiconductor layer ACT1.

[00116] The first semiconductor layer ACT1 can be arranged over at least a portion of the first bottom gate electrode BG1. For example, at least a portion of the first semiconductor layer ACT1, which includes the first channel region CH1, can overlap the first bottom gate electrode BG1. The first top gate electrode GE1 can be arranged over a portion of the first semiconductor layer ACT1, which includes the first channel region CH1, and the third insulating layer INS3 can be arranged between the first top gate electrode GE1 and the first semiconductor layer ACT1.

[00117] In one embodiment, the first transistor T1 may also include a first drain electrode DE1 and a first source electrode SE1 connected to different portions of the first semiconductor layer ACT1. Alternatively, the first transistor T1 does not include a separate drain and / or source electrode, and the first drain region DR1 and / or the first source region SR1 of the first semiconductor layer ACT1 may be connected to other circuit elements, lines, and / or conductive patterns to function. Petition 870250081403, dated 10 / 09 / 2025, page 34 / 90 29 / 57 as the drain electrode and / or source electrode of the first transistor T1.

[00118] The first bottom gate electrode BG1 can be placed between the substrate SUB and the first insulating layer INS1. For example, the first bottom gate electrode BG1 can be placed on the buffer layer BUF and covered by the first insulating layer INS1.

[00119] The first bottom gate electrode BG1 can overlap the first semiconductor layer ACT1. For example, the first bottom gate electrode BG1 can be arranged on a lower side of the first semiconductor layer ACT1 to at least overlap the first channel region CH1. The first insulating layer INS1 and the second insulating layer INS2 can be arranged between the first bottom gate electrode BG1 and the first semiconductor layer ACT1. The first bottom gate electrode BG1 and the first semiconductor layer ACT1 can be spaced from each other by a distance that corresponds to the thicknesses of the first insulating layer INS1 and the second insulating layer INS2. The first bottom gate electrode BG1 can confront the first top gate electrode GE1 with the first semiconductor layer ACT1 interposed between them.

[00120] The first bottom gate electrode BG1 may or may not be connected to another electrode of the first transistor T1. In one embodiment, the first bottom gate electrode BG1 may be electrically connected to the first top gate electrode GE1 and may be used as a back gate electrode to adjust the characteristics of the first transistor T1.

[00121] The first semiconductor layer ACT1 can be arranged over the second insulating layer INS2. In one embodiment, the first semiconductor layer ACT1 can be arranged over the second insulating layer INS2 and can be covered by the third insulating layer INS3. Petition 870250081403, dated 10 / 09 / 2025, p. 35 / 90 30 / 57

[00122] The first semiconductor layer ACT 1 may include a first channel region CH1 superimposed on the first top gate electrode GE1, and a first drain region DR1 and a first source region SR1 spaced apart, with the first channel region CH1 interposed between them. For example, the first drain region DR1 and the first source region SR1 may be positioned on either side of the first channel region CH1. The first channel region CH1 may be a non-conductive region that retains semiconductor properties, and the first drain region DR1 and the first source region SR1 may be conductive regions.

[00123] The first semiconductor layer ACT1 can overlap the first bottom gate electrode BG1 and the first top gate electrode GE1. For example, the first channel region CH1 of the first semiconductor layer ACT1 can be arranged between the first bottom gate electrode BG1 and the first top gate electrode GE1, and can overlap the first bottom gate electrode BG1 and the first top gate electrode GE1.

[00124] The first semiconductor layer ACT1 can be entirely covered by the third insulating layer INS3. For example, the first semiconductor layer ACT1 can be covered by the third insulating layer INS3, except for a portion where at least one contact hole (e.g., a first contact hole CNT1 and a second contact hole CNT2) is formed for connection to the first drain electrode DE1 and / or the first source electrode SE1. Consequently, as the amount of hydrogen flowing into the first semiconductor layer ACT1 during the PCL panel circuit layer formation process is reduced, the conductivity (e.g., carrier concentration) of the first semiconductor layer ACT1 and / or the length of the first channel region CH1 formation can be appropriately controlled. Petition 870250081403, dated 10 / 09 / 2025, p. 36 / 90 31 / 57

[00125] The first top gate electrode GE1 can be arranged over the third insulating layer INS3. In one embodiment, the first top gate electrode GE1 can be arranged over the third insulating layer INS3 and covered by the fourth insulating layer INS4.

[00126] The first top gate electrode GE1 can be arranged over the first semiconductor layer ACT1 to overlap the first channel region CH1. The first top gate electrode GE1 and the first semiconductor layer ACT1 can be spaced apart with the third insulating layer INS3 interposed between them.

[00127] The first drain electrode DE1 and the first source electrode SE1 can be arranged on the fourth insulating layer INS4. The first drain electrode DE1 can be connected to a portion of the first semiconductor layer ACT1. For example, the first drain electrode DE1 can be connected to the first drain region DR1 through the first contact hole CNT1, which penetrates through the third insulating layer INS3 and the fourth insulating layer INS4. The first source electrode SE1 can be connected to another portion of the first semiconductor layer ACT1. For example, the first source electrode SE1 can be connected to the first source region SR1 through the second contact hole CNT2, which penetrates through the third insulating layer INS3 and the fourth insulating layer INS4.

[00128] The second transistor T2 may include a second bottom gate electrode BG2 arranged on the substrate SUB, a second semiconductor layer ACT2 arranged on the second bottom gate electrode BG2 and which includes a second channel region CH2, a second drain region DR2 and a second source region SR2, and a second gate electrode GE2 (hereinafter referred to as the second top gate electrode GE2) arranged on the second semiconductor layer ACT2. The second semiconductor layer Petition 870250081403, dated 10 / 09 / 2025, page 37 / 90 32 / 57 ACT2 may be disposed of in at least a portion of the second lower gate electrode BG2. For example, at least a portion of the second semiconductor layer ACT2, which includes the second channel region CH2, may overlap the second lower gate electrode BG2. The second upper gate electrode GE2 may be disposed of over a portion of the second semiconductor layer ACT2, which includes the second channel region CH2, and the third insulating layer INS3 may be disposed of between the second upper gate electrode GE2 and the second semiconductor layer ACT2.

[00129] In one embodiment, the second transistor T2 may also include a second drain electrode DE2 and a second source electrode SE2 connected to different portions of the second semiconductor layer ACT2. Alternatively, the second transistor T2 does not include a separate drain and / or source electrode, and the second drain region DR2 and / or the second source region SR2 of the second semiconductor layer ACT2 may be connected to other circuit elements, lines, and / or conductive patterns to function as the drain and / or source electrode of the second transistor T2.

[00130] The second bottom gate electrode BG2 can be placed on the BUF buffer layer and can be placed on the same layer as the first bottom gate electrode BG1. The second bottom gate electrode BG2 can overlap the second semiconductor layer ACT2. For example, the second bottom gate electrode BG2 can be placed on a lower side of the second semiconductor layer ACT2 to at least overlap the second channel region CH2. The first insulating layer INS1 and the second insulating layer INS2 can be placed between the second bottom gate electrode BG2 and the second semiconductor layer ACT2. The second bottom gate electrode BG2 and the second semiconductor layer ACT2 po Petition 870250081403, dated 10 / 09 / 2025, page 38 / 90 33 / 57 must be spaced apart by a distance corresponding to the thicknesses of the first insulating layer INS1 and the second insulating layer INS2. The second lower gate electrode BG2 can face the second upper gate electrode GE2 with the second semiconductor layer ACT2 interposed between them.

[00131] The second bottom gate electrode BG2 may or may not be connected to an electrode of the second transistor T2. In one embodiment, the second bottom gate electrode BG2 may be connected to the second source electrode SE2 of the second transistor T2 and may be used as a back gate electrode to adjust the characteristics of the second transistor T2.

[00132] The second semiconductor layer ACT2 can be arranged over the second insulating layer INS2, can be arranged over the same layer as the first semiconductor layer ACT1, and can include the same oxide semiconductor as the first semiconductor layer ACT1.

[00133] The second semiconductor layer ACT2 may include a second CH2 channel region superimposed on the second top gate electrode GE2, and a second drain region DR2 and a second source region SR2 spaced apart, with the second CH2 channel region interposed between them. For example, the second drain region DR2 and the second source region SR2 may be positioned on either side of the second CH2 channel region. The second CH2 channel region may be a non-conductive region that retains semiconductor properties, and the second drain region DR2 and the second source region SR2 may be conductive regions.

[00134] The second semiconductor layer ACT2 can overlap the second bottom gate electrode BG2 and the second top gate electrode GE2. For example, the second channel region CH2 of Petition 870250081403, dated 10 / 09 / 2025, page 39 / 90 34 / 57 The second semiconductor layer ACT2 may be arranged between the second lower gate electrode BG2 and the second upper gate electrode GE2, and may overlap the second lower gate electrode BG2 and the second upper gate electrode GE2.

[00135] The second semiconductor layer ACT2 can be entirely covered by the third insulating layer INS3. For example, the second semiconductor layer ACT2 can be covered by the third insulating layer INS3, except for a portion where at least one contact hole (e.g., a third contact hole CNT3 and a fourth contact hole CNT4) is formed for connection to the second drain electrode DE2 and / or the second source electrode SE2. Consequently, as the amount of hydrogen flowing into the second semiconductor layer ACT2 during the PCL panel circuit layer formation process is reduced, the conductivity (e.g., carrier concentration) of the second semiconductor layer ACT2 and / or the length of the second channel region CH2 formation can be appropriately controlled.

[00136] The second top gate electrode GE2 can be placed on the third insulating layer INS3 and can be placed on the same layer as the first top gate electrode GE1.

[00137] The second top gate electrode GE2 can be placed over the second semiconductor layer ACT2 to overlap the second channel region CH2. The second top gate electrode GE2 and the second semiconductor layer ACT2 can be spaced apart, with the third insulating layer INS3 interposed between them.

[00138] The second drain electrode DE2 and the second source electrode SE2 can be placed on the fourth insulating layer INS4 and covered by the first passivation layer PVX1.

[00139] The second drain electrode DE2 can be connected to Petition 870250081403, dated 10 / 09 / 2025, page 40 / 90 35 / 57 a portion of the second semiconductor layer ACT2. For example, the second drain electrode DE2 can be connected to the second drain region DR2 through the third contact hole CNT3, which penetrates through the third insulating layer INS3 and the fourth insulating layer INS4.

[00140] The second source electrode SE2 can be connected to another portion of the second semiconductor layer ACT2. For example, the second source electrode SE2 can be connected to the second source region SR2 through the fourth contact hole CNT4, which penetrates through the third insulating layer INS3 and the fourth insulating layer INS4. In one embodiment, the second source electrode SE2 can be additionally connected to the second bottom gate electrode BG2. For example, the second source electrode SE2 can be connected to the second bottom gate electrode BG2 through a fifth contact hole CNT5, which penetrates through the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4.

[00141] The TRS pixel transistors, which include the first transistor T1 and the second transistor T2, can be covered by at least one passivation layer. For example, the TRS pixel transistors can be covered by the first passivation layer PVX1 and the second passivation layer PVX2, as illustrated in Figure 5.

[00142] In the embodiment illustrated in Figure 5, the second transistor T2 of each PX pixel can be connected to the light-emitting element ED of the corresponding PX pixel via the CNE connection electrode. The CNE connection electrode can be placed over the first via layer VIA1 and covered by the second passivation layer PVX2. For example, the CNE connection electrode can be placed between the first via layer VIA1 and the second passivation layer. Petition 870250081403, dated 10 / 09 / 2025, page 41 / 90 36 / 57 PVX2 action.

[00143] The CNE connection electrode can be connected to an electrode of the second transistor T2. As an example, the CNE connection electrode can be placed on the second source electrode SE2 and connected to the second source electrode SE2 through at least one contact hole or via hole that penetrates through the first passivation layer PVX1 and the first via layer VIA1.

[00144] Each of the electrodes, conductive patterns and / or lines provided on the conductive layers of the PCL panel circuit layer may include at least one conductive material and may have a single-layer or multi-layer structure.For example, the first and second bottom gate electrodes BG1 and BG2, the first and second top gate electrodes GE1 and GE2, the first and second source electrodes SE1 and SE2, the first and second drain electrodes DE1 and DE2, and the connecting electrode CNE may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, an alloy thereof, or other conductive materials, and may each have a single-layer or multi-layer structure.

[00145] In one embodiment, the first and second semiconductor layers ACT1 and ACT2 may include an oxide semiconductor. For example, the first and second semiconductor layers ACT1 and ACT2 may include at least one zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indiogallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), and indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors. The oxide semiconductor Petition 870250081403, dated 10 / 09 / 2025, page 42 / 90 37 / 57 used to form the oxide semiconductor transistors, which include the first transistor T1 and the second transistor T2, is not limited to the materials exemplified above and can be variously altered depending on the embodiments. In one embodiment, the first and second semiconductor layers ACT1 and ACT2 may include the same oxide semiconductor.

[00146] In one embodiment, the semiconductor layers of TRS pixel transistors can be formed from a high-mobility oxide semiconductor (e.g., a high-mobility oxide semiconductor with a high electron concentration (e.g., mobility of approximately 50 cm2 / Vs or more)), such as indium tin gallium zinc oxide (ITGZO) or indium gallium oxide (IGO). When TRS pixel transistors are formed from the high-mobility oxide semiconductor, it is possible to form each transistor in a precise size (e.g., a size that includes an active layer with a width and / or length ranging from approximately several micrometers to tens of micrometers), while appropriately ensuring the mobility of each transistor.Consequently, even in a high-resolution display device with a relatively narrow PXA pixel area, the TRS pixel transistors can be easily arranged and / or formed, and the element characteristics and / or operating characteristics of the TRS pixel transistors can be appropriately ensured. For example, even if the channel length of at least one switching transistor provided in the PX pixel is reduced, the operating characteristics (e.g., appropriate switching characteristics) of the switching transistor can be ensured. Consequently, the area occupied by the TRS pixel transistors can be appropriately and / or easily reduced, and a design space for other elements or circuit lines, etc., can be ensured. Petition 870250081403, dated 10 / 09 / 2025, p. 43 / 90 38 / 57 Furthermore, since TRS pixel transistors are made of highly mobile oxide semiconductor, the power consumption of the display device can be reduced.

[00147] The LEL light-emitting element layer can be placed over the PCL panel circuit layer and can be positioned in the DA display area. For example, the LEL light-emitting element layer can be placed over the PCL panel circuit layer in the DA display area.

[00148] The LEL light-emitting element layer may include ED light-emitting elements of the PX pixels. For example, the LEL light-emitting element layer may include a PDL pixel-defining film (also referred to as a bank) that partitions a light-emitting area of ​​each of the PX pixels and an ED light-emitting element positioned in each light-emitting area. In one embodiment, the LEL light-emitting element layer may further include an SPC spacer disposed over a portion of the PDL pixel-defining film.

[00149] Each ED light-emitting element may include a first PE electrode (e.g., an anode electrode) connected to at least one TRS pixel transistor (e.g., the second transistor T2) included in the corresponding PX pixel, and an EML light-emitting layer and a second CE electrode (e.g., a cathode electrode) that are sequentially arranged on the first PE electrode. In one embodiment, the ED light-emitting element may further include a first functional layer (e.g., a hole layer that includes a hole transport layer) interposed between the first PE electrode and the EML light-emitting layer, and a second functional layer (e.g., an electron layer that includes an electron transport layer) interposed between the EML light-emitting layer and the second CE electrode. Petition 870250081403, dated 10 / 09 / 2025, p. 44 / 90 39 / 57

[00150] The first PE electrode of the ED light-emitting element can be arranged on the PCL panel circuit layer. In the embodiment illustrated in Figure 5, the first PE electrode can be arranged on the second via layer VIA2 to correspond to each light-emitting area, and can be connected to the CNE connection electrode through at least one contact hole or via hole that penetrates through the second passivation layer PVX2 and the second via layer VIA2.

[00151] The first PE electrode may include a conductive material. In one embodiment, the first PE electrode may include a metallic material with high reflectivity. For example, the first PE electrode may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), or it may have a multi-layer structure (e.g., ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.) that includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (InsO3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni).

[00152] The EML light-emitting layer of the ED light-emitting element may include a high molecular weight material or a low molecular weight material. The light emitted by the EML light-emitting layer can contribute to the display of an image.In one embodiment, the EML light-emitting layer can be provided for each PX pixel, and the EML light-emitting layer of each PX pixel can emit visible light of a color that corresponds to the corresponding PX pixel. In another embodiment, the EML light-emitting layer can be a common layer shared by PX pixels of different colors, and wavelength conversion layers and / or color filters that correspond to the color (or wavelength band) of the light to be emitted by each PX pixel can be arranged in the light-emitting areas of at least some of the PX pixels. Petition 870250081403, dated 10 / 09 / 2025, p. 45 / 90 40 / 57

[00153] The second CE electrode of the ED light-emitting element may include a conductive material. In one embodiment, the second CE electrode may be a common film formed over the entire DA display area to cover the EML light-emitting layer and the PDL pixel-defining film. In another embodiment, the second CE electrode may be formed of a transparent conductive material (TCO), such as ITO, IZO, ZnO, or ITZO, capable of transmitting light, or of a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[00154] The PDL pixel definition film may have an aperture that corresponds to each light-emitting area and may encircle the light-emitting area. For example, the PDL pixel definition film may be formed to cover an edge of the first PE electrode of the ED light-emitting element and may include an aperture that exposes the remaining portion of the first PE electrode. An area where the first exposed PE electrode and the EML light-emitting layer overlap (or an area that includes the same) may be defined as a light-emitting area for each PX pixel.

[00155] In one embodiment, the PDL pixel-defining film may include at least one organic insulating layer, which includes an organic insulating material. For example, the PDL pixel-defining film may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB), or other organic insulating materials.

[00156] The SPC spacer may be placed over a portion of the PDL pixel definition film. The SPC spacer may include at least one organic insulating layer, which includes an organic insulating material. The SPC spacer may include the same material as the film. Petition 870250081403, dated 10 / 09 / 2025, page 46 / 90 41 / 57 Pixel-defining film (PDL) or may include a material other than the pixel-defining film (PDL). In one embodiment, the pixel-defining film (PDL) and the spacer (SPC) may be sequentially formed through each masking process. In another embodiment, the pixel-defining film (PDL) and the spacer (SPC) may be simultaneously formed using a halftone mask. In this case, the pixel-defining film (PDL) and the spacer (SPC) may be viewed as an insulating film that is integrated with each other.

[00157] The TFEL thin-film encapsulation layer can be placed over the LEL light-emitting element layer. The TFEL thin-film encapsulation layer can cover the LEL light-emitting element layer in the DA display area and extend into the non-display NDA area to contact the PCL panel circuit layer. For example, the TFEL thin-film encapsulation layer can be placed over the DA display area to cover the LEL light-emitting element layer, and an end portion of the TFEL thin-film encapsulation layer can be positioned in a portion of the non-display NDA area adjacent to the DA display area. The TFEL thin-film encapsulation layer can block oxygen or moisture permeation into the LEL light-emitting element layer and can alleviate electrical and / or physical shocks to the PCL panel circuit layer and the LEL light-emitting element layer.

[00158] In one embodiment, the TFEL thin-film encapsulation layer may have a multi-layered structure, which includes a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3, which are sequentially stacked on top of the LEL light-emitting element layer. Each of the first layer of Petition 870250081403, dated 10 / 09 / 2025, page 47 / 90 42 / 57 encapsulation TFE1 and the third encapsulation layer TFE3 can be an inorganic encapsulation layer, which includes an inorganic material. The second encapsulation layer TFE2 can be an organic encapsulation layer, which includes an organic material. The structure and / or material of the TFEL thin film encapsulation layer can be altered depending on the embodiments.

[00159] Figure 6 is a plan view illustrating an inspection pattern according to a modality. Figure 7 is a cross-sectional view taken along line Q1-Q1' of Figure 6.

[00160] Referring to Figures 6 and 7, the TAG inspection pattern, according to one embodiment, may include a first conductive pattern COP1, a first inspection electrode INE1 connected to the first conductive pattern COP1, a semiconductor pattern SCP, a second conductive pattern COP2, a second inspection electrode INE2 connected to the second conductive pattern COP2, an inspection source electrode IPS connected to a portion of the semiconductor pattern SCP, a third inspection electrode INE3 connected to the inspection source electrode IPS, an inspection drain electrode IPD connected to another portion of the semiconductor pattern SCP, and a fourth inspection electrode INE4 connected to the inspection drain electrode IPD.

[00161] The first conductive pattern COP1 can be placed on the SUB substrate. For example, the first conductive pattern COP1 can be placed on the SUB substrate where the BUF buffer layer is formed and can be placed directly on the BUF buffer layer.

[00162] The first conductive pattern COP1 can be arranged on the same layer as the bottom gate electrode BG of the panel circuit layer PCL illustrated in Figure 5. For example, the first Petition 870250081403, dated 10 / 09 / 2025, page 48 / 90 Standard 43 / 57 conductor COP1 can be formed simultaneously with the bottom gate electrode BG through the same process.

[00163] A first insulating layer INS1 and a second insulating layer INS2 can be arranged over the first conductor pattern COP1. The first insulating layer INS1 can be the first insulating layer INS1 of the PCL panel circuit layer, and the second insulating layer INS2 can be the second insulating layer INS2 of the PCL panel circuit layer. For example, the first insulating layer INS1 and the second insulating layer INS2 can extend from the DA display area to the NDA non-display area and can be arranged on the first conductor pattern COP1.

[00164] The SCP semiconductor pattern can be placed on the second insulating layer INS2. The SCP semiconductor pattern can be placed directly on the second insulating layer INS2. The SCP semiconductor pattern can be placed on the same layer as the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the PCL panel circuit layer. For example, the SCP semiconductor pattern can be formed simultaneously with the first semiconductor layer ACT1 and the second semiconductor layer ACT2 through the same process.

[00165] The SCP semiconductor pattern may include an oxide semiconductor. For example, the SCP semiconductor pattern may include the oxide semiconductors illustrated in the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the PCL panel circuit layer.

[00166] The SCP semiconductor pattern may include a first conducting region COR1, a channel region with a PCH pattern, and a second conducting region COR2. The PCH pattern channel region may overlap with the second conducting pattern COR2. The first conducting region COR1 and the second conducting region COR2 may be... Petition 870250081403, dated 10 / 09 / 2025, page 49 / 90 44 / 57 steps apart, with the PCH pattern channel region interposed between them. For example, the first conductive region COR1 and the second conductive region COR2 can be positioned on either side of the PCH pattern channel region. The PCH pattern channel region can be a non-conductive region that retains semiconductor properties, and the first conductive region COR1 and the second conductive region COR2 can be conductive regions.

[00167] A third insulating layer INS3 can be arranged over the SCP semiconductor pattern. The third insulating layer INS3 can be the third insulating layer INS3 of the PCL panel circuit layer. For example, the third insulating layer INS3 can extend from the DA display area to the NDA non-display area and can be arranged over the SCP semiconductor pattern.

[00168] The second COP2 conductor pattern can be placed over the third insulating layer INS3. For example, the second COP2 conductor pattern can be placed over the third insulating layer INS3 and covered by the fourth insulating layer INS4.

[00169] The second COP2 conductive pattern can be arranged on the same layer as the top gate electrodes GE1 and GE2 of the PCL panel circuit layer illustrated in Figure 5. For example, the second COP2 conductive pattern can be formed simultaneously with the top gate electrodes GE1 and GE2 through the same process. The second COP2 conductive pattern can overlap the first COP1 conductive pattern and can be arranged to overlap the PCH pattern channel region of the SCP semiconductor pattern.

[00170] The second COP2 conductor pattern can be connected to a portion of the SCP semiconductor pattern. For example, the second COP2 conductor pattern can be connected to the SCP semiconductor pattern through a first VH1 via hole that penetrates the third insulating layer INS3. In some embodiments, the second pa Petition 870250081403, dated 10 / 09 / 2025, pp. 50 / 90 45 / 57 The COP2 conductor pattern may be in direct contact with an upper surface of the SCP semiconductor pattern. In some embodiments, the second COP2 conductor pattern may be in direct contact with the PCH pattern channel region of the SCP semiconductor pattern.

[00171] A fourth insulating layer INS4 can be placed over the second standard conductor COP2. The fourth insulating layer INS4 can be the fourth insulating layer INS4 of the PCL panel circuit layer. For example, the fourth insulating layer INS4 can extend from the DA display area to the NDA non-display area and can be placed over the second standard conductor COP2.

[00172] A first inspection electrode INE1, a second inspection electrode INE2, a third inspection electrode INE3, a fourth inspection electrode INE4, an inspection source electrode IPS, and an inspection drain electrode IPD can be arranged on the fourth insulating layer INS4. The first inspection electrode INE1, the second inspection electrode INE2, the third inspection electrode INE3, the fourth inspection electrode INE4, the inspection source electrode IPS, and the inspection drain electrode IPD can be arranged on the same layer as the first and second source electrodes SE1 and SE2 and the first and second drain electrodes DE1 and DE2 of the PCL panel circuit layer illustrated in Figure 5, and can be formed simultaneously with them through the same process.

[00173] The first inspection electrode INE1 can be arranged to overlap a portion of the first conductor standard COP1. The first inspection electrode INE1 can be connected to a portion of the first conductor standard COP1. For example, the first inspection electrode INE1 can be connected to the first conductor standard COP1 through a second through hole VH2 that penetrates through the first insulating layer INS1, the second insulating layer INS2, the third Petition 870250081403, dated 10 / 09 / 2025, page 51 / 90 46 / 57 insulating layer INS3 and the fourth insulating layer INS4.

[00174] The second inspection electrode INE2 can be arranged to overlap a portion of the second conductor pattern COP2. The second inspection electrode INE2 can be connected to a portion of the second conductor pattern COP2. For example, the second inspection electrode INE2 can be connected to the second conductor pattern COP2 through a third via hole VH3 that penetrates through the fourth insulating layer INS4.

[00175] The IPS inspection source electrode can be arranged to overlap a portion of the SCP semiconductor pattern. The IPS inspection source electrode can be connected to a portion of the SCP semiconductor pattern. For example, the IPS inspection source electrode can be connected to the first conductive region COR1 of the SCP semiconductor pattern through a fourth via hole VH4 that penetrates through the third insulating layer INS3 and the fourth insulating layer INS4.

[00176] The third inspection electrode INE3 can be connected to the inspection source electrode IPS. For example, the third inspection electrode INE3 can be integrally formed with the inspection source electrode IPS. However, the present invention is not limited to this, and the third inspection electrode INE3 can be formed separately from the inspection source electrode IPS and can be connected to it through a through hole.

[00177] The IPD inspection drain electrode can be arranged to overlap another portion of the SCP semiconductor pattern. The IPD inspection drain electrode can be connected to another portion of the SCP semiconductor pattern. For example, the IPD inspection drain electrode can be connected to the second conductive region COR2 of the SCP semiconductor pattern through a fifth via hole VH5 that penetrates through the third insulating layer INS3 and the fourth ca Petition 870250081403, dated 10 / 09 / 2025, page 52 / 90 47 / 57 insulating material INS4.

[00178] The fourth inspection electrode INE4 can be connected to the IPD inspection drain electrode. For example, the fourth inspection electrode INE4 can be integrally formed with the IPD inspection drain electrode. However, the present invention is not limited to this, and the fourth inspection electrode INE4 can be formed separately from the IPD inspection drain electrode and connected to it via a through hole.

[00179] The TAG inspection pattern described above can be formed by including the same SCP semiconductor pattern as the first and second ACT1 and ACT2 semiconductor layers of the first and second T1 and T2 transistors in the DA display area. Consequently, the characteristics of the TRS pixel transistors can be inferred by inspecting the characteristics of the TAG inspection pattern.

[00180] Figure 8 is a graph illustrating the changes in the characteristics of a transistor depending on the hydrogen content of a semiconductor layer. For example, Figure 8 illustrates the electrical characteristics of transistors through a drain current Id, according to a gate voltage Vg, in transistors formed when hydrogen is not supplied, is supplied at 3 sccm (standard cubic centimeters per minute), and is supplied at 10 sccm, during the formation of the semiconductor layer.

[00181] Figure 9 is a graph illustrating the changes in the characteristics of a transistor that has a semiconductor layer without hydrogen. Figure 10 is a graph illustrating the changes in the characteristics of a transistor that has a semiconductor layer containing hydrogen. For example, Figure 9 illustrates a hysteresis curve of a transistor formed when hydrogen is not supplied during the formation of the semiconductor layer in Figure 8, and Figure 10 illustrates a hysteresis curve of a transistor formed when Petition 870250081403, dated 10 / 09 / 2025, page 53 / 90 48 / 57 hydrogen is supplied at 3 sccm during the formation of the semiconductor layer in Figure 8.

[00182] Referring to Figure 8, when hydrogen is not supplied, the threshold voltage Vth is approximately 3.82 and the subthreshold oscillation (SS) is approximately 1.89, and hydrogen is supplied at 3 sccm, a threshold voltage Vth is approximately 3.82 and the subthreshold oscillation (SS) is approximately 1.89. Furthermore, when hydrogen is supplied at 10 sccm, the semiconductor layer becomes conductive.

[00183] Referring to Figures 9 and 10, it was found that the hysteresis of the transistor containing hydrogen in the semiconductor layer was reduced compared to the transistor that did not contain hydrogen in the semiconductor layer.

[00184] It can be seen from Figures 8 to 10 that the hydrogen content in the semiconductor layer had a significant effect on the transistor's characteristics.

[00185] Through this, the present inventors intend to maintain uniform display quality by inspecting and monitoring the characteristics of TRS pixel transistors in the DA display area, even when the characteristics of TRS pixel transistors in the DA display area change depending on the manufacturing process conditions by inspecting the TRS pixel transistor characteristics through the TAG inspection pattern and confirming the hydrogen content of the semiconductor layer.

[00186] Hereafter, a method for inspecting a display device that includes the TAG inspection pattern will be described with reference to Figures 1 to 7 described above.

[00187] Because the TAG inspection pattern includes an SCP oxide pattern, which is the same semiconductor layer as the TRS pixel transistors in the DA display area, the TAG inspection pattern re Petition 870250081403, dated 10 / 09 / 2025, page 54 / 90 49 / 57 displays the TRS pixel transistors in the DA display area, and the TRS pixel transistor characteristics in the DA display area can be confirmed using the TAG inspection pattern. For example, the transistor characteristics could be a semiconductor layer capacitance value.

[00188] In one embodiment, during the manufacturing process of the display device 10, a manufacturing process for the TRS pixel transistor of the PCL panel circuit layer and a manufacturing process for the TAG inspection pattern can be simultaneously performed. For example, the bottom gate electrode BG of the TRS pixel transistor and the first conducting pattern COP1 of the TAG inspection pattern, the semiconductor layers ACT1 and ACT2 of the TRS pixel transistor and the semiconductor pattern SCP of the TAG inspection pattern, the top gate electrodes GE1 and GE2 of the TRS pixel transistor and the second conducting pattern COP2 of the TAG inspection pattern, and the source and drain electrodes SE1, SE2, DE1 and DE2 of the TRS pixel transistor and the first to fourth inspection electrodes INE1, INE2, INE3 and INE4 of the TAG inspection pattern can each be simultaneously formed through the same process.

[00189] After the TRS pixel transistor and the TAG inspection pattern are formed, the inspection can be performed by connecting a measuring device to the TAG inspection pattern. The measuring device can be provided with terminals that can apply electrical signals to the first through fourth inspection electrodes INE1, INE2, INE3, and IN4.

[00190] In one embodiment, the capacitance of a back channel of the SCP semiconductor pattern of the TAG inspection pattern can be a measure. Here, the back channel of the SCP semiconductor pattern can refer to a channel formed on a lower side of the SCP semiconductor pattern adjacent to the first COP1 conductive pattern. A Petition 870250081403, dated 10 / 09 / 2025, pp. 55 / 90 50 / 57 back channel capacitance can be obtained by measuring the capacitance of the SCP semiconductor pattern while forming the back channel in the SCP semiconductor pattern.

[00191] As a method for forming the back channel in the SCP semiconductor pattern of the TAG inspection pattern, the back channel can be formed by applying an alternating current signal (e.g., frequency) to the first conductive pattern COP1 through the first inspection electrode INE1, and applying a direct current signal to the second conductive pattern COP2 through the second inspection electrode INE2 in the measuring device.

[00192] As described above, the second conductive pattern COP2 can be in direct contact with the upper surface of the semiconductor pattern SCP and be connected to it. The third insulating layer INS3 is interposed between the second conductive pattern COP2 and the semiconductor pattern SCP. A tunneling effect does not occur between the second conductive pattern COP2 and the first conductive pattern COP1, even if electrical signals are applied to the second conductive pattern COP2 and the first conductive pattern COP1, because the third insulating layer INS3 is thick. In the present embodiment, by directly contacting the second conductive pattern COP2 with the semiconductor pattern SCP, the tunneling effect can occur between the second conductive pattern COP2 and the first conductive pattern COP1. In the presence of an electron trap caused by the hydrogen present in the semiconductor pattern SCP, the current can flow through the trap due to the tunneling effect.

[00193] That is, when electrical signals are applied to the first conductive pattern COP1 and the second conductive pattern COP2, current can flow between the first conductive pattern COP1 and the second conductive pattern COP2, and the current and capacitance within the semiconductor pattern SCP can be measured through the third electrode. Petition 870250081403, dated 10 / 09 / 2025, pp. 56 / 90 51 / 57 of inspection INE3 and of the fourth inspection electrode INE4.

[00194] Figure 11 is a graph illustrating the capacitance of a semiconductor pattern as a function of frequency. For example, Figure 11 illustrates the capacitance of the SCP semiconductor pattern as a function of the frequency of the alternating current signal applied to the second COP2 conductor pattern.

[00195] Referring to Figure 11, as the frequency of the alternating current signal applied to the second conductor pattern COP2 increases, a capacitance Qcp of the semiconductor pattern SCP decreases.

[00196] In the present embodiment, a capacitance value of the SCP semiconductor standard in which the back channel is formed can be measured using the TAG inspection standard described above. Using such capacitance value, a hydrogen content of the SCP semiconductor standard can be found by comparing the capacitance value with a reference table in which the hydrogen content according to the capacitance value is analyzed.

[00197] Therefore, the characteristics of TRS pixel transistors can be monitored by measuring the hydrogen content of the SCP semiconductor standard using the TAG inspection standard at regular intervals during the manufacture of the display device 10.

[00198] Figure 12 is a cross-sectional view illustrating an inspection pattern of a display device according to another embodiment. Figure 12 illustrates another embodiment of Figure 7 described above.

[00199] Referring to Figure 12, the present embodiment differs from the embodiment in Figure 7, in that the TAG inspection pattern still includes a CNP connection pattern that connects the first conductor pattern COP1 and the semiconductor pattern SCP, and the second conductor pattern COP2 is spaced from the semiconductor pattern SCP. Petition 870250081403, dated 10 / 09 / 2025, pp. 57 / 90 From 52 / 57 onwards, descriptions of the same configuration as the modality described above will be omitted and differences from the modality described above will be described.

[00200] The TAG inspection pattern, according to one embodiment, may include a first conductive pattern COP1, a first inspection electrode INE1 connected to the first conductive pattern COP1, a CNP connection pattern connecting the first conductive pattern COP1 and a semiconductor pattern SCP, a semiconductor pattern SCP, a second conductive pattern COP2, a second inspection electrode INE2 connected to the second conductive pattern COP2, an inspection source electrode IPS connected to a portion of the semiconductor pattern SCP, a third inspection electrode INE3 connected to the inspection source electrode IPS, an inspection drain electrode IPD connected to another portion of the semiconductor pattern SCP, and a fourth inspection electrode INE4 connected to the inspection drain electrode IPD.

[00201] The CNP connection pattern can be arranged over the first conductor pattern COP1. For example, the CNP connection pattern can be arranged in direct contact with the first conductor pattern COP1. The CNP connection pattern can overlap the SCP semiconductor pattern and can be arranged to overlap the PCH channel region of the SCP semiconductor pattern. The CNP connection pattern can be arranged in a sixth VH6 via hole, which penetrates through the first insulating layer INS1 and the second insulating layer INS2. The sixth VH6 via hole can be arranged to overlap the first conductor pattern COP1, the second conductor pattern COP2, and the SCP semiconductor pattern. The CNP connection pattern can be connected to the first conductor pattern COP1 and the SCP semiconductor pattern through the sixth VH6 via hole. For example, the CNP connection pattern can be in direct contact with a su Petition 870250081403, dated 10 / 09 / 2025, pp. 58 / 90 53 / 57 lower surface of the standard PCH channel region. The first conductor pattern COP1, the second conductor pattern COP2, and the CNP connection pattern can be arranged to overlap the standard PCH channel region of the SCP semiconductor pattern.

[00202] The CNP connection pattern can be arranged in contact with the lateral surfaces of the first insulating layer INS1 and the second insulating layer INS2. In some embodiments, an upper surface of the CNP connection pattern can be aligned with an upper surface of the second insulating layer INS2. However, the present invention is not limited to this, and at least a portion of the CNP connection pattern can also be arranged to extend to the upper surface of the second insulating layer INS2.

[00203] The CNP connection standard may include a conductive material. For example, the CNP connection standard may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, an alloy thereof, or other conductive materials, and each may have a single-layer or multi-layer structure.

[00204] The SCP semiconductor pattern can be arranged over the CNP connection pattern, and the second insulating layer INS2 and the third insulating layer INS3 can be arranged over the SCP semiconductor pattern. The second conductive pattern COP2 can be arranged over the third insulating layer INS3, overlapping the SCP semiconductor pattern. Unlike Figure 7, the second conductive pattern COP2 can be arranged to be spaced from the SCP semiconductor pattern.

[00205] In one embodiment, the capacitance of a front-side channel of the SCP semiconductor pattern of the TAG inspection pattern can be Petition 870250081403, dated 10 / 09 / 2025, pp. 59 / 90 54 / 57 measurement. Here, the front channel of the SCP semiconductor pattern may refer to a channel formed on an upper side of the SCP semiconductor pattern adjacent to the second COP2 conductor pattern. Consequently, the front channel may be formed by contacting the first COP1 conductor pattern with the SCP semiconductor pattern through the CNP connection pattern and arranging the second COP2 conductor pattern to be spaced from the SCP semiconductor pattern.

[00206] The front channel capacitance can be obtained by measuring a capacitance of the SCP semiconductor pattern while forming the front channel in the SCP semiconductor pattern. As a method for forming the front channel in the SCP semiconductor pattern of the TAG inspection pattern, the front channel can be formed by applying a direct current signal to the first conductive pattern COP1 through the first inspection electrode INE1 and by applying an alternating current signal (e.g., frequency) to the second conductive pattern COP2 through the second inspection electrode INE2 in the measuring device. In the present embodiment, a tunneling effect can occur between the second conductive pattern COP2 and the first conductive pattern COP1 by directly connecting the first conductive pattern COP1 to the SCP semiconductor pattern through the CNP connection pattern.

[00207] Therefore, when electrical signals are applied to the first conductive pattern COP1 and the second conductive pattern COP2, current can flow between the first conductive pattern COP1 and the second conductive pattern COP2, and the current and capacitance within the semiconductor pattern SCP can be measured through the third inspection electrode INE3 and the fourth inspection electrode INE4.

[00208] Figure 13 is a cross-sectional view illustrating an inspection pattern of a display device according to yet another embodiment. Figure 13 illustrates a different embodiment. Petition 870250081403, dated 10 / 09 / 2025, pages 60 / 90 55 / 57 of those in Figures 7 and 12 described above.

[00209] Referring to Figure 13, the present embodiment illustrates a TAG inspection pattern that includes the structures of the embodiments in Figures 7 and 12 together. For example, the present embodiment differs from the embodiments described above in that the TAG inspection pattern includes a CNP connection pattern that connects the first conductor pattern COP1 and the semiconductor pattern SCP, and the second conductor pattern COP2 is in contact with the semiconductor pattern SCP.

[00210] In one embodiment, the capacitance of a dual channel of the SCP semiconductor pattern of the TAG inspection pattern can be measured. Here, the dual channel of the SCP semiconductor pattern can refer either to the front channel formed on the upper side of the SCP semiconductor pattern adjacent to the second COP2 conductive pattern or to the rear channel formed on the lower side of the SCP semiconductor pattern adjacent to the first COP1 conductive pattern. Consequently, the dual channel can be formed by contacting the first COP1 conductive pattern with the SCP semiconductor pattern through the CNP connection pattern and by contacting the second COP2 conductive pattern with the SCP semiconductor pattern.

[00211] Dual channel capacitance can be obtained by measuring the capacitance of the SCP semiconductor pattern while forming the front channel and back channel in the SCP semiconductor pattern. As a method for forming the dual channel in the SCP semiconductor pattern of the TAG inspection pattern, the dual channel can be formed by applying an alternating current signal (e.g., frequency) to the first conductive pattern COP1 through the first inspection electrode INE1, and applying an alternating current signal (e.g., frequency) to the second conductive pattern COP2 through the second inspection electrode INE2 in the measuring device.

[00212] In the present embodiment, a tunneling effect can Petition 870250081403, dated 10 / 09 / 2025, pp. 61 / 90 56 / 57 occur between the second conductor pattern COP2 and the first conductor pattern COP1, by directly connecting the first conductor pattern COP1 to the semiconductor pattern SCP through the CNP connection pattern and connecting the second conductor pattern COP2 to the semiconductor pattern SCP. Therefore, when electrical signals are applied to the first conductor pattern COP1 and the second conductor pattern COP2, current can flow between the first conductor pattern COP1 and the second conductor pattern COP2, and the current and capacitance within the semiconductor pattern SCP can be measured through the third inspection electrode INE3 and the fourth inspection electrode INE4.

[00213] Therefore, the characteristics of TRS pixel transistors can be monitored by measuring the capacitance of the SCP semiconductor pattern using the TAG inspection pattern at regular intervals during the manufacture of the display device 10 and confirming the hydrogen content.

[00214] Figure 14 is a plan view illustrating a display panel according to yet another embodiment.

[00215] Referring to Figure 14, the present embodiment differs from the embodiment described in Figure 2 above, in that the display panel includes a plurality of TAG1, TAG2 and TAG3 inspection patterns.

[00216] The plurality of inspection patterns TAG1, TAG2, and TAG3 can be arranged in the non-display NDA area. For example, a first inspection pattern TAG1 can be arranged in a space between the first driver 120 and the PA block area, and a second inspection pattern TAG2 can be arranged adjacent to the first inspection pattern TAG1 with the PA block area interposed between them. A third inspection pattern TAG3 can be arranged on the upper left side of display panel 110. However, the present in Petition 870250081403, dated 10 / 09 / 2025, pp. 62 / 90 The 57 / 57 convention is not limited to this, and the plurality of inspection patterns TAG1, TAG2, and TAG3 can be arranged anywhere in the area without displaying an NDA. Furthermore, the plurality of inspection patterns TAG1, TAG2, and TAG3 can be arranged in the space between the first driver 120 and the PA block area.

[00217] In one embodiment, the first inspection pattern TAG1 may be the inspection pattern illustrated in Figure 7, the second inspection pattern TAG2 may be the inspection pattern illustrated in Figure 11, and the third inspection pattern TAG3 may be the inspection pattern illustrated in Figure 13. For example, the first inspection pattern TAG1 may be an inspection pattern that can measure the capacitance of the rear channel, the second inspection pattern TAG2 may be an inspection pattern that can measure the capacitance of the front channel, and the third inspection pattern TAG3 may be an inspection pattern that can measure the capacitance of the dual channel.

[00218] In the present embodiments, the hydrogen content of the SCP semiconductor standard can be analyzed by measuring the capacitances of multiple channels of the inspection standard, which includes the plurality of TAG1, TAG2, and TAG3 inspection standards.

[00219] Upon completing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the modalities without substantially departing from the principles of the description. Therefore, the modalities described are used in a generic and descriptive sense only and not for purposes of limitation. Petition 870250081403, dated 10 / 09 / 2025, pp. 63 / 90

Claims

1 / 5 CLAIMS 1. A display device characterized in that it comprises: a substrate that includes a display area and a non-display area; a transistor disposed on the display area of ​​the substrate and including a semiconductor layer; and at least one inspection pattern disposed on the non-display area of ​​the substrate and including a semiconductor pattern, wherein the inspection pattern includes: a first conductive pattern and a second conductive pattern spaced apart from each other in a thickness direction with the semiconductor pattern interposed between them; and an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to the other portion of the semiconductor pattern, and the second conductive pattern is in contact with the semiconductor pattern.

2. Display device according to claim 1, characterized in that the first conductive pattern further includes a first insulating layer and a second insulating layer which are disposed on the substrate and interposed between the semiconductor pattern and the first conductive pattern.

3. Display device according to claim 1, characterized in that the semiconductor pattern includes a pattern channel region and a first conductive region and a second conductive region spaced apart from each other, with the pattern channel region interposed between them.

4. Display device according to claim 3, characterized in that the first conductive pattern overlaps the standard channel region.

5. Display device according to claim 3, characterized in that the inspection source electrode is connected to the first conductive area and the inspection drain electrode is connected to the second conductive area.

6. Display device according to claim 1, characterized in that the second conductive pattern is arranged over the semiconductor pattern and overlaps the first conductive pattern.

7. Display device according to claim 1, characterized in that it further comprises a third insulating layer disposed between the second conductor pattern and the semiconductor pattern, wherein the second conductor pattern is in contact with the semiconductor pattern through a first wayhole that penetrates through the third insulating layer.

8. Display device according to claim 1, characterized in that it further comprises a fourth insulating layer disposed between the inspection source electrode and the inspection drain electrode, and the second conductive pattern, wherein the inspection source electrode and the inspection drain electrode are connected to the semiconductor pattern through a second via hole and a third via hole that penetrate through the fourth insulating layer.

9. Display device according to claim 1, characterized in that it further comprises: a fourth insulating layer disposed over the second conductive pattern; and a first inspection electrode, a second inspection electrode, a third inspection electrode and a fourth inspection electrode disposed over the fourth insulating layer and spaced apart from each other.

10. Display device according to claim 9, characterized in that the first inspection electrode is connected to the first conductive standard, and the second inspection electrode is connected to the second conductive standard.

11. Display device according to claim 9, characterized in that the third inspection electrode extends from the inspection source electrode, and the fourth inspection electrode extends from the inspection drain electrode.

12. Display device according to claim 1, characterized in that the semiconductor layer of the transistor in the display area includes the same material as the semiconductor pattern of the inspection standard.

13. Display device according to claim 12, characterized in that the semiconductor layer of the transistor in the display area and the semiconductor pattern of the inspection pattern include an oxide semiconductor.

14. Display device according to claim 1, characterized in that it further comprises a connection pattern disposed between the first conductor pattern and the semiconductor pattern, wherein the first conductor pattern is electrically connected to the semiconductor pattern through the connection pattern.

15. Display device characterized in that it comprises: a substrate that includes a display area and a non-display area; a transistor disposed on the display area of ​​the substrate and that includes a semiconductor layer; and Petition 870250081403, dated 10 / 09 / 2025, page 66 / 90 4 / 5 an inspection pattern disposed on the non-display area of ​​the substrate and that includes a semiconductor pattern, wherein the inspection pattern includes: a first conductive pattern and a second conductive pattern spaced apart from each other in a thickness direction with the semiconductor pattern interposed between them; an inspection source electrode connected to one portion of the semiconductor pattern and an inspection drain electrode connected to the other portion of the semiconductor pattern; and a connection pattern disposed between the first conductive pattern and the semiconductor pattern, and the connection pattern is in contact with the first conductive pattern and the semiconductor pattern.

16. Display device according to claim 15, characterized in that the semiconductor layer of the transistor in the display area and the semiconductor pattern of the inspection pattern include an oxide semiconductor.

17. Display device according to claim 15, characterized in that it further comprises a first insulating layer and a second insulating layer interposed between the semiconductor pattern and the first conductor pattern, wherein the connection pattern is arranged in a first via hole that penetrates through the first insulating layer and the second insulating layer, and the first via hole overlaps the first conductor pattern and the semiconductor pattern.

18. Display device according to claim 15, characterized in that the semiconductor pattern includes a pattern channel region, a first conductive region and a second conductive region spaced apart from each other, with the pattern channel region interposed between these, and Petition 870250081403, dated 10 / 09 / 2025, page 67 / 90 5 / 5 the connection pattern is in contact with the pattern channel region.

19. Display device according to claim 18, characterized in that the first conductor pattern, the second conductor pattern and the connection pattern overlap the pattern channel region of the semiconductor pattern.

20. Display device according to claim 15, characterized in that it further comprises a third insulating layer disposed between the second conductive pattern and the second conductive pattern, wherein the second conductive pattern is spaced from the semiconductor pattern. Petition 870250081403, dated 10 / 09 / 2025, pp. 68 / 90

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