PACKAGES

Abstract

A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Description

1 / 58 PACKAGES CROSS-REFERENCE TO RELATED REQUESTS

[0001] This application claims priority and the benefit of (i) non-provisional U.S. patent application serial no. 18 / 607,170 filed with the U.S. Patent and Trademark Office on March 15, 2024, and (ii) provisional U.S. patent application serial no. 63 / 491,982 filed with the U.S. Patent and Trademark Office on March 24, 2023. Non-provisional U.S. patent application serial no. 18 / 607,170 claims priority and the benefit of provisional U.S. patent application serial no. 63 / 491,982. The entire content of both applications is incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes. Field

[0002] Several attributes refer to a package that includes an integrated device. Background

[0003] A package can include a substrate and integrated devices. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components can depend on many factors. There is a continuous need to provide packages that offer improved performance. In addition, there is a continuous need to include a package that includes a more compact form factor so that the package can be deployed in smaller devices. SUMMARY

[0004] Several attributes refer to a package Petition 870250081854, dated 11 / 09 / 2025, page 8 / 148 2 / 58 which includes an integrated device.

[0005] An example provides a package comprising a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; a encapsulation layer that at least partially encapsulates the first integrated device; a plurality of post-interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post-interconnects; a second integrated device coupled to the metallization portion via a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

[0006] Another example provides a package comprising a metallization portion; a first integrated device coupled to the metallization portion through a first plurality of solder interconnects, wherein one front side of the first integrated device faces the metallization portion; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of post-interconnects located in the encapsulation layer; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion through a third plurality of solder interconnects; an optical fiber coupled to the optical integrated device; and a package substrate coupled to the plurality of post-interconnects through Petition 870250081854, dated 11 / 09 / 2025, page 9 / 148 3 / 58 of a fourth plurality of solder interconnections. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Several attributes, nature and advantages may become evident from the detailed description set forth below when taken together with the drawings in which related reference characters correspondingly identify equivalent items throughout the description.

[0008] Figure 1 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0009] Figure 2 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0010] Figure 3 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0011] Figure 4 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0012] Figure 5 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0013] Figure 6 illustrates a cross-sectional profile view of an exemplary package comprising an integrated optical device.

[0014] Figure 7 illustrates a cross-sectional profile view of an exemplary integrated optical device.

[0015] Figure 8 illustrates a profile view in Petition 870250081854, dated 11 / 09 / 2025, page 10 / 148 4 / 58 cross-section of an exemplary integrated optical device.

[0016] Figures 9A to 9D illustrate an exemplary sequence for manufacturing a package comprising an integrated optical device.

[0017] Figure 10 illustrates an example flow diagram of a method for manufacturing a package comprising an integrated optical device.

[0018] Figure 11 illustrates various electronic devices that can integrate a chip, an integrated device, an integrated passive device (IPD), a passive component, a package and / or a device package described in the present invention. DETAILED DESCRIPTION

[0019] The following description gives specific details that provide a complete understanding of the various aspects of this disclosure. However, it will be understood by those skilled in the art that the aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the disclosure.

[0020] This disclosure describes a package comprising a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; an encapsulation layer that at least partially encapsulates the first integrated device; a Petition 870250081854, dated 11 / 09 / 2025, page 11 / 148 5 / 58 a plurality of post-interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post-interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device. The optical integrated device coupled to the package substrate provides a short distance for at least one electrical path for several integrated devices in the package. Furthermore, the optical integrated device being closer to the integrated devices provides a small IR drop, which helps improve the performance of the integrated devices and / or the package. Sample Package Comprising an Integrated Optical Device

[0021] Figure 1 illustrates a cross-sectional profile view of a package 100 that includes an integrated optical device. The package 100 includes an integrated optical device 101, a package substrate 102, an integrated device 103, and a metallization portion. 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnections 160 and an encapsulation layer 106.

[0022] The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122 (e.g., substrate interconnects). The integrated optical device 101 is coupled to the substrate of Petition 870250081854, dated 11 / 09 / 2025, page 12 / 148 6 / 58 Package 102. For example, the integrated optical device 101 may be embedded in the package substrate 102. In some implementations, the integrated optical device 101 may be located in a cavity of the package substrate 102. The integrated optical device 101 may be coupled to the package substrate 102 via an adhesive (not shown). An optical fiber 110 is coupled to the integrated optical device 101. The optical fiber 110 may be considered part of the package. 100. Optical fiber 110 can be coupled to another optical integrated device (not shown). The other optical integrated device can be coupled to another package or to a board. An example of an optical integrated device 101 is illustrated and described below in Figure 7. An optical integrated device may include the capability (i) to convert optical signal / energy into electrical signal / energy and / or (ii) to convert electrical signal / energy into optical signal / energy. For example, a signal may be received as an optical signal and may be converted into an electrical signal. Similarly, a signal may be received as an electrical signal and may be converted into an optical signal. An optical integrated device may send a signal as an optical signal and / or an electrical signal. More detailed examples of an optical integrated device are illustrated and described below at least in Figures 7 and 8.In some implementations, the optical integrated device 101 can be implemented by the optical integrated device 700 and / or the optical integrated device 800.

[0023] The encapsulation layer 106 can at least partially encapsulate the integrated device 103, the integrated device 105, and the plurality of post-interconnections 160. The integrated device 103 is coupled to Petition 870250081854, dated 11 / 09 / 2025, page 13 / 148 7 / 58 Package substrate 102 via multiple solder interconnects 123. One front side of integrated device 103 faces the package substrate 102. For example, a surface on the front side of integrated device 103 can be directed in one direction, towards the package substrate 102. Integrated device 105 is coupled to package substrate 102 via multiple solder interconnects 123. One front side of integrated device 105 faces the package substrate 102. For example, a surface on the front side of integrated device 105 can be directed in one direction, towards the package substrate 102. Multiple post-interconnects 160 are coupled to package substrate 102 via multiple solder interconnects 123. There is an underfill 125 between the substrate of package 102 and encapsulation layer 106.The underfill 125 can laterally encircle the plurality of solder interconnections 123. The underfill 125 can be coupled to and touch the package substrate 102, the plurality of solder interconnections 123, the encapsulation layer 106, the integrated device 103, and the integrated device 105.

[0024] The metallization portion 104 is coupled to the encapsulation layer 106 and the plurality of post-interconnections 160. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnections 142. The metallization portion 104 may be a redistribution portion. The plurality of metallization interconnections 142 may include a plurality of redistribution interconnections. The plurality of post-interconnections Petition 870250081854, dated 11 / 09 / 2025, page 14 / 148 8 / 58 Interconnections 160 is coupled to the metallization interconnections of the plurality of metallization interconnections 142 of the metallization portion 104. The rear side of the integrated device 103 may face the metallization portion 104. For example, a surface on the rear side of the integrated device 103 may be directed in one direction, towards the metallization portion 104. A rear side of the integrated device 105 may face the metallization portion 104. For example, a surface on the rear side of the integrated device 105 may be directed in one direction, towards the metallization portion 104. The bottom surface of the metallization portion 104 may be coupled to the encapsulation layer 106.

[0025] The passive device 111 can be coupled to a top surface of the metallization portion 104 through a plurality of solder interconnections 112. For example, the passive device 111 can be coupled to the metallization interconnections of the plurality of metallization interconnections 142 through the plurality of solder interconnections 112.

[0026] The integrated device 109 can be coupled to a top surface of the metallizing portion 104 through a plurality of solder interconnections 190. For example, the integrated device 109 can be coupled to the metallizing interconnections of the plurality of metallizing interconnections 142 through the plurality of solder interconnections 190. The integrated device 130 can be coupled to a top surface of the metallizing portion 104 through a plurality of solder interconnections 131. For example, the integrated device 130 can be coupled to the interconnections Petition 870250081854, dated 11 / 09 / 2025, page 15 / 148 9 / 58 of metallization of the plurality of metallization interconnections 142 through the plurality of solder interconnections 131.

[0027] Integrated device 132 is coupled to integrated device 130 through a plurality of solder interconnections 133. Integrated device 134 is coupled to integrated device 132 through a plurality of solder interconnections 135. Integrated device 130, integrated device 132 and integrated device 134 can be stacked integrated devices.

[0028] Connector socket 107 is coupled to the top surface of the metallized portion 104 through a plurality of solder interconnections 170. Connector socket 107 is configured to be electrically coupled to connector socket 113. Connector socket 107 is configured to provide an electrical path for power. Connector socket 107 is configured to provide an electrical path for ground. Connector socket 107 can be coupled to connector socket 113 through one or more wires.

[0029] Package 100 is coupled to a plate 108 through a plurality of solder interconnects 183. Plate 108 includes at least one dielectric layer of plate 180 and a plurality of plate interconnects 182. Connector socket 113 is coupled to plate 108 through a plurality of solder interconnects 114. A connector socket (e.g., 107, 113) may include a plurality of connector interconnects. A connector socket may include a connector housing, where the plurality of connector interconnects may be located at least partially in the housing. Petition 870250081854, dated 11 / 09 / 2025, page 16 / 148 10 / 58 connector. The one or more wires that are coupled to the connector socket may include wire interconnections and a dielectric layer surrounding the one or more wires.

[0030] Optical fiber 110 is coupled to the optical integrated device 101. Optical fiber 110 may extend through the package substrate 102. Optical fiber 110 may extend through a cavity in the package substrate 102. In some implementations, optical fiber 110 may extend onto the board 108. In some implementations, optical fiber 110 may extend between the package substrate 102 and the board 108. One or more optical signals may travel to and / or from the optical integrated device 101 via optical fiber 110.

[0031] The integrated device 103 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 151 that includes a solder interconnection of the plurality of solder interconnections 123. The integrated device 105 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 153 that includes a solder interconnection of the plurality of solder interconnections 123. The integrated device 103 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path that includes a solder interconnection of the plurality of solder interconnections 123, the optical integrated device 101, and another solder interconnection of the plurality of solder interconnections. The integrated device 130 can be configured to be electrically coupled to the optical integrated device 101 via Petition 870250081854, dated 11 / 09 / 2025, p. 17 / 148 11 / 58 an electrical path 155 that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104, a back interconnection of the plurality of back interconnections 160, and a solder interconnection of the plurality of solder interconnections 123. The electrical path 155 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include a pad interconnection of the integrated device 130, a through-substrate path of the integrated device 130, a solder interconnection of the plurality of solder interconnections 133, a pad interconnection of the integrated device 132, a through-substrate path of the integrated device 132, a solder interconnection of the plurality of solder interconnections 135, and a pad interconnection of the integrated device 134.In some implementations, there may be pillar interconnections between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In these cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnections mentioned above.

[0032] The integrated device 130 can be configured to be electrically coupled to the integrated device 103 via an electrical path 157 which includes a plurality of solder interconnections 131, metallization interconnections 104, a plurality of post-interconnections 160, a plurality of solder interconnections Petition 870250081854, dated 11 / 09 / 2025, page 18 / 148 12 / 58 of solder interconnections 123, package substrate interconnections 102 and other solder interconnection of the plurality of solder interconnections 123. The electrical path 157 may include an electrical path between the integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include a chip interconnect of integrated device 130, a through-substrate path of integrated device 130, a solder interconnect of the plurality of solder interconnects 133, a chip interconnect of integrated device 132, a through-substrate path of integrated device 132, a solder interconnect of the plurality of solder interconnects 135, and a chip interconnect of integrated device 134. In some implementations, there may be pillar interconnections between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnections mentioned above.

[0033] The integrated device 130 can be configured to be electrically coupled to the integrated device 105 via an electrical path 159 that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104, a post-interconnection of the plurality of post-interconnections 160, a solder interconnection of the plurality of solder interconnections 123, package substrate interconnections 102 and another solder interconnection of the plurality of solder interconnections 123. The electrical path 159 can Petition 870250081854, dated 11 / 09 / 2025, page 19 / 148 13 / 58 include an electrical path between the integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include a chip interconnect of integrated device 130, a through-substrate path of integrated device 130, a solder interconnect of the plurality of solder interconnects 133, a chip interconnect of integrated device 132, a through-substrate path of integrated device 132, a solder interconnect of the plurality of solder interconnects 135, and a chip interconnect of integrated device 134. In some implementations, there may be pillar interconnections between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnections mentioned above.

[0034] In some implementations, an optical signal can be received by the optical integrated device 101 through the optical fiber 110. The optical signal can be converted into an electrical signal by the optical integrated device 101 and the electrical signal can be sent to the integrated device 103, the integrated device 105 and / or the integrated device 130, using one or more of the electrical paths described above.

[0035] In some implementations, an electrical signal can be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signal can be converted into an optical signal by the optical integrated device 101, and the optical signal can be sent through the optical fiber 110. Petition 870250081854, dated 11 / 09 / 2025, page 20 / 148 14 / 58

[0036] Integrated device 103 may be a system on a chip (SoC). Integrated device 109 may include a power management integrated circuit (PMIC). Passive device 111 may include a capacitor. Integrated device 130, integrated device 132, and / or integrated device 134 may include memory. An electrical path between integrated device 109 and integrated device 130 may include a plurality of solder interconnects 190, a plurality of metallization interconnects 142, and a plurality of solder interconnects 131. An electrical path between integrated device 109 and integrated device 134 may include the electrical path between integrated device 130 and integrated device 134, as described above.

[0037] In some implementations, the optical integrated device 101 can be configured to operate as a bridge. The integrated device 103 can be configured to be electrically coupled to the integrated device 105 through the integrated device 101. For example, an electrical path between the integrated device 103 and the integrated device 105 may include the optical integrated device 101. An electrical path between the integrated device 103 and the integrated device 105 may include the electrical path 151 (as described above), interconnections of the optical integrated device 101, and the electrical path 153 (as described above).

[0038] Figure 2 illustrates a profile view in Petition 870250081854, dated 11 / 09 / 2025, page 21 / 148 15 / 58 cross-section of a package 200 that includes an integrated optical device. The package 200 includes an integrated optical device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnects 160, an encapsulation layer 106, at least one rear-side power rail interconnect 203, and at least one rear-side power rail interconnect 205.

[0039] At least one rear-side power rail interconnect 203 may be considered part of the integrated device 103. For example, at least one rear-side power rail interconnect 203 may be located on a wafer substrate of the integrated device 103. The rear-side power rail interconnect 203 may include track interconnects and / or through-substrate vias. The rear-side power rail interconnect 203 may be considered part of the rear side of the integrated device 103. At least one rear-side power rail interconnect 205 may be considered part of the integrated device 105. For example, at least one rear-side power rail interconnect 205 may be located on a wafer substrate of the integrated device 105. The rear-side power rail interconnect 205 may include track interconnects and / or through-substrate vias.The rear-side power rail interconnection 205 can be considered part of the rear side of the... Petition 870250081854, dated 11 / 09 / 2025, page 22 / 148 16 / 58 integrated device 105.

[0040] Package 200 is similar to package 100. However, some of the components of package 200 are located and / or coupled differently from some of the components of package 100.

[0041] The integrated device 103 is coupled to a bottom surface of the metallizing portion 104 through a plurality of solder interconnections 223. A front side of the integrated device 103 may be facing the metallizing portion 104. For example, a surface on the front side of the integrated device 103 may be directed in one direction, towards the metallizing portion 104. The integrated device 105 is coupled to a bottom surface of the metallizing portion 104 through a plurality of solder interconnections 225. A front side of the integrated device 105 may be facing the metallizing portion 104. For example, a surface on the front side of the integrated device 105 may be directed in one direction, towards the metallizing portion 104. The integrated device 109 is coupled to a bottom surface of the metallizing portion 104 through a plurality of solder interconnections. 190.The passive device 111 is coupled to a bottom surface of the metallization portion 104 through a plurality of solder interconnections 112. The encapsulation layer 106 may at least partially encapsulate the integrated device 103, the integrated device 105, the integrated device 109, the passive device 111, the rear-side power rail interconnection 203, the rear-side power rail interconnection 205, and the plurality of post-interconnections 160. The encapsulation layer 106 may... Petition 870250081854, dated 11 / 09 / 2025, page 23 / 148 17 / 58 include a mold, a resin and / or an epoxy. A compression molding process, a transfer molding process or a liquid injection molding process may be used to form the encapsulation layer 106.

[0042] Package 200 is coupled to board 108 via a plurality of solder interconnections 183. Connector socket 113 is coupled to board 108 via a plurality of solder interconnections 114.

[0043] The integrated device 130 can be configured to be electrically coupled to the integrated device 103 via an electrical path 257 that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104, and a solder interconnection of the plurality of solder interconnections 223. The integrated device 130 can be configured to be electrically coupled to the integrated device 105 via an electrical path 259 that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104, and a solder interconnection of the plurality of solder interconnections 225. The electrical path 257 can include an electrical path between the integrated device 130 and the integrated device 134.The electrical path between integrated device 130 and integrated device 134 may include a chip interconnect of integrated device 130, a through-substrate path of integrated device 130, a solder interconnect of the plurality of solder interconnects 133, a chip interconnect of integrated device 132, a through-substrate path of integrated device 132. Petition 870250081854, dated 11 / 09 / 2025, page 24 / 148 18 / 58 a solder interconnection of the plurality of solder interconnections 135 and a pad interconnection of the integrated device 134. In some implementations, there may be pillar interconnections between (i) the integrated device 130 and the integrated device 132 and / or (ii) the integrated device 132 and the integrated device 134. In these cases, the electrical path between the integrated device 130 and the integrated device 134 may also include the pillar interconnections mentioned above. The electrical path 259 may include an electrical path between the integrated device 130 and the integrated device 134.The electrical path between integrated device 130 and integrated device 134 may include a chip interconnect of integrated device 130, a through-substrate path of integrated device 130, a solder interconnect of the plurality of solder interconnects 133, a chip interconnect of integrated device 132, a through-substrate path of integrated device 132, a solder interconnect of the plurality of solder interconnects 135, and a chip interconnect of integrated device 134. In some implementations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects mentioned above.

[0044] The integrated device 130 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 255 that Petition 870250081854, dated 11 / 09 / 2025, page 25 / 148 19 / 58 includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104, a rear interconnection of the plurality of rear interconnections 160, and a solder interconnection of the plurality of solder interconnections 123. The electrical path 255 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include a pad interconnection of the integrated device 130, a through-substrate path of the integrated device 130, a solder interconnection of the plurality of solder interconnections 133, a pad interconnection of the integrated device 132, a through-substrate path of the integrated device 132, a solder interconnection of the plurality of solder interconnections 135, and a pad interconnection of the integrated device 134.In some implementations, there may be pillar interconnections between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In these cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnections mentioned above.

[0045] In some implementations, the integrated device 103 can be configured to be electrically coupled to the integrated device 105 through the plurality of solder interconnections 223, metallization interconnections 142 and the plurality of solder interconnections 225. Petition 870250081854, dated 11 / 09 / 2025, page 26 / 148 20 / 58

[0046] In some implementations, integrated device 103 can be configured to be electrically coupled to integrated device 105 via solder interconnects of the plurality of solder interconnects 123, optical integrated device 101, and other solder interconnects of the plurality of solder interconnects 123. In some implementations, optical integrated device 101 can be configured as a bridge. In some implementations, optical integrated device 101, integrated device 103, and / or integrated device 105 can be one or more chiplets. In some implementations, integrated device 103 can be fabricated using a first technology node, and integrated device 105 can be fabricated using a second technology node that is not as advanced as the first technology node.The integrated optical device 101 can be manufactured using a third technology node that is different from the first technology node and / or the second technology node.

[0047] In some implementations, an optical signal can be received by the optical integrated device 101 through the optical fiber 110. The optical signal can be converted into an electrical signal by the optical integrated device 101 and the electrical signal can be sent to the integrated device 103, the integrated device 105 and / or the integrated device 130, using one or more of the electrical paths described above.

[0048] In some implementations, an electrical signal can be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signal can be converted into an optical signal by the optical integrated device 101, and the signal Petition 870250081854, dated 11 / 09 / 2025, page 27 / 148 21 / 58 optical can be sent via 110 optical fiber.

[0049] The integrated optical device 101 is coupled to the package substrate 102. For example, the integrated optical device 101 may be embedded in the package substrate 102. In some implementations, the integrated optical device 101 may be located in a cavity of the package substrate 102. The integrated optical device 101 may be coupled to the package substrate 102 via an adhesive (not shown). An optical fiber 110 is coupled to the integrated optical device 101. The optical fiber 110 may be considered part of the package 200.

[0050] Power may be supplied to integrated device 103 via a rear side of integrated device 103. For example, an electrical power path to integrated device 103 may include multiple interconnections 122, at least one solder interconnection 123, and at least one rear side power rail interconnection 203. Similarly, power may be supplied to integrated device 105 via a rear side of integrated device 105. For example, an electrical power path to integrated device 105 may include multiple interconnections 122, at least one solder interconnection 123, and at least one rear side power rail interconnection 205.

[0051] Figure 3 illustrates a cross-sectional profile view of a 300 package that includes an integrated optical device. The 300 package includes an integrated optical device 101, a package substrate 102, a device Petition 870250081854, dated 11 / 09 / 2025, page 28 / 148 22 / 58 integrated 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnections 160, an encapsulation layer 106, at least one rear-side power rail interconnection 203 and at least one rear-side power rail interconnection 205.

[0052] Package 300 is similar to package 200. However, some of the components of package 300 are located and / or coupled differently from some of the components of package 200.

[0053] For example, the integrated optical device 101 is coupled to a top surface of the metallization portion 104 through a plurality of solder interconnections 310. An example of an integrated optical device 101 is illustrated and described below in Figure 8. The integrated optical device 101 is coupled to an integrated optical device 301 through the optical fiber 110. The integrated optical device 301 is coupled to the board 108. The integrated optical device 301 can be coupled to the board 108 through a plurality of solder interconnections.

[0054] The integrated device 130 can be configured to be electrically coupled to the integrated device 103 via an electrical path 257 which includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104 and a solder interconnection of the plurality of solder interconnections 223. The integrated device 130 can be configured to be electrically coupled to Petition 870250081854, dated 11 / 09 / 2025, page 29 / 148 23 / 58 integrated device 105 through an electrical path that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104 and a solder interconnection of the plurality of solder interconnections 225.

[0055] The integrated device 130 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 355 that includes a solder interconnection of the plurality of solder interconnections 131, metallization interconnections of the metallization portion 104 and a solder interconnection of the plurality of solder interconnections 310. The electrical path 355 may include an electrical path between the integrated device 130 and the integrated device 134.The electrical path between integrated device 130 and integrated device 134 may include a chip interconnect of integrated device 130, a through-substrate path of integrated device 130, a solder interconnect of the plurality of solder interconnects 133, a chip interconnect of integrated device 132, a through-substrate path of integrated device 132, a solder interconnect of the plurality of solder interconnects 135, and a chip interconnect of integrated device 134. In some implementations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects mentioned above.

[0056] The integrated device 103 can be Petition 870250081854, dated 11 / 09 / 2025, page 30 / 148 24 / 58 configured to be electrically coupled to the integrated optical device 101 via an electrical path 353 which includes a solder interconnection of the plurality of solder interconnections 223, metallization interconnections of the metallization portion 104 and a solder interconnection of the plurality of solder interconnections 310.

[0057] The integrated device 105 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 357 which includes a solder interconnection of the plurality of solder interconnections 225, metallization interconnections of the metallization portion 104 and a solder interconnection of the plurality of solder interconnections 310.

[0058] In some implementations, an optical signal can be received by the optical integrated device 101 through the optical fiber 110. The optical signal can be converted into an electrical signal by the optical integrated device 101 and the electrical signal can be sent to the integrated device 103, the integrated device 105 and / or the integrated device 130, using one or more of the electrical paths described above.

[0059] In some implementations, an electrical signal can be received by the optical integrated device 101 through one or more of the electrical paths described above. The electrical signal can be converted into an optical signal by the optical integrated device 101, and the optical signal can be sent through the optical fiber 110.

[0060] Figure 4 illustrates a cross-sectional profile view of a 400 package that includes an integrated optical device. The 400 package includes an integrated optical device 101, a package substrate 102, a device Petition 870250081854, dated 11 / 09 / 2025, page 31 / 148 25 / 58 integrated 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnections 160, an encapsulation layer 106, at least one rear-side power rail interconnection 203 and at least one rear-side power rail interconnection 205.

[0061] Package 400 is similar to package 300. However, some of the components of package 400 are located and / or coupled differently from some of the components of package 300. For example, package substrate 102 includes an interconnect 122a and an interconnect 122b. Interconnect 122a and interconnect 122b are configured as a heat spreader on package substrate 102. Plate 108 includes a plate interconnect 182a and a plate interconnect 182b. A heat sink 403 is coupled to plate 108. A thermal interface material can be used to couple heat sink 403 to plate 108. A heat sink 405 is coupled to plate 108. A thermal interface material can be used to couple heat sink 405 to plate 108.The heat generated by the integrated device 103 and / or the rear side power rail interconnection 203 can be dissipated through a solder interconnection of the plurality of solder interconnections 123, the interconnection 122a, a solder interconnection of the plurality of solder interconnections 183, a plate interconnection 182a, and the heat sink 403. The heat generated by the integrated device 105 and / or the rear side power rail interconnection. Petition 870250081854, dated 11 / 09 / 2025, page 32 / 148 26 / 58 rear 205 can dissipate heat through a solder interconnection of the plurality of solder interconnections 123, the interconnection 122b, a solder interconnection of the plurality of solder interconnections 183, a plate interconnection 182b and the heat sink 405.

[0062] In some implementations, integrated device 103 may be a first chiplet and integrated device 105 may be a second chiplet. Integrated device 103 may be configured to perform a first plurality of functions and / or operations. Integrated device 105 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations. In some implementations, integrated device 103 may be manufactured using a first technology node, and integrated device 105 may be manufactured using a second technology node that is not as advanced as the first technology node.

[0063] Figure 5 illustrates a cross-sectional profile view of a 500 package that includes an integrated optical device. The 500 package includes an integrated optical device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnects 160, an encapsulation layer 106, at least one rear-side power rail interconnect 203, and at least one Petition 870250081854, dated 11 / 09 / 2025, page 33 / 148 27 / 58 rear side power rail interconnection 205.

[0064] Package 500 is similar to package 300 and / or package 400. However, some of the components in package 500 are located and / or coupled differently from some of the components in package 300 and / or package 400.

[0065] As shown in Figure 5, the integrated optical device 101 is coupled to a top surface (e.g., second integrated device) of the metallization portion 104 through a plurality of solder interconnections 310. The integrated device 109 is coupled to a top surface of the metallization portion 104 through a plurality of solder interconnections 190. The passive device 111 is coupled to a top surface of the metallization portion 104 through a plurality of solder interconnections 112.

[0066] In some implementations, an optical signal can be received by the optical integrated device 101 through the optical fiber 110. The optical signal can be converted into an electrical signal by the optical integrated device 101 and the electrical signal can be sent to the integrated device 103, the integrated device 105 and / or the integrated device 130, using one or more of the electrical paths described above at least in Figure 3.

[0067] In some implementations, an electrical signal can be received by the optical integrated device 101 through one or more of the electrical paths described above, at least in Figure 3. The electrical signal can be converted into an optical signal by the optical integrated device 101, and the optical signal can be sent through the fiber. Petition 870250081854, dated 11 / 09 / 2025, page 34 / 148 28 / 58 optical 110.

[0068] Figure 6 illustrates a cross-sectional profile view of a package 600 that includes an optical integrated device. The package 600 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post-interconnects 160, an encapsulation layer 106, at least one rear-side power rail interconnect 203, and at least one rear-side power rail interconnect 205.

[0069] Package 600 is similar to package 300 and / or package 400. However, some of the components in package 600 are located and / or coupled differently from some of the components in package 300 and / or package 400.

[0070] Package substrate 102 includes an interconnect 122a and an interconnect 122b. Interconnect 122a and interconnect 122b are configured as a heat spreader on package substrate 102. Board 108 includes a board interconnect 182a and a board interconnect 182b. A heat sink 403 is attached to board 108. A thermal interface material may be used to attach heat sink 403 to board 108. A heat sink 405 is attached to board 108. A thermal interface material may be used to attach heat sink 405 to board 108. The heat that is generated by the integrated device 103 and / or the rear-side power rail interconnect Petition 870250081854, dated 11 / 09 / 2025, page 35 / 148 29 / 58 203 can be dissipated through a solder interconnection of the plurality of solder interconnections 123, interconnection 122a, a solder interconnection of the plurality of solder interconnections 183, a plate interconnection 182a and the heat sink 403. The heat that is generated by the integrated device 105 and / or the rear-side power rail interconnection 205 can be dissipated through a solder interconnection of the plurality of solder interconnections 123, interconnection 122b, a solder interconnection of the plurality of solder interconnections 183, a plate interconnection 182b and the heat sink 405.

[0071] In some implementations, an optical signal can be received by the optical integrated device 101 through the optical fiber 110. The optical signal can be converted into an electrical signal by the optical integrated device 101 and the electrical signal can be sent to the integrated device 103, the integrated device 105 and / or the integrated device 130, using one or more of the electrical paths described above at least in Figure 3.

[0072] In some implementations, an electrical signal can be received by the optical integrated device 101 through one or more of the electrical paths described above at least in Figure 3. The electrical signal can be converted into an optical signal by the optical integrated device 101, and the optical signal can be sent through the optical fiber 110.

[0073] Note that any of the packages may include additional components and / or other components. For example, an integrated device may be replaced by a stack of integrated devices. For example, the Petition 870250081854, dated 11 / 09 / 2025, page 36 / 148 30 / 58 integrated device 103 and / or integrated device 105 can each be replaced by a stack of integrated devices (for example, similar to integrated device 130, integrated device 132, and integrated device 134). The stack of integrated devices may include integrated devices with their fronts facing each other, integrated devices with their front and rear facing each other, and / or integrated devices with their rear facing each other. In another example, a substrate and / or an interposer may be located between package substrate 102 and integrated device 103 and / or integrated device 105.

[0074] It is noted that any of the plurality of weld interconnects described in the disclosure can be implemented as a plurality of weld overhang interconnects. A weld overhang interconnect may include a pillar interconnect and a weld interconnect. In some implementations, a plurality of weld overhang interconnects may include a plurality of micro weld overhang interconnects. A micro weld overhang interconnect may be similar to a weld overhang interconnect. However, the micro weld overhang interconnect may have smaller dimensions than a weld overhang interconnect to accommodate finer interconnect pitches.For example, in some implementations, the plurality of 123 solder interconnections can be implemented as a plurality of micro solder overhang interconnections, while the plurality of 183 solder interconnections can be implemented as a plurality of interconnections of... Petition 870250081854, dated 11 / 09 / 2025, page 37 / 148 31 / 58 solder overhang. In some implementations, one or more solder overhang interconnections may have a pitch (e.g., minimum pitch) in a range of about 80 to 120 micrometers. In some implementations, one or more micro solder overhang interconnections may have a pitch (e.g., minimum pitch) in a range of about 25 to 50 micrometers. Examples of Integrated Optical Devices

[0075] Figure 7 illustrates an exemplary optical integrated device 700. The optical integrated device 700 may be the optical integrated device 101 described in Figures 1 to 6. The optical integrated device 700 includes a substrate 702 (e.g., silicon substrate), an optical device 704, a waveguide 706, a waveguide 708, a waveguide 709, an oxide layer 710, a plurality of interconnects 730, and a fiber ferrule 720. The optical fiber 110 is coupled to the waveguide 706 and the fiber ferrule 720. An optical signal from the optical fiber 110 may travel through the waveguide 706, the waveguide 709, and the waveguide 708. The optical signal may be processed by the optical device 704, where the optical signal may be converted into an electrical signal. The electrical signal can be sent through the plurality of interconnections 730. The oxide layer 710 can surround the waveguide 709 and the waveguide 708.The 709 waveguide can include silicon (S silicon) or silicon nitride. The 709 waveguide can extend through a 702 substrate thickness as a through silicon via (TSV). The 708 waveguide can include silicon (S), germanium (Ge), or silicon nitride. Petition 870250081854, dated 11 / 09 / 2025, p. 38 / 148 32 / 58

[0076] Figure 8 illustrates an exemplary optical integrated device 800. The optical integrated device 800 may be the optical integrated device 101 described in Figures 1 to 6. The optical integrated device 800 includes a substrate 702 (e.g., silicon mouse substrate), an optical device 704, a waveguide 706, a plurality of interconnects 830, a plurality of interconnects 840, and a fiber ferrule 720. The optical fiber 110 is coupled to the waveguide 706 and the fiber ferrule 720. An optical signal from the optical fiber 110 can travel through the waveguide 706. The optical signal can be processed by the optical device 704, where the optical signal can be converted into an electrical signal. The electrical signal can be sent through the plurality of interconnects 830 and / or the plurality of interconnects 840.

[0077] Although not shown, the 720 fiber ferrule can be coupled to a carrier (e.g., silicon carrier) and the carrier is used to help couple the 720 fiber ferrule to the 706 waveguide. In some implementations, there may be more than one optical fiber.

[0078] Different implementations may use different waveguide designs. In some implementations, a waveguide may include a silicon crest waveguide, a silicon rib waveguide, a silicon slot waveguide, and / or a silicon nitride crest waveguide. However, other implementations may use other waveguide designs. For example, some implementations may use germanium in conjunction with silicon.

[0079] An integrated device (e.g., 103) may include a chip (e.g., chip) Petition 870250081854, dated 11 / 09 / 2025, p. 39 / 148 33 / 58 exposed semiconductor). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, a power management processor and / or combinations thereof.An integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc.). An integrated device may include transistors. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. In some implementations, an optical integrated device (e.g., 101) may be a chiplet. A chiplet may be manufactured using a process that provides better yields compared to other processes used to manufacture other types of integrated devices, which may reduce the total manufacturing cost of a chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets may be... Petition 870250081854, dated 11 / 09 / 2025, page 40 / 148 34 / 58 configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, multiple chiplets may be used to perform the functionalities of one or more chips (e.g., more than one integrated device). Thus, for example, a single integrated device may be divided into multiple chiplets. As mentioned above, the use of multiple chiplets performing multiple functions can reduce the total cost of a package, compared to using a single chip to perform all the functions of a package. In some implementations, one or more of the chiplets and / or one or more integrated devices (e.g., 103) described in the disclosure may be manufactured using the same technology node or two or more different technology nodes.For example, an integrated device might be manufactured using a first technology node, and a chiplet might be manufactured using a second technology node that is not as advanced as the first technology node. In this example, the integrated device might include components (e.g., interconnects, transistors) that have a first minimum size, and the chiplet might include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in a package might be manufactured using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in a package might be manufactured using the same technology node or different technology nodes. Petition 870250081854, dated 11 / 09 / 2025, page 41 / 148 35 / 58

[0080] A technology node can refer to a specific manufacturing process and / or technology used to manufacture an integrated device and / or chiplet. A technology node can specify the smallest possible size (e.g., minimum size) that can be manufactured (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes that produce components (e.g., traces, transistors) with fine details are more expensive and may have higher yield losses than a technology node that produces components (e.g., traces, transistors) with less fine details. In this way, more advanced technology nodes may be more expensive and may have higher yield losses than less advanced technology nodes.When all the functions of a package are implemented in single embedded devices, the same technology node is used to manufacture the entire embedded device, even if some of the embedded device functions do not need to be manufactured using that particular technology node. In this way, the embedded device is locked into a single technology node. To optimize the cost of a package, some functions may be implemented in different embedded devices and / or chiplets, where different embedded devices and / or chiplets can be manufactured using different technology nodes to reduce overall costs. For example, functions that require the use of the most advanced technology node may be implemented in one embedded device, and functions that can be implemented using a less advanced technology node may be. Petition 870250081854, dated 11 / 09 / 2025, page 42 / 148 36 / 58 implemented in another embedded device and / or in one or more chiplets. An example would be an embedded device, manufactured using a first technology node (e.g., a more advanced technology node), which is configured to provide computing applications and at least one chiplet, which is manufactured using a second technology node, which is configured to provide other functionalities, where the second technology node is not as expensive as the first technology node, and where the second technology node manufactures components with minimum sizes that are larger than the minimum sizes of the components manufactured using the first technology node.Examples of computing applications might include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packaging as many transistors as possible in an integrated device. This is why an integrated device configured for computing applications might be manufactured using the most advanced technology node available, while other chiplets might be manufactured using less advanced technology nodes, since those chiplets may not require as many transistors. In this way, combining the use of different technology nodes (which may have different associated throughput losses) for different integrated devices and / or chiplets can reduce the overall cost of a package, compared to using a single integrated device to perform all the package functions.

[0081] Another advantage of dividing functions across multiple integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign. Petition 870250081854, dated 11 / 09 / 2025, page 43 / 148 37 / 58 each integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by altering the design of the first integrated device while preserving the design of the first chiplet. In this way, the first chiplet can be reused with the improved and / or differently configured first integrated device. This saves costs by not having to redesign the first chiplet when packages with improved integrated devices are manufactured. Example Sequence for Manufacturing a Package Comprising an Integrated Optical Device

[0082] In some implementations, the fabrication of a package includes several processes. Figures 9A to 9B illustrate an example sequence for providing or fabricating a package. In some implementations, the sequence in Figures 9A to 9D can be used to provide or fabricate package 300 of Figure 3. However, the process in Figures 9A to 9D can be used to fabricate any of the packages (e.g., 100, 200, 400, 500, 600) described in the disclosure.

[0083] It should be noted that the sequence of Figures 9A to 9D may combine one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified. In some implementations, one or more processes may be swapped or replaced without departing from the scope of the disclosure.

[0084] Stage 1, as shown in Figure 9A, illustrates a state after a metallization portion 104 has been provided to a carrier 900. The metallization portion Petition 870250081854, dated 11 / 09 / 2025, page 44 / 148 38 / 58 104 includes at least one dielectric layer 140 and a plurality of metallization interconnections 142. The metallization portion 104 can be formed on the carrier 900. A deposition process, a masking process, an exposure process, a pickling process, a plating process and / or a stripping process can be used to form the metallization portion 104. A deposition, lamination, exposure, development and / or pickling process can be used to form and pattern at least one dielectric layer. A plating process and / or a patterning process can be used to form the metallization interconnections.

[0085] Stage 2 illustrates a state after a plurality of post-interconnections 160 is formed on, and coupled to, the metallization portion 104. The plurality of post-interconnections 160 is coupled to the plurality of metallization interconnections 142. A plating process can be used to form the plurality of post-interconnections 160.

[0086] Stage 3 illustrates a state after a plurality of integrated devices and / or at least one passive device are coupled to a surface of the metallizing portion 104. For example, the integrated device 103 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 223. For example, the front side of the integrated device 103 is coupled to a surface of the metallizing portion 104. The integrated device 103 may include the rear-side power rail interconnection 203. The integrated device 105 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 225. For example, the front side of Petition 870250081854, dated 11 / 09 / 2025, page 45 / 148 39 / 58 Integrated device 105 is coupled to a surface of the metallizing portion 104. Integrated device 105 may include rear-side power rail interconnection 205. Integrated device 109 is coupled to a surface of the metallizing portion 104 via a plurality of solder interconnections 190. Passive device 111 is coupled to a surface of the metallizing portion 104 via a plurality of solder interconnections 112. One or more reflow soldering processes may be used to couple the plurality of integrated devices and / or passive devices to the metallizing portion 104.

[0087] Stage 4, as shown in Figure 9B, illustrates a state after an encapsulation layer 106 is formed over, and coupled to, the metallization portion 104. The encapsulation layer 106 may include a mold, a resin, and / or an epoxy. A compression molding process, a transfer molding process, or a liquid injection molding process may be used to form the encapsulation layer 106. The encapsulation may encapsulate (e.g., partially encapsulate) the integrated device 103 / rear-side power rail interconnect 203, the integrated device 105 / rear-side power rail interconnect 205, the integrated device 109, the passive device 111, and the plurality of post-interconnects 160.

[0088] Stage 5 illustrates a state after carrier 900 is decoupled from metallization portion 104.

[0089] Stage 6 illustrates a state after a 102 package substrate is coupled to the rear-side power rail interconnects (e.g., 203, 205) of Petition 870250081854, dated 11 / 09 / 2025, page 46 / 148 40 / 58 integrated devices (e.g., 103, 105), a plurality of post-interconnections 160 through a plurality of solder interconnections 123. A reflow soldering process can be used to couple the power rail interconnections and the plurality of post-interconnections 160 through the plurality of solder interconnections 123. The package substrate 102 can be coupled to the back side of the integrated device 103 and to the back side of the integrated device 105. The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnections 122. In some implementations, the package substrate 102 may include an optical integrated device 101 and / or an optical integrated device 101 may be coupled to the package substrate 102. As shown and described in Figures 1 and 2, in some implementations, an optical integrated device 101 It can be part of the 102 package substrate.The integrated optical device 101 may be located in a cavity of the package substrate 102. The integrated optical device 101 may be attached to the package substrate 102 by means of an adhesive.

[0090] Stage 7 illustrates a state after an underfill 125 is provided between the package substrate 102 and the encapsulation layer 106. The underfill 125 can be formed so that the underfill 125 laterally surrounds the plurality of solder interconnects 123. The underfill 125 can be coupled to, and touch, the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated device 103 and / or the integrated device 105.

[0091] Stage 8, as shown in Figure 9C, illustrates a state after one or more integrated devices are coupled to a surface of the metallization portion 104. Petition 870250081854, dated 11 / 09 / 2025, page 47 / 148 41 / 58 For example, an integrated device stack can be coupled to the metallization portion 104. In one example, an integrated device stack comprising an integrated device 130, an integrated device 132, and an integrated device 134 can be coupled to the metallization portion 104 via a reflow soldering process.

[0092] Stage 9 illustrates a state after the substrate package 102 is coupled to a board 108 through a plurality of solder interconnects 183. A reflow soldering process can be used to couple the package substrate 102 to the board 108.

[0093] Stage 10, as shown in Figure 9D, illustrates a state after the optical integrated device 101 is coupled to the metallization portion 104 through a plurality of solder interconnections 310. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be similar to the optical integrated device 101. The optical integrated device 301 may be coupled to the board 108 through a plurality of solder interconnections. An optical fiber 110 may be coupled to the optical integrated device 101 and to the optical integrated device 301.

[0094] Stage 10 also illustrates a state after connector socket 107 is coupled to the metallization portion 104 through a plurality of solder interconnections 170 and connector socket 113 is coupled to the board 108 through a plurality of solder interconnections 114. A reflow soldering process can be used for connector socket 107 to the metallization portion 104 and connector socket 113 to the board 108. The socket of Petition 870250081854, dated 11 / 09 / 2025, pages 48 / 148 The 42 / 58 connector 107 can be coupled to the connector socket 113 via one or more wires. Illustrative Flow Diagram of a Method for Manufacturing a Package Comprising an Integrated Optical Device

[0095] In some implementations, the fabrication of a package includes several processes. Figure 10 illustrates an example flow diagram of a method 1000 for providing or fabricating a package. In some implementations, the method 1000 in Figure 10 can be used to provide or fabricate the packages in at least Figures 1 to 6.

[0096] It should be noted that method 1000 of Figure 10 can combine one or more processes in order to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified.

[0097] The method provides (in 1005) a metallization portion and a plurality of post-interconnects. The metallization portion can be provided on a carrier. In some implementations, providing the metallization portion and the plurality of post-interconnects includes fabricating the metallization portion and the plurality of post-interconnects. Stages 1 and 2 of Figure 9A illustrate and describe an example of providing a metallization portion 104 and a plurality of post-interconnects 160. Stage 1 of Figure 9A illustrates and describes an example of providing a metallization portion. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 can be formed on the carrier 900. A deposition, lamination, exposure, development and / or process Petition 870250081854, dated 11 / 09 / 2025, page 49 / 148 43 / 58 pickling can be used to form and pattern at least one dielectric layer. A plating process and / or a patterning process can be used to form the metallization interconnects.

[0098] Stage 2 of Figure 9A illustrates and describes an example of a plurality of post-interconnections 160 formed on, and coupled to, the metallization portion 104. The plurality of post-interconnections 160 is coupled to the plurality of metallization interconnections 142. A plating process can be used to form the plurality of post-interconnections 160.

[0099] The method couples (in 1010) a plurality of integrated devices and / or at least one passive device in the metallization portion. Stage 3 of Figure 9A illustrates and describes an example of a plurality of integrated devices and / or at least one passive device that are coupled to a surface of the metallizing portion 104. For example, integrated device 103 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 223. Integrated device 105 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 225. Integrated device 109 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 190. Passive device 111 is coupled to a surface of the metallizing portion 104 through a plurality of solder interconnections 112.One or more reflow soldering processes can be used to couple the plurality of integrated devices and / or passive devices to the portion. Petition 870250081854, dated 11 / 09 / 2025, p. 50 / 148 44 / 58 metallization 104.

[00100] The method forms (in 1015) an encapsulation layer. The encapsulation layer may at least partially encapsulate the plurality of post-interconnections, integrated devices and / or passive devices. Stage 4 of Figure 9B illustrates and describes an example of an encapsulation layer 106 that is formed on, and coupled to, the metallization portion 104. The encapsulation layer 106 may include a mold, a resin and / or an epoxy. A compression molding process, a transfer molding process, or a liquid injection molding process can be used to form the encapsulation layer 106. The encapsulation can encapsulate the integrated device 103 / rear-side power rail interconnection 203, the integrated device 105 / rear-side power rail interconnection 205, the integrated device 109, the passive device 111, and the plurality of post-interconnections 160.

[00101] The method can also remove (at 1015) a carrier that is coupled to the metallization portion. Stage 5 of Figure 9B illustrates and describes an example of a carrier 900 that is decoupled from the metallization portion 104.

[00102] The method can couple (in 1020) a package substrate to a plurality of post-interconnects via a plurality of solder interconnects. Stage 6 of Figure 9B illustrates and describes an example of a package substrate 102 that is coupled to the power rail interconnects (e.g., 203, 205) of integrated devices (e.g., 103, 105), the plurality of post-interconnects. 160 through a plurality of solder interconnections 123. Petition 870250081854, dated 11 / 09 / 2025, page 51 / 148 45 / 58 A reflow soldering process can be used to couple the power rail interconnects and the plurality of post-interconnects 160 through the plurality of solder interconnects 123. The package substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122.

[00103] In some implementations, the package substrate 102 may include an optical integrated device 101 and / or an optical integrated device 101 may be coupled to the package substrate 102. As shown and described in Figures 1 and 2, in some implementations, an optical integrated device 101 may be part of the package substrate 102. The optical integrated device 101 may be located in a cavity of the package substrate 102. The optical integrated device 101 may be coupled to the package substrate 102 via an adhesive.

[00104] In some implementations, since the package substrate 102 is coupled to the plurality of post-interconnects through a plurality of solder interconnects, an underfill 125 can be provided between the package substrate 102 and the encapsulation layer 106. Stage 7 of Figure 9B illustrates and describes an example of providing an underfill. The underfill 125 can be formed so that the underfill 125 laterally surrounds the plurality of solder interconnects 123. The underfill 125 can be coupled to, and touch, the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated device 103 and / or the integrated device 105.

[00105] The method can also couple (in 1020) integrated devices and / or passive devices to the package. For example, the method can couple the devices Petition 870250081854, dated 11 / 09 / 2025, page 52 / 148 46 / 58 integrated and / or passive devices to a surface of the metallization portion. Stage 8 of Figure 9C illustrates and describes an example of one or more integrated devices that are coupled to a surface of the metallization portion 104. For example, a stack of integrated devices can be coupled to the metallization portion 104. In one example, a stack of integrated devices comprising an integrated device 130, an integrated device 132, and an integrated device 134 can be coupled to the metallization portion 104 through a reflow soldering process.

[00106] The method can couple (in 1025) the package substrate to a board through a plurality of solder interconnects. Stage 9 of Figure 9C illustrates and describes an example of a package substrate 102 that is coupled to a board 108 through a plurality of solder interconnects 183. A reflow soldering process can be used to couple the package substrate 102 to the board 108 through a plurality of solder interconnects 183.

[00107] The method can couple (in 1030) connector sockets to the package and the board. The method can also couple (in 1030) an optical integrated device to a package and another optical integrated device to a board. Stage 10 of Figure 9D illustrates and describes an example of the optical integrated device 101 that is coupled to the metallization portion 104 through a plurality of solder interconnections 310. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be similar to the optical integrated device 101. The optical integrated device 301 can be coupled to the board 108 through a plurality of solder interconnections. A fiber Petition 870250081854, dated 11 / 09 / 2025, p. 53 / 148 47 / 58 optical 110 can be coupled to integrated optical device 101 and integrated optical device 301.

[00108] Stage 10 of Figure 9D also illustrates and describes an example of connector socket 107 being coupled to the metallization portion 104 through a plurality of solder interconnections 170, and connector socket 113 being coupled to the board 108 through a plurality of solder interconnections 114. A reflow soldering process can be used for connector socket 107 to the metallization portion 104 and connector socket 113 to the board. 108. Connector socket 107 can be coupled to connector socket 113 via one or more wires. Examples of Electronic Devices

[00109] Figure 11 illustrates various electronic devices that can be integrated into any of the previously mentioned devices: integrated device, integrated circuit (IC) package, integrated circuit device (IC), semiconductor device, integrated circuit, chip, interposer, package, package-on-package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or a motor vehicle 1110 may include a device 1100, as described in the present invention. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described in the present invention. Devices 1102, 1104, 1106 and 1108 and the vehicle The 1110 illustrated in Figure 11 are merely examples. Petition 870250081854, dated 11 / 09 / 2025, page 54 / 148 48 / 58 Other electronic devices may also feature the 1100 device, including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, signal decoders, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g.,autonomous vehicles) or any other device that stores or retrieves computer data or instructions, or any combination thereof.

[00110] One or more of the components, processes, attributes, and / or functions illustrated in Figures 1 to 8, 9A to 9D, and / or 10 and 11 may be rearranged and / or combined into a single component, process, attribute, or function, or incorporated into multiple components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the disclosure. It should also be noted that Figures 1 to 8, 9A to 9D, and / or 10 and 11 and their corresponding descriptions in this disclosure are not limited to chips and / or ICs. In some implementations, Petition 870250081854, dated 11 / 09 / 2025, p. 55 / 148 49 / 58 Figures 1 to 8, 9A to 9D and / or 10 and 11 and their corresponding descriptions can be used to manufacture, create, provide and / or produce devices and / or integrated devices. In some implementations, a device may include a wafer, an integrated device, an integrated passive device (IPD), a wafer package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device and / or an interposer.

[00111] It should be mentioned that the figures in the disclosure may be actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some cases, the figures may not be to scale. In some cases, for clarity, not all components and / or parts may be visible. In some cases, the position, location, sizes and / or shapes of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[00112] The word exemplifier is used in the present invention to mean serving as an example, an instance, or an illustration. Any implementations or aspects described in this invention as exemplifiers should not necessarily be interpreted as preferential or advantageous in relation to other aspects of the disclosure. Similarly, the term aspects does not require that all aspects of the disclosure include the attribute, Petition 870250081854, dated 11 / 09 / 2025, p. 56 / 148 50 / 58 the advantage or mode of operation discussed. The term coupled is used in the present invention to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to each other – even if they do not physically touch directly. The term electrically coupled can mean that two objects are directly or indirectly coupled to each other so that an electric current (e.g., signal, power, ground) can flow between the two objects. Two objects that are electrically coupled may or may not have an electric current flowing between them. The use of the terms first, second, third, and fourth (and / or any value above the fourth) is arbitrary.Any of the described components can be the first component, the second component, the third component, or the fourth component. For example, a component that is called a second component can be the first component, the second component, the third component, or the fourth component. The term encapsulation means that the object can partially encapsulate or completely encapsulate another object. A first component that is located within a second component can mean that the first component is partially located within the second component or completely located within the second component. A first component that is embedded within a second component can mean that the first component is partially embedded within the second component or completely embedded within the second component. The terms top and bottom are... Petition 870250081854, dated 11 / 09 / 2025, page 57 / 148 51 / 58 arbitrary. A component that is located on top can be located on top of a component that is located on a bottom. A top component can be considered a bottom component, and vice versa. As described in the disclosure, a first component being located on top of a second component can mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component can be located on (e.g., above) a first surface of the second component, and a third component can be located on (e.g., below) a second surface of the second component, where the second surface is opposite the first surface.It should be further mentioned that the term "on," as used in this application in the context of a component located on top of another component, may be used to mean a component that is on top of another component and / or within another component (e.g., on top of a component's surface or embedded in a component). Thus, for example, a first component that is on top of the second component may mean that (1) the first component is on top of the second component but not directly touching the second component, (2) the first component is on top of (e.g., on top of a surface of) the second component, and / or (3) the first component is within (e.g., embedded in) the second component. A value that is approximately X to XX may mean a value that is between X and XX, inclusive of X and XX. The value(s) between X and XX may be distinct or continuous. The term "approximately" refers to the 'value X' or... Petition 870250081854, dated 11 / 09 / 2025, page 58 / 148 52 / 58 approximately the value X, as used in the disclosure, means within 10 percent of 'value X'. For example, a value of approximately 1 or approximately 1 would mean a value in a range of 0.9 to 1.1. A plurality of components may include all possible components or only some of the components among all possible components. For example, if a device includes ten components, the use of the term plurality of components may refer to all ten components or only some of the components among the ten components.

[00113] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a redistribution metal layer, and / or an under-bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a current (e.g., a data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects.Different implementations may use similar or different processes to form the interconnections. In some implementations, a chemical vapor deposition (CVD) process and / or a process of... Petition 870250081854, dated 11 / 09 / 2025, page 59 / 148 53 / 58 Physical vapor deposition (PVD) to form the interconnects. For example, an ion bombardment process, a spray coating, and / or a plating or autocatalytic plating process can be used to form the interconnects.

[00114] Furthermore, it should be mentioned that several disclosures contained in the present invention can be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. A process is terminated when its operations are completed.

[00115] Additional examples are described below to facilitate understanding of the invention.

[00116] Aspect 1: A package comprising a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; a encapsulation layer that at least partially encapsulates the first integrated device; a plurality of post-interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post-interconnects; a second integrated device coupled to the metallization portion via a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

[00117] Aspect 2: The package of aspect 1, in which Petition 870250081854, dated 11 / 09 / 2025, page 60 / 148 54 / 58 One front side of the first integrated device is facing the package substrate.

[00118] Aspect 3: The package of aspects 1 and 2, wherein the second integrated device is configured to be electrically coupled to the optical integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post-interconnections and a solder interconnection of the first plurality of solder interconnections.

[00119] Aspect 4: The package of aspects 1 to 3, wherein the first integrated device is configured to be electrically coupled to the optical integrated device via an electrical path that includes a solder interconnection of the first plurality of solder interconnections.

[00120] Aspect 5: The package of aspects 1 to 4, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post-interconnections and a solder interconnection of the first plurality of solder interconnections, package substrate interconnections and another solder interconnection of the first plurality of solder interconnections.

[00121] Aspect 6: The package of aspects 1 to 5, in which the second integrated device is configured to be electrically coupled to the first integrated device. Petition 870250081854, dated 11 / 09 / 2025, page 61 / 148 55 / 58 through an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post-interconnections and a solder interconnection of the first plurality of solder interconnections, the integrated optical device and another solder interconnection of the first plurality of solder interconnections.

[00122] Aspect 7: The package of aspects 1 to 6, which additionally comprises a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

[00123] Aspect 8: The package of aspects 1 to 7, in which the integrated optical device includes a waveguide and a circuit for processing optical and / or electrical signals.

[00124] Aspect 9: The package of aspects 1 to 8, in which the optical fiber extends through the package substrate.

[00125] Aspect 10: The package of aspects 1 to 9, in which the second integrated device includes memory.

[00126] Aspect 11: A package comprising: a metallization portion; a first integrated device coupled to the metallization portion via a first plurality of solder interconnections, wherein one front side of the first integrated device faces the metallization portion; an encapsulation layer encapsulating the first integrated device; a plurality of post-interconnections located in the encapsulation layer; a second integrated device coupled to the metallization portion via a second plurality of Petition 870250081854, dated 11 / 09 / 2025, page 62 / 148 56 / 58 solder interconnections; an integrated optical device coupled to the metallization portion via a third plurality of solder interconnections; an optical fiber coupled to the integrated optical device; and a package substrate coupled to the plurality of post-interconnections via a fourth plurality of solder interconnections.

[00127] Aspect 12: The package of aspects 11, wherein the second integrated device is coupled to the optical integrated device via an electrical path which includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion and a solder interconnection of the third plurality of solder interconnections.

[00128] Aspect 13: The package of aspects 11 to 12, wherein the first integrated device is coupled to the optical integrated device via an electrical path which includes a solder interconnection of the first plurality of solder interconnections, metallization interconnections of the metallization portion and a solder interconnection of the third plurality of solder interconnections.

[00129] Aspect 14: The package of aspects 11 to 13, wherein the second integrated device is coupled to the first integrated device via an electrical path which includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion and a solder interconnection of the first plurality of solder interconnections.

[00130] Aspect 15: The package of aspects 11 to 14, which additionally comprises a passive device coupled to the metallization portion. Petition 870250081854, dated 11 / 09 / 2025, page 63 / 148 57 / 58

[00131] Aspect 16: The package of aspect 15, in which the passive device is at least partially encapsulated by the encapsulation layer.

[00132] Aspect 17: The package of aspects 11 to 16, which additionally comprises a plurality of power rail interconnections located in the encapsulation layer.

[00133] Aspect 18: The package of aspect 17, in which the plurality of power rail interconnections is located between a rear side of the first integrated device and the package substrate.

[00134] Aspect 19: The package of aspects 11 to 18, in which the second integrated device includes memory.

[00135] Aspect 20: The package of aspects 11 to 19, which further comprises a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

[00136] Aspect 21: The package of aspects 11 to 20, wherein the package is implemented in a device that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[00137] Aspect 22: The package of aspects 1 to 10, where the package is implemented on a device that is Petition 870250081854, dated 11 / 09 / 2025, page 64 / 148 58 / 58 selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[00138] The various attributes of the disclosure described in the present invention can be implemented in different systems without departing from the scope of the disclosure. It should be mentioned that the previously mentioned aspects of the disclosure are merely examples and should not be interpreted as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not to limit the scope of the aspects. Thus, the present teachings can be readily applied to other types of apparatus, and many alternatives, modifications, and variations will be evident to those skilled in the art. Petition 870250081854, dated 11 / 09 / 2025, page 65 / 148

Claims

1 / 5 CLAIMS 1. Package characterized by comprising: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of post-interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post-interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

2. Package, according to claim 1, characterized in that the front side of the first integrated device is directed in one direction, towards the package substrate.

3. Package, according to claim 1, characterized in that the second integrated device is configured to be electrically coupled to the optical integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post interconnections and a solder interconnection of the first plurality of solder interconnections.

4. Package, according to claim 1, characterized in that the first integrated device is configured to be electrically coupled to the optical integrated device via an electrical path that includes a solder interconnection of the first plurality of solder interconnections.

5. Package, according to claim 1, characterized in that the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post-interconnections and a solder interconnection of the first plurality of solder interconnections, package substrate interconnections and another solder interconnection of the first plurality of solder interconnections.

6. Package, according to claim 1, characterized in that the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion, a post-interconnection of the plurality of post-interconnections and a solder interconnection of the first plurality of solder interconnections, the optical integrated device and another solder interconnection of the first plurality of solder interconnections. Petition 870250081854, dated 11 / 09 / 2025, pp. 126 / 148 3 / 5 7. Package, according to claim 1, characterized by further comprising a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

8. Package, according to claim 1, characterized in that the integrated optical device includes a waveguide and a circuit for processing optical and / or electrical signals.

9. Package according to claim 1, characterized in that the optical fiber extends through the package substrate.

10. Package according to claim 1, characterized in that the second integrated device includes memory.

11. Package characterized by comprising: a metallization portion; a first integrated device coupled to the metallization portion through a first plurality of solder interconnections, wherein a front side of the first integrated device is facing towards the metallization portion; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of post-interconnections located in the encapsulation layer; a second integrated device coupled to the metallization portion through a second plurality of solder interconnections; an optical integrated device coupled to the metallization portion through a third plurality of solder interconnections; an optical fiber coupled to the optical integrated device; and a package substrate coupled to the plurality of post-interconnections through a fourth plurality of solder interconnections.

12. Package, according to claim 11, characterized in that the second integrated device is coupled to the optical integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion and a solder interconnection of the third plurality of solder interconnections.

13. Package, according to claim 11, characterized in that the first integrated device is coupled to the optical integrated device via an electrical path that includes a solder interconnection of the first plurality of solder interconnections, metallization interconnections of the metallization portion, and a solder interconnection of the third plurality of solder interconnections.

14. Package, according to claim 11, characterized in that the second integrated device is coupled to the first integrated device via an electrical path that includes a solder interconnection of the second plurality of solder interconnections, metallization interconnections of the metallization portion and a solder interconnection of the first plurality of solder interconnections.

15. Package, according to claim 11, characterized by further comprising a passive device attached to the metallization portion.

16. Package according to claim 15, characterized in that the passive device is at least partially encapsulated by the encapsulation layer.

17. Package according to claim 11, characterized by further comprising a plurality of power rail interconnections located in the encapsulation layer.

18. Package, according to claim 17, characterized in that the plurality of power rail interconnections are located between a rear side of the first integrated device and the package substrate.

19. Package, according to claim 11, characterized in that the second integrated device includes memory.

20. Package, according to claim 11, characterized by further comprising a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power. Petition 870250081854, dated 11 / 09 / 2025, pp. 129 / 148

Images