PACKAGE, AND, DEVICE

Abstract

A package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially in the substrate. The first integrated device is coupled to the first plurality of interconnects through a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects through a second plurality of solder interconnects.

Description

1 / 71 “PACKAGE, AND, DEVICE CROSS-REFERENCE TO RELATED REQUESTS

[0001] This application claims priority and benefit of non-provisional application U.S. Serial No. 18 / 190,019, filed with the United States Patent and Trademark Office on March 24, 2023, the entire content of which is incorporated herein by reference, as if fully set forth below in its entirety and for all applicable purposes. Field

[0002] Several attributes refer to a package that includes a substrate. Background

[0003] A package can include a substrate and integrated devices. These components are coupled together to provide a package that can perform various functions. The performance of a package and its components can depend on many factors. There is a continuous need to provide packages that offer improved performance. In addition, there is a continuous need to include a package that includes a more compact form factor so that the package can be deployed in smaller devices. SUMMARY

[0004] Several attributes refer to a package that includes a substrate.

[0005] An example provides a package that includes a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device. Petition 870250081895, dated 11 / 09 / 2025, page 8 / 179 2 / 71 located at least partially on the substrate. The first integrated device is coupled to the first plurality of interconnections via a first plurality of soldered interconnections. The second integrated device is coupled to the first plurality of interconnections via a second plurality of soldered interconnections.

[0006] Another example provides a device comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially on the substrate. The first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects via a second plurality of solder interconnects.

[0007] Another example provides a method for fabricating a substrate, wherein the fabrication of the substrate comprises coupling a first integrated device to a first plurality of carrier interconnects, through a first plurality of solder interconnects; forming a first dielectric layer on the carrier and the first integrated device, wherein the first dielectric layer encapsulates the first integrated device, the first plurality of solder interconnects and the first plurality of interconnects; forming a second dielectric layer on a surface of the first dielectric layer; forming a first plurality of cavities in the second dielectric layer and in the first dielectric layer; Petition 870250081895, dated 11 / 09 / 2025, page 9 / 179 3 / 71 form a second plurality of interconnections at least in the first plurality of cavities; form a third dielectric layer over the second dielectric layer; form a second plurality of cavities in the third dielectric layer; and form a third plurality of interconnections at least in the second plurality of cavities.

[0008] Another example provides a method for fabricating a substrate, wherein the fabrication of the substrate comprises coupling a first integrated device to a first plurality of carrier interconnects, through a first plurality of solder interconnects; forming a first underfill between the first integrated device and the carrier, wherein the first underfill laterally encircles the first plurality of solder interconnects; forming a first dielectric layer on the carrier; forming a second dielectric layer on the first integrated device and a surface of the first dielectric layer; forming a first plurality of cavities in the second dielectric layer and in the first dielectric layer; forming a second plurality of interconnects at least in the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities in the third dielectric layer;and to form a third plurality of interconnections, at least in the second plurality of cavities. BRIEF DESCRIPTION OF THE DRAWINGS Petition 870250081895, dated 11 / 09 / 2025, page 10 / 179 4 / 71

[0009] Several attributes, nature and advantages may become evident from the detailed description set forth below when taken together with the drawings in which related reference characters correspondingly identify equivalent items throughout the description.

[0010] Figure 1 illustrates a cross-sectional profile view of an exemplary package that includes a substrate with an embedded integrated device.

[0011] Figure 2 illustrates a cross-sectional profile view of an exemplary package that includes a substrate with an embedded integrated device.

[0012] Figure 3 illustrates a cross-sectional profile view of an exemplary package that includes a substrate with an embedded integrated device.

[0013] Figure 4 illustrates a cross-sectional profile view of an exemplary package that includes a substrate with an embedded integrated device.

[0014] Figure 5 illustrates a cross-sectional profile view of an exemplary deep trench capacitor device.

[0015] Figures 6A to 6C illustrate an exemplary sequence for manufacturing a package that includes a substrate with an embedded integrated device.

[0016] Figure 7 illustrates an example flowchart of a method for manufacturing a package that includes a substrate with an embedded integrated device.

[0017] Figures 8A to 8E illustrate an example sequence for manufacturing a package that includes Petition 870250081895, dated 11 / 09 / 2025, page 11 / 179 5 / 71 a substrate with an integrated device embedded.

[0018] Figure 9 illustrates an example flowchart of a method for manufacturing a package that includes a substrate with an embedded integrated device.

[0019] Figure 10 illustrates various electronic devices that can integrate a chip, an integrated device, an integrated passive device (IPD), a passive component, a package and / or a device package described in the present invention. DETAILED DESCRIPTION

[0020] The following description gives specific details that provide a complete understanding of the various aspects of this disclosure. However, it will be understood by those skilled in the art that the aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring the aspects with unnecessary details. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the disclosure.

[0021] This disclosure describes a package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially on the substrate. The first integrated device is coupled to the first plurality of interconnects via a first plurality of soldered interconnects. The second Petition 870250081895, dated 11 / 09 / 2025, page 12 / 179 The integrated device (6 / 71) is coupled to the first plurality of interconnects via a second plurality of soldered interconnects. Embedding the integrated device in the substrate allows it to be located close to the second integrated device, reducing the distance an electrical signal has to travel between the first and second integrated devices. Thus, placing the first integrated device near the second integrated device, and vice versa, can help improve the performance of both the second integrated device and the package. Example Package Comprising a Substrate with an Integrated Embedded Device

[0022] Figure 1 illustrates a package 100 that includes a substrate with an embedded integrated device. Package 100 includes a substrate 102, an integrated device 103, and an integrated device 105. In some implementations, the integrated device 103 may be configured as a deep trench capacitor device. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the integrated device 103 may be replaced by a bridge that includes a plurality of bridge interconnects.

[0023] Substrate 102 may be a package substrate. Substrate 102 includes a dielectric layer 104, a dielectric layer 106, a dielectric layer 108, a plurality of interconnects 121, a solder-resistant layer 122, a solder-resistant layer 124, and a plurality of solder interconnects 120. The plurality of interconnects 121 may include a plurality of Petition 870250081895, dated 11 / 09 / 2025, page 13 / 179 7 / 71 interconnections 142, a plurality of interconnections 162, and a plurality of interconnections 182. The dielectric layer 104, the dielectric layer 106, and / or the dielectric layer 108 may include the same material or different materials. For example, the dielectric layer 104, the dielectric layer 106, and / or the dielectric layer 108 may include pre-impregnation, Ajinomoto Build-Up Film (ABF), and / or an underfill. In one example, the dielectric layer 108 may include ABF (or resin without glass reinforcement), the dielectric layer 106 may include ABF or pre-impregnation, and the dielectric layer 104 may include pre-impregnation.

[0024] Dielectric layer 106 is located between dielectric layer 108 and dielectric layer 104. Dielectric layer 104 is coupled to dielectric layer 106. Dielectric layer 108 is coupled to dielectric layer 106. The plurality of interconnections 142 may be located at least in dielectric layer 104. The plurality of interconnections 162 may be located at least in dielectric layer 106 and dielectric layer 108. In some implementations, the plurality of interconnections 162 may extend through at least part of dielectric layer 106 and at least part of dielectric layer 108. For example, the plurality of interconnections 162 may include vias (e.g., via-type interconnects) that extend through at least part of dielectric layer 106 and at least part of dielectric layer 108. A The plurality of interconnections 182 may be located at least in the dielectric layer 108.The plurality of interconnections 182 is coupled to the plurality of interconnections 162. The plurality of interconnections 162 is coupled to the plurality of interconnections. Petition 870250081895, dated 11 / 09 / 2025, page 14 / 179 8 / 71 142. The plurality of solder interconnections 120 is coupled to the substrate 102. For example, the plurality of solder interconnections 120 is coupled to the plurality of interconnections 142. The solder-resistant layer 122 can be coupled to the dielectric layer 108. The solder-resistant layer 124 can be coupled to the dielectric layer 104.

[0025] The integrated device 103 is located at least partially within the substrate 102. The integrated device 103 is surrounded by the dielectric layer 108. The dielectric layer 108 may touch a front side of the integrated device 103, a rear side of the integrated device, and / or a side surface of the integrated device 103. The integrated device 103 may include a plurality of pillar interconnections 132. The plurality of solder interconnections 130 may be coupled to the plurality of pillar interconnections 132. A plurality of interconnections 184 may be coupled to the plurality of solder interconnections 130. The plurality of interconnections 184 may be considered part of the plurality of interconnections 182 and / or the plurality of interconnections 121. The plurality of pillar interconnections 132, the plurality of solder interconnections 130 and the plurality of interconnections 184 may be located in the dielectric layer 108.Thus, the integrated device 103, the plurality of pillar interconnections 132, the plurality of weld interconnections 130 and the plurality of interconnections 184 can be incorporated into the substrate 102.

[0026] The integrated device 105 is coupled to the substrate 102 through a plurality of solder interconnections 150. The integrated device 105 may include a Petition 870250081895, dated 11 / 09 / 2025, page 15 / 179 9 / 71 Pillar Interconnection Plurality 152. Weld Interconnection Plurality 150 can be coupled to Pillar Interconnection Plurality 152 and Interconnection Plurality 184. Weld Interconnection Plurality 150 can be located between Pillar Interconnection Plurality 152 and Interconnection Plurality 184. Weld Interconnection Plurality 130 can be located between Pillar Interconnection Plurality 132 and Interconnection Plurality 184. An underfill 110 can be located between the integrated device 105 and the substrate 102. The underfill 110 can laterally encircle Pillar Interconnection Plurality 152 and Weld Interconnection Plurality 150.

[0027] One front side of the integrated device 105 may face the substrate 102. The front side of the integrated device 105 may face the integrated device 103. One front side of the integrated device 103 may face the integrated device 105.

[0028] In some implementations, an electrical path 170 between integrated device 105 and integrated device 103 may include at least one pillar interconnection of the plurality of pillar interconnections 152, at least one solder interconnection of the plurality of solder interconnections 150, at least one interconnection of the plurality of interconnections 184, at least one solder interconnection of the plurality of solder interconnections 130, and at least one pillar interconnection of the plurality of pillar interconnections 132. The electrical path 170 may be configured to provide a path Petition 870250081895, dated 11 / 09 / 2025, page 16 / 179 10 / 71 electrical path for power. The 170 electrical path can be configured to provide an electrical path for signals.

[0029] Package 100 can be coupled to a board (not shown), such as a printed circuit board, via a plurality of solder interconnects 120. In some implementations, an electrical path 190 between the integrated device 105 and a board (not shown) may include at least one pillar interconnect of a plurality of pillar interconnects 152, at least one solder interconnect of a plurality of solder interconnects 150, at least one plurality of interconnects 182, at least one plurality of interconnects 162, at least one plurality of interconnects 142, and at least one solder interconnect of a plurality of solder interconnects 120. The electrical path 190 can be configured to provide an electrical path for power. The electrical path 190 can be configured to provide an electrical path for signals.

[0030] The structure and / or configuration shown in Figure 1 allows the integrated device 103 to be placed and / or located close to the integrated device 105, shortening the distance that a current has to travel between the integrated device 103 and the integrated device 105, which can lead to an overall improvement in the performance of the integrated device 103, the integrated device 105 and / or the package 100.

[0031] Figure 2 illustrates a package 200 that includes a substrate with an embedded integrated device. Package 200 includes a substrate 202, an integrated device 103, and an integrated device 105. In Petition 870250081895, dated 11 / 09 / 2025, page 17 / 179 11 / 71 In some implementations, the integrated device 103 can be configured as a deep trench capacitor device. In some implementations, the integrated device 103 can be configured as a bridge. In some implementations, the integrated device 103 can be replaced by a bridge that includes a plurality of bridge interconnects.

[0032] Substrate 202 may be a package substrate. Substrate 202 includes a dielectric layer 204, a dielectric layer 206, a dielectric layer 208, an underfill 210, a plurality of interconnects 221, a solder-resistant layer 122, a solder-resistant layer 124, and a plurality of solder interconnects 120. The plurality of interconnects 221 may include a plurality of interconnects 242, a plurality of interconnects 262, and a plurality of interconnects 282. The dielectric layer 204, the dielectric layer 206, and / or the dielectric layer 208 may include the same material or different materials. For example, dielectric layer 204, dielectric layer 206, and / or dielectric layer 208 may include pre-impregnation, Ajinomoto Build-Up Film (ABF), and / or an underfill.In one example, dielectric layer 208 may include ABF or pre-impregnation, dielectric layer 206 may include ABF (or non-glass-reinforced resin), and dielectric layer 204 may include pre-impregnation.

[0033] Dielectric layer 206 is located between dielectric layer 208 and dielectric layer 204. Dielectric layer 204 is coupled to dielectric layer 206. Dielectric layer 208 is coupled to dielectric layer 206. The plurality of interconnections 242 may be located by Petition 870250081895, dated 11 / 09 / 2025, page 18 / 179 12 / 71 less in dielectric layer 204. The plurality of interconnections 262 may be located at least in dielectric layer 206 and dielectric layer 208. In some implementations, the plurality of interconnections 262 may extend through at least part of dielectric layer 206 and at least part of dielectric layer 208. For example, the plurality of interconnections 262 may include vias (e.g., via-type interconnections) that extend through at least part of dielectric layer 206 and at least part of dielectric layer 208. The plurality of interconnections 282 may be located at least in dielectric layer 208. The plurality of interconnections 282 is coupled to the plurality of interconnections 262. The plurality of interconnections 262 is coupled to the plurality of interconnections 242. The plurality of Solder interconnection 120 is coupled to substrate 202. For example, a plurality of solder interconnections 120 is coupled to a plurality of interconnections 242.Weld-resistant layer 122 can be coupled to dielectric layer 208. Weld-resistant layer 124 can be coupled to dielectric layer 204.

[0034] The integrated device 103 is located at least partially within the substrate 202. The integrated device 103 is surrounded by the dielectric layer 206. The dielectric layer 206 may touch a rear side of the integrated device and / or a side surface of the integrated device 103. The underfill 210 may touch a front side of the integrated device 103. The integrated device 103 may include a plurality of pillar interconnections 132. The plurality of solder interconnections 130 may be coupled to the plurality of interconnections. Petition 870250081895, dated 11 / 09 / 2025, page 19 / 179 13 / 71 of pillar 132. A plurality of interconnections 284 can be coupled to the plurality of solder interconnections 130. The plurality of interconnections 284 can be considered part of the plurality of interconnections 282 and / or the plurality of interconnections 121. The plurality of pillar interconnections 132, the plurality of solder interconnections 130, and the plurality of interconnections 284 can be located in the underfill 210. Thus, the integrated device 103, the plurality of pillar interconnections 132, the plurality of solder interconnections 130, and the plurality of interconnections 284 can be incorporated into the substrate 202.

[0035] The integrated device 105 is coupled to the substrate 202 through a plurality of solder interconnections 150. The integrated device 105 may include a plurality of pillar interconnections 152. The plurality of solder interconnections 150 may be coupled to the plurality of pillar interconnections 152 and the plurality of interconnections 284. The plurality of solder interconnections 150 may be located between the plurality of pillar interconnections 152 and the plurality of interconnections 284. The plurality of solder interconnections 130 may be located between the plurality of pillar interconnections 132 and the plurality of interconnections 284. An underfill 110 may be located between the integrated device 105 and the substrate 202. The underfill 110 may laterally encircle the plurality of pillar interconnections 152 and the plurality of weld interconnections 150. The underfill 110 can be coupled to and touch the underfill 210 of the substrate 202.

[0036] One front side of the integrated device 105 may be facing the substrate 202. The front side Petition 870250081895, dated 11 / 09 / 2025, page 20 / 179 14 / 71 of integrated device 105 may be facing integrated device 103. One front side of integrated device 103 may be facing integrated device 105.

[0037] In some implementations, an electrical path 270 between integrated device 105 and integrated device 103 may include at least one pillar interconnection of the plurality of pillar interconnections 152, at least one solder interconnection of the plurality of solder interconnections 150, at least one interconnection of the plurality of interconnections 284, at least one solder interconnection of the plurality of solder interconnections 130, and at least one pillar interconnection of the plurality of pillar interconnections 132. The electrical path 270 may be configured to provide an electrical path for power. The electrical path 270 may be configured to provide an electrical path for signals.

[0038] Package 200 can be coupled to a board (not shown), such as a printed circuit board, via a plurality of solder interconnects 120. In some implementations, an electrical path 290 between the integrated device 105 and a board (not shown) may include at least one pillar interconnect of a plurality of pillar interconnects 152, at least one solder interconnect of a plurality of solder interconnects 150, at least one plurality of interconnects 282, at least one plurality of interconnects 262, at least one plurality of interconnects 242, and at least one solder interconnect of a plurality of solder interconnects 120. The path Petition 870250081895, dated 11 / 09 / 2025, page 21 / 179 The 15 / 71 electrical path 290 can be configured to provide an electrical path for power. The electrical path 290 can also be configured to provide an electrical path for signals.

[0039] The structure and / or configuration shown in Figure 2 allows the integrated device 103 to be placed and / or located close to the integrated device 105, shortening the distance that a current has to travel between the integrated device 103 and the integrated device 105, which can lead to an overall improvement in the performance of the integrated device 103, the integrated device 105 and / or the package 100.

[0040] In some implementations, more than one integrated device can be coupled to a substrate and / or more than one integrated device can be embedded in the substrate (e.g., 102, 202). Figures 3 and 4 illustrate examples of multiple integrated devices coupled to a substrate in a package.

[0041] Figure 3 illustrates a 300 package that includes a substrate with an embedded integrated device. The 300 package includes a substrate 102, an integrated device 103, an integrated device 105, and an integrated device 305. In some implementations, the integrated device 103 may be configured as a deep trench capacitor device. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the integrated device 103 may be replaced by a bridge that includes a plurality of bridge interconnects. The 300 package is similar to the 100 package in Figure 1. However, the 300 package illustrates two coupled integrated devices. Petition 870250081895, dated 11 / 09 / 2025, page 22 / 179 16 / 71 to substrate 102. Integrated device 105 is coupled to substrate 102 and integrated device 305 is coupled to substrate 102. The plurality of pillar interconnections 184 includes a plurality of interconnections 184a and a plurality of interconnections 184b. The plurality of pillar interconnections 132 includes a plurality of pillar interconnections 132a and a plurality of pillar interconnections 132b. The plurality of solder interconnections 130 includes a plurality of solder interconnections 130a and a plurality of solder interconnections 130b.

[0042] The integrated device 105 is coupled to the substrate 102 through a plurality of solder interconnections 150. The integrated device 105 may include a plurality of pillar interconnections 152. The plurality of solder interconnections 150 may be coupled to the plurality of pillar interconnections 152 and the plurality of interconnections 184a. The plurality of solder interconnections 150 may be located between the plurality of pillar interconnections 152 and the plurality of interconnections 184a. The plurality of solder interconnections 130a may be located between the plurality of pillar interconnections 132a and the plurality of interconnections 184a. An underfill 110 may be located between the integrated device 105 and the substrate 102. The underfill 110 may laterally encircle the plurality of pillar interconnections 152 and the plurality of solder interconnections 150.

[0043] One front side of the integrated device 105 may face the substrate 102. The front side of the integrated device 105 may face the integrated device 103. One front side of the device Petition 870250081895, dated 11 / 09 / 2025, page 23 / 179 17 / 71 integrated 103 may be facing the integrated device 105.

[0044] The integrated device 305 is coupled to the substrate 102 through a plurality of solder interconnections 350. The integrated device 305 may include a plurality of pillar interconnections 352. The plurality of solder interconnections 350 may be coupled to the plurality of pillar interconnections 352 and the plurality of interconnections 184b. The plurality of solder interconnections 350 may be located between the plurality of pillar interconnections 352 and the plurality of interconnections 184b. The plurality of solder interconnections 130b may be located between the plurality of pillar interconnections 132b and the plurality of interconnections 184b. An underfill 110 may be located between the integrated device 305 and the substrate 102. The underfill 110 may laterally encircle the plurality of pillar interconnections 352 and the plurality of solder interconnections 350.

[0045] One front side of integrated device 305 may face substrate 102. The front side of integrated device 305 may face integrated device 103. One front side of integrated device 103 may face integrated device 305.

[0046] In some implementations, an electrical path between integrated device 105 and integrated device 103 may include at least one pillar interconnection of the plurality of pillar interconnections 152, at least one solder interconnection of the plurality of solder interconnections 150, at least one interconnection of Petition 870250081895, dated 11 / 09 / 2025, page 24 / 179 18 / 71 plurality of interconnections 184a, at least one weld interconnection of the plurality of weld interconnections 130a and at least one pillar interconnection of the plurality of pillar interconnections 132a.

[0047] In some implementations, an electrical path between integrated device 305 and integrated device 103 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one interconnection of the plurality of interconnections 184b, at least one solder interconnection of the plurality of solder interconnections 130b, and at least one pillar interconnection of the plurality of pillar interconnections 132b.

[0048] In some implementations, an electrical path 370 between integrated device 305 and integrated device 105 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one plurality of interconnections 184b, at least one solder interconnection of the plurality of solder interconnections 130b, at least one pillar interconnection of the plurality of pillar interconnections 132b, integrated device 103, at least one pillar interconnection of the plurality of pillar interconnections 132a, at least one solder interconnection of the plurality of solder interconnections 130a, at least one plurality of interconnections 184a, at least one solder interconnection of the plurality of solder interconnections 150 and at least one pillar interconnection of plurality of Petition 870250081895, dated 11 / 09 / 2025, page 25 / 179 19 / 71 pillar interconnections 152. The electrical path 370 can be configured to provide an electrical path for signals (e.g., input / output signals) between the integrated device 305 and the integrated device 105.

[0049] In some implementations, an electrical path between integrated device 305 and integrated device 105 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one interconnection of the plurality of interconnections 184, at least one solder interconnection of the plurality of solder interconnections 150, and at least one pillar interconnection of the plurality of pillar interconnections 152. Thus, a current and / or signal between integrated device 305 and integrated device 105 may bypass integrated device 103.

[0050] Figure 4 illustrates a 400 package that includes a substrate with an embedded integrated device. The 400 package includes a substrate 202, an integrated device 103, an integrated device 105, and an integrated device 305. In some implementations, the integrated device 103 may be configured as a deep trench capacitor device. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the integrated device 103 may be replaced by a bridge that includes a plurality of bridge interconnects. The bridge may include a wafer substrate. The plurality of bridge interconnects may be formed over a surface. Petition 870250081895, dated 11 / 09 / 2025, page 26 / 179 20 / 71 of the wafer substrate. Package 400 is similar to package 200 in Figure 2. However, package 400 illustrates two integrated devices coupled to substrate 202. Integrated device 105 is coupled to substrate 202 and integrated device 305 is coupled to substrate 202. The plurality of pillar interconnects 284 includes a plurality of interconnects 284a and a plurality of interconnects 284b. The plurality of pillar interconnects 132 includes a plurality of pillar interconnects 132a and a plurality of pillar interconnects 132b. The plurality of solder interconnects 130 includes a plurality of solder interconnects 130a and a plurality of solder interconnects 130b.

[0051] The integrated device 105 is coupled to the substrate 202 through a plurality of solder interconnections 150. The integrated device 105 may include a plurality of pillar interconnections 152. The plurality of solder interconnections 150 may be coupled to the plurality of pillar interconnections 152 and the plurality of interconnections 284. The plurality of solder interconnections 150 may be located between the plurality of pillar interconnections 152 and the plurality of interconnections 284. The plurality of solder interconnections 130 may be located between the plurality of pillar interconnections 132 and the plurality of interconnections 284. An underfill 110 may be located between the integrated device 105 and the substrate 202. The underfill 110 may laterally encircle the plurality of pillar interconnections 152 and the plurality of weld interconnections 150.

[0052] A front side of the integrated device Petition 870250081895, dated 11 / 09 / 2025, page 27 / 179 21 / 71 105 may be facing substrate 202. The front side of integrated device 105 may be facing integrated device 103. A front side of integrated device 103 may be facing integrated device 105.

[0053] The integrated device 305 is coupled to the substrate 202 through a plurality of solder interconnections 350. The integrated device 305 may include a plurality of pillar interconnections 352. The plurality of solder interconnections 350 may be coupled to the plurality of pillar interconnections 352 and the plurality of interconnections 284. The plurality of solder interconnections 350 may be located between the plurality of pillar interconnections 352 and the plurality of interconnections 284. The plurality of solder interconnections 130 may be located between the plurality of pillar interconnections 132 and the plurality of interconnections 284. An underfill 110 may be located between the integrated device 305 and the substrate 202. The underfill 110 may laterally encircle the plurality of pillar interconnections 352 and the plurality of weld interconnections 350.

[0054] One front side of integrated device 305 may face substrate 202. The front side of integrated device 305 may face integrated device 103. One front side of integrated device 103 may face integrated device 305.

[0055] In some implementations, an electrical path between integrated device 105 and integrated device 103 may include at least one interconnection of Petition 870250081895, dated 11 / 09 / 2025, page 28 / 179 22 / 71 pillar of the plurality of pillar interconnections 152, at least one weld interconnection of the plurality of weld interconnections 150, at least one interconnection of the plurality of interconnections 284, at least one weld interconnection of the plurality of weld interconnections 130 and at least one pillar interconnection of the plurality of pillar interconnections 132.

[0056] In some implementations, an electrical path between integrated device 305 and integrated device 103 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one interconnection of the plurality of interconnections 284, at least one solder interconnection of the plurality of solder interconnections 130, and at least one pillar interconnection of the plurality of pillar interconnections 132.

[0057] In some implementations, an electrical path 470 between integrated device 305 and integrated device 105 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one plurality of interconnections 284b, at least one solder interconnection of the plurality of solder interconnections 130b, at least one pillar interconnection of the plurality of pillar interconnections 132b, integrated device 103, at least one pillar interconnection of the plurality of pillar interconnections 132a, at least one solder interconnection of the plurality of solder interconnections 130a, at least one interconnection of the Petition 870250081895, dated 11 / 09 / 2025, page 29 / 179 23 / 71 plurality of interconnections 284a, at least one solder interconnection of the plurality of solder interconnections 150 and at least one pillar interconnection of the plurality of pillar interconnections 152. The electrical path 470 can be configured to provide an electrical path for signals (e.g., input / output signals) between the integrated device 305 and the integrated device 105.

[0058] In some implementations, an electrical path between integrated device 305 and integrated device 105 may include at least one pillar interconnection of the plurality of pillar interconnections 352, at least one solder interconnection of the plurality of solder interconnections 350, at least one interconnection of the plurality of interconnections 284, at least one solder interconnection of the plurality of solder interconnections 150, and at least one pillar interconnection of the plurality of pillar interconnections 152. Thus, a current and / or signal between integrated device 305 and integrated device 105 may bypass integrated device 103.

[0059] In some implementations, integrated device 103, integrated device 105, and / or integrated device 305 may be chiplets. For example, in some implementations, integrated device 103 may be a first chiplet, integrated device 105 may be a second chiplet, and integrated device 305 may be a third chiplet. In some implementations, one or more of the integrated devices described in the disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, a chiplet (by Petition 870250081895, dated 11 / 09 / 2025, page 30 / 179 24 / 71 example, 105) can be manufactured using a first technology node, and another chiplet (e.g., 305) can be manufactured using a second technology node that is not as advanced as the first technology node. In such an example, one chiplet (e.g., 105) may include components (e.g., interconnects, transistors) that have a first minimum size, and the other chiplet (e.g., 305) may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, integrated device 105 and integrated device 305 of a package may be manufactured using the same technology node or different technology nodes. In some implementations, one chiplet (e.g., 103) and another chiplet (e.g., 105, 305) of a package may be manufactured using the same technology node or different technology nodes.

[0060] As another example, in some implementations, integrated device 105 may be a first chiplet and integrated device 305 may be a second chiplet. Integrated device 105 may be configured to perform a first plurality of functions and / or operations. Integrated device 305 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations. In some implementations, integrated device 105 may be manufactured using a first technology node, and integrated device 305 may be manufactured using a Petition 870250081895, dated 11 / 09 / 2025, page 31 / 179 25 / 71 second technology node that is not as advanced as the first technology node. In some implementations, the integrated device 103 may be manufactured using a third technology node that is different from the first technology node and / or the second technology node.

[0061] As mentioned above, in some implementations, integrated device 103 can be configured as a deep trench capacitor. Figure 5 illustrates a cross-sectional profile view of an integrated device 500 that is configured as a trench capacitor device. Integrated device 500 can be a passive integrated device that includes multiple trench capacitors (e.g., deep trench capacitors). Integrated device 500 can be a means for trench capacitance. Integrated device 500 can represent integrated device 103. Integrated device 500 includes a front side and a back side. The front side of integrated device 500 can include the plurality of trench capacitors.

[0062] The integrated device 500 includes a wafer substrate 502 and a plurality of trench capacitors 505. A plurality of solder interconnects (not shown) may be coupled to the integrated device 500. The wafer substrate 502 may include silicon (Si). The wafer substrate 502 may include a plurality of trenches and / or cavities over which capacitors may be formed.

[0063] The 505 trench capacitor plurality includes a 505a trench capacitor and a Petition 870250081895, dated 11 / 09 / 2025, p. 32 / 179 26 / 71 Trench capacitor 505b. The 505a trench capacitor and the 505b trench capacitor can be configured to be part of the same capacitor (e.g., the first capacitor, first trench capacitor). The 505a trench capacitor and the 505b trench capacitor can be configured to be coupled to and / or be part of a first power distribution network (PDN). The 505a trench capacitor and the 505b trench capacitor can be configured to be part of a first electrical path for first power to a packet. The 505a trench capacitor and the 505b trench capacitor can be configured to be coupled to integrated device(s).

[0064] As shown in Figure 5, the integrated device 500 includes the wafer substrate 502, an oxide layer 504, a first electrically conductive layer 506, a dielectric layer 508, and a second electrically conductive layer 510. The first electrically conductive layer 506 and / or the second electrically conductive layer 510 may include polysilicon. The oxide layer 504 and / or the dielectric layer 508 may include SiO2 (e.g., low-pressure chemical vapor deposition (LPCVD) SiO2) or Si3N4 (e.g., LPCVD Si3N4). Portions of the oxide layer 504, the first electrically conductive layer 506, the dielectric layer 508, and the second electrically conductive layer 510 may be located in trenches and / or cavities of the pellet substrate 502. Note that a pellet substrate 502 may be considered as having a trench or a cavity, even if the trench or cavity is filled with a Petition 870250081895, dated 11 / 09 / 2025, p. 33 / 179 27 / 71 or more materials.

[0065] The trench capacitor 505a (e.g., first trench capacitor, first capacitor, means for first trench capacitance) can be defined by (i) a first portion of the oxide layer 504, (ii) a first portion of the first electrically conductive layer 506, (iii) a first portion of the dielectric layer 508 and (iv) a first portion of the second electrically conductive layer 510 that are located in a trench (e.g., first trench) of the wafer substrate 502.

[0066] The trench capacitor 505b (e.g., the second trench capacitor, second capacitor, means for the second trench capacitance) can be defined by (i) a second portion of the oxide layer 504, (ii) a second portion of the first electrically conductive layer 506, (iii) a second portion of the dielectric layer 508, and (iv) a second portion of the second electrically conductive layer 510 that are located in a trench (e.g., second trench) of the wafer substrate 502. It should be noted that the trench capacitor 505b can be part of the same capacitor as the trench capacitor 505a. That is, the trench capacitor 505a and the trench capacitor 505b can be configured to be electrically coupled together to form a capacitor (e.g., the first capacitor) with a higher capacitance.

[0067] The integrated device 500 may also include an interconnect 509, an interconnect 592, and an interconnect 594. Interconnect 509 is coupled to Petition 870250081895, dated 11 / 09 / 2025, page 34 / 179 28 / 71 interconnection 592 and to interconnection 594. Interconnection 509 may be a through-substrate pathway extending through the wafer substrate 502. Interconnection 592 may be a pad interconnection. Interconnection 594 may be a pad interconnection. Interconnection 592 may be located on the front side of the integrated device 500. Interconnection 592 may be located on the rear side of the integrated device 500. Interconnection 509 may be a through-substrate interconnection. The integrated device may include at least one through-substrate interconnection.

[0068] An integrated device (e.g., 103, 105, 305) may include a chip (e.g., exposed semiconductor chip). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem.The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light-emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, a power management processor, and / or combinations thereof. An integrated device (e.g. Petition 870250081895, dated 11 / 09 / 2025, page 35 / 179 29 / 71 example, 103, 105, 305) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc.). An integrated device may include transistors. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. A chiplet may be manufactured using a process that provides better yields compared to other processes used to manufacture other types of integrated devices, which may reduce the total manufacturing cost of a chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings).In some implementations, multiple chiplets can be used to perform the functionalities of one or more chips (e.g., one or more embedded devices). Thus, for example, a single embedded device can be divided into multiple chiplets. As mentioned above, the use of multiple chiplets performing various functions can reduce the total cost of a package, compared to using a single chip to perform all the functions of a package. In some implementations, one or more of the chiplets and / or one or more of the embedded devices (e.g., 103) described in the disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an embedded device may be manufactured using a first technology node and a chiplet may be manufactured using a second. Petition 870250081895, dated 11 / 09 / 2025, page 36 / 179 30 / 71 technology node that is not as advanced as the first technology node. In such an example, the integrated device may include components (e.g., interconnects, transistors) that have a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in a package may be manufactured using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in a package may be manufactured using the same technology node or different technology nodes.

[0069] A technology node can refer to a specific manufacturing process and / or technology used to manufacture an integrated device and / or chiplet. A technology node can specify the smallest possible size (e.g., minimum size) that can be manufactured (e.g., the size of a transistor, trace width, gap between two transistors). Different technology nodes may have different throughput losses. Different technology nodes may have different costs. Technology nodes that produce components (e.g., traces, transistors) with fine details are more expensive and may have higher throughput losses than a technology node that produces components (e.g., traces, transistors) with less fine details. Thus, more advanced technology nodes may be more expensive and may have higher throughput losses than less advanced technology nodes. When all the functions of a package are implemented in Petition 870250081895, dated 11 / 09 / 2025, p. 37 / 179 31 / 71 unique integrated devices, the same technology node is used to manufacture the entire integrated device, even if some of the integrated device's functions do not need to be manufactured using that particular technology node. Thus, the integrated device becomes tied to a technology node. To optimize the cost of a package, some functions may be implemented in different integrated devices and / or chiplets, where different integrated devices and / or chiplets can be manufactured using different technology nodes to reduce overall costs. For example, functions that require the use of the most advanced technology node may be implemented in one integrated device, and functions that can be implemented using a less advanced technology node may be implemented in another integrated device and / or in one or more chiplets.An example would be an integrated device, manufactured using a first technology node (e.g., a more advanced technology node), which is configured to provide computing applications and at least one chiplet, which is manufactured using a second technology node, which is configured to provide other functionalities, where the second technology node is not as expensive as the first technology node, and where the second technology node manufactures components with minimum sizes that are larger than the minimum sizes of the components manufactured using the first technology node. Examples of computing applications might include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packaging as many transistors as possible in an integrated device, which is why an integrated device that is configured for applications of... Petition 870250081895, dated 11 / 09 / 2025, page 38 / 179 32 / 71 computing can be manufactured using the most advanced technology node available, while other chiplets can be manufactured using less advanced technology nodes, since these chiplets may not require as many transistors to be manufactured in the chiplets. Thus, combining the use of different technology nodes (which may have different associated throughput losses) for different integrated devices and / or chiplets can reduce the total cost of a package, compared to using a single integrated device to perform all the package functions.

[0070] Another advantage of dividing functions across multiple integrated devices and / or chiplets is that it allows for package performance improvements without having to redesign each integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by altering the design of the first integrated device while preserving the design of the first chiplet. Thus, the first chiplet can be reused with the improved and / or differently configured first integrated device. This saves costs by not having to redesign the first chiplet when packages with enhanced integrated devices are manufactured. Example Sequence for Manufacturing a Package Comprising a Substrate with an Integrated Embedded Device

[0071] In some implementations, the fabrication of a package includes several processes. Figures 6A to 6E illustrate an exemplary sequence for providing or fabricating a package. In some implementations, the sequence Petition 870250081895, dated 11 / 09 / 2025, p. 39 / 179 Step 33 / 71 of Figures 6A to 6E can be used to provide or manufacture package 100. However, the process in Figures 6A to 6E can be used to manufacture other packages described in the disclosure.

[0072] It should be noted that the sequence of Figures 6A to 6E may combine one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified. In some implementations, one or more processes may be replaced or swapped without this departing from the scope of the disclosure.

[0073] Stage 1, as shown in Figure 6A, illustrates a state after the provision of a carrier 600 and a seed layer 602. The seed layer 602 may be located on a surface of the carrier 600. The seed layer 602 may include a copper layer.

[0074] Stage 2 illustrates a state after the formation of a plurality of 182 interconnections on the 600 carrier. Forming the plurality of 182 interconnections may include forming a plurality of 184 interconnections. The seed layer 602 may be part of the plurality of 182 interconnections and / or the plurality of 184 interconnections. A masking, galvanizing, and / or pickling process may be used to form the plurality of 182 interconnections and / or the plurality of 184 interconnections.

[0075] Stage 3 illustrates a state after an integrated device 103 is coupled to the plurality of interconnections 184. The integrated device 103 may include the plurality of pillar interconnections 132. The integrated device 103 is coupled to the plurality of interconnections 184 Petition 870250081895, dated 11 / 09 / 2025, page 40 / 179 34 / 71 through a plurality of solder interconnections 130. A reflow soldering process can be used to couple the integrated device 103 to the plurality of interconnections 184. The plurality of solder interconnections 130 can be coupled to the plurality of pillar interconnections 132 and to the plurality of interconnections 184. In some implementations, the integrated device 103 can be configured as a deep trench capacitor. In some implementations, the integrated device 103 can be configured as a bridge. In some implementations, the plurality of pillar interconnections 132 may be optional. In such instances, the plurality of solder interconnections 130 can be coupled to other interconnections of the integrated device 103.

[0076] Stage 4 illustrates a state after the provision of a dielectric layer 108. The dielectric layer 108 may be formed over the carrier 600 and the integrated device 103. A vacuum lamination process may be used to form the dielectric layer 108. The dielectric layer 108 may encapsulate the integrated device 103, the plurality of interconnects 182, the plurality of interconnects 184, the plurality of solder interconnects 130, and the plurality of pillar interconnects 132. The dielectric layer 108 may include ABF (or non-glass reinforced resin). The dielectric layer 108 may be a first dielectric layer.

[0077] Stage 5, as shown in Figure 6B, illustrates a state after a dielectric layer 106 is formed on a surface of the dielectric layer 108. A deposition and / or lamination process can be used to form the dielectric layer 106. In some implementations, the layer Petition 870250081895, dated 11 / 09 / 2025, page 41 / 179 35 / 71 dielectric 106 may include the same material or a different material from dielectric layer 108. Dielectric layer 106 is provided so that dielectric layer 106 has a relatively flat surface. Dielectric layer 106 may be a second dielectric layer. Dielectric layer 106 may include ABF or pre-impregnation.

[0078] Stage 6 illustrates a state after a plurality of 662 cavities is formed in the 106 dielectric layer and the 108 dielectric layer. The plurality of 662 cavities can be formed using a stripping process (e.g., photo-stripping process) or a laser process. A masking, exposure, and / or development process can be used to form the plurality of 662 cavities.

[0079] Stage 7 illustrates a state after a plurality of interconnections 162 is formed on and over surfaces of the dielectric layer 106 and / or the dielectric layer 108. The plurality of interconnections 162 can be coupled to the plurality of interconnections 182. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 162.

[0080] Stage 8, as shown in Figure 6C, illustrates a state after a dielectric layer 104 is formed on a surface of dielectric layer 106. A deposition and / or lamination process may be used to form the dielectric layer 104. In some implementations, the dielectric layer 104 may include the same material or a different material from dielectric layer 108 and / or dielectric layer 106. The dielectric layer 104 is provided so that the dielectric layer 104 has a relatively flat surface. A Petition 870250081895, dated 11 / 09 / 2025, page 42 / 179 36 / 71 dielectric layer 104 may be a third dielectric layer. The dielectric layer 104 may include pre-impregnation.

[0081] Stage 9 illustrates a state after a plurality of 642 cavities is formed in the 104 dielectric layer. The plurality of 642 cavities can be formed using a stripping process (e.g., photo-stripping process) or a laser process. A masking, exposure, and / or development process can be used to form the plurality of 642 cavities.

[0082] Stage 10 illustrates a state after a plurality of interconnections 142 is formed in, and on, the dielectric layer 104. The plurality of interconnections 142 can be coupled to the plurality of interconnections 162. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 142.

[0083] Stage 11, as shown in Figure 6D illustrates a state after carrier 600 is decoupled. Carrier 600 can be separated from dielectric layer 108. In some implementations, at least part of seed layer 602 can be removed and / or separated.

[0084] Stage 12 illustrates a state after a weld-resistant layer 122 and a weld-resistant layer 124 have been formed. The weld-resistant layer 122 may be formed over (e.g., above) the dielectric layer 108. The weld-resistant layer 122 may include openings that expose portions of the plurality of interconnections 182 and / or the plurality of interconnections 184. The weld-resistant layer 124 may be formed over (e.g., below) the dielectric layer 104. The weld-resistant layer 124 may Petition 870250081895, dated 11 / 09 / 2025, page 43 / 179 37 / 71 include openings that expose portions of the plurality of interconnections 142. A deposition, lamination, masking, exposure, and / or development process may be used to form the weld-resistant layers and the openings in the weld-resistant layers. Stages 1 to 12 may illustrate a sequence for manufacturing a substrate (e.g., 102). Once the substrate is manufactured, an assembly process may be used to attach the substrate to one or more integrated devices to form a package. The assembly process to form the package may be performed by a different factory than the factory that manufactured the substrate, or by the same factory that manufactured the substrate.

[0085] Stage 13 illustrates a state after an integrated device 105 is coupled to the plurality of interconnections 184. The integrated device 105 may include the plurality of pillar interconnections 152. The integrated device 105 is coupled to the plurality of interconnections 184 through a plurality of solder interconnections 150. A reflow soldering process may be used to couple the integrated device 105 to the plurality of interconnections 184. The plurality of solder interconnections 150 may be coupled to the plurality of pillar interconnections 152 and to the plurality of interconnections 184.

[0086] Stage 14, as shown in Figure 6E, illustrates a state after an underfill 110 is provided between the integrated device 105 and the substrate 102. A deposition and / or injection process can be used to form and / or provide the underfill 110.

[0087] Stage 15 illustrates a state after the Petition 870250081895, dated 11 / 09 / 2025, page 44 / 179 38 / 71 plurality of solder interconnects 120 to be coupled to substrate 102. A reflow soldering process can be used to form and couple the plurality of solder interconnects 120. The plurality of solder interconnects 120 can be coupled to the plurality of interconnects 142. Stage 15 can illustrate package 100. Illustrative Flowchart of a Method for Manufacturing a Package Comprising a Substrate with an Embedded Integrated Device

[0088] In some implementations, the fabrication of a package includes several processes. Figure 7 illustrates an example flowchart of a method 700 for providing or fabricating a package. In some implementations, the method 700 in Figure 7 can be used to provide or fabricate any of the packages in Figures 1 to 4. Figure 7 will be described with respect to the fabrication of package 100. However, Figure 7 can be used to fabricate any package.

[0089] It should be noted that method 700 in Figure 7 may combine one or more processes in order to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified.

[0090] The method provides (in 705) a carrier with a seed layer. Stage 1 in Figure 6A illustrates and describes an example of a carrier 600 and a seed layer 602 that are provided. The seed layer 602 may be located on a surface of the carrier 600. The seed layer 602 may include a copper layer.

[0091] The method forms (in 710) interconnections on the carrier and seed layer. Stage 2 of the Figure Petition 870250081895, dated 11 / 09 / 2025, p. 45 / 179 39 / 71 Figure 6A illustrates and describes an example of a plurality of 182 interconnections that is formed on the carrier 600. Forming the plurality of 182 interconnections may include forming a plurality of 184 interconnections. The seed layer 602 may be part of the plurality of 182 interconnections and / or the plurality of 184 interconnections. A masking, galvanizing, and / or pickling process may be used to form the plurality of 182 interconnections and / or the plurality of 184 interconnections.

[0092] The method couples (in 715) an integrated device to the plurality of interconnections. Stage 3 of Figure 6A illustrates and describes an example of an integrated device 103 that is coupled to the plurality of interconnections 184. The integrated device 103 may include the plurality of pillar interconnections 132. The integrated device 103 is coupled to the plurality of interconnections 184 through a plurality of solder interconnections 130. A reflow soldering process may be used to couple the integrated device 103 to the plurality of interconnections 184. The plurality of solder interconnections 130 may be coupled to the plurality of pillar interconnections 132 and to the plurality of interconnections 184. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 can be configured as a bridge.In some implementations, the plurality of pillar interconnections 132 may be optional. In such instances, the plurality of solder interconnections 130 may be coupled to other interconnections of the integrated device 103.

[0093] The method forms (in 720) a first Petition 870250081895, dated 11 / 09 / 2025, page 46 / 179 40 / 71 dielectric layer. Stage 4 of Figure 6A illustrates and describes an example of a dielectric layer 108 that is provided. The dielectric layer 108 can be formed over the carrier 600 and the integrated device 103. A vacuum lamination process can be used to form the dielectric layer 108. The dielectric layer 108 can encapsulate the integrated device 103, the plurality of interconnects 182, the plurality of interconnects 184, the plurality of solder interconnects 130, and the plurality of pillar interconnects 132. The dielectric layer 108 can include ABF (or non-glass reinforced resin). The dielectric layer 108 can be a first dielectric layer.

[0094] The method forms (in 725) a second dielectric layer. Stage 5 of Figure 6B illustrates and describes an example of a dielectric layer 106 that is formed on a surface of dielectric layer 108. A deposition and / or lamination process can be used to form the dielectric layer 106. In some implementations, the dielectric layer 106 may include the same material or a different material from the dielectric layer 108. The dielectric layer 106 is provided so that the dielectric layer 106 has a relatively flat surface. The dielectric layer 106 may be a second dielectric layer. The dielectric layer 106 may include ABF or pre-impregnation. The formation of the first and / or second dielectric layer may include the formation of cavities in the dielectric layer(s). Stage 6 of Figure 6B illustrates and describes a plurality of cavities 662 that is formed in the dielectric layer 106 and in the dielectric layer 108.A plurality of 662 cavities can be formed using a pickling process (e.g., Petition 870250081895, dated 11 / 09 / 2025, page 47 / 179 41 / 71 photoetch process) or a laser process. A masking, exposure and / or development process may be used to form the plurality of cavities 662.

[0095] The method forms (in 730) interconnections in the dielectric layer. Stage 7 of Figure 6B illustrates and describes an example of a plurality of interconnections 162 that are formed on and over surfaces of the dielectric layer 106 and / or the dielectric layer 108. The plurality of interconnections 162 can be coupled to the plurality of interconnections 182. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 162.

[0096] The method forms (in 735) a third dielectric layer. Stage 8 of Figure 6C illustrates and describes an example of a dielectric layer 104 that is formed on a surface of dielectric layer 106. A deposition and / or lamination process can be used to form the dielectric layer 104. In some implementations, the dielectric layer 104 may include the same material or a different material from dielectric layer 108 and / or dielectric layer 106. The dielectric layer 104 is provided so that the dielectric layer 104 has a relatively flat surface. The dielectric layer 104 may be a third dielectric layer. The dielectric layer 104 may include pre-impregnation. In some implementations, the formation of the dielectric layer may include the formation of cavities in the dielectric layer. Stage 9 of Figure 6C illustrates and describes an example of a plurality of cavities 642 that are formed in the dielectric layer 104.A plurality of 642 cavities can be formed using a pickling process (by). Petition 870250081895, dated 11 / 09 / 2025, page 48 / 179 42 / 71 example, photoetch process) or a laser process. A masking, exposure and / or development process can be used to form the plurality of cavities 642.

[0097] The method forms (in 740) interconnections in the third dielectric layer. Stage 10 of Figure 10C illustrates and describes an example of a plurality of interconnections 142 that are formed on and over the surface of the dielectric layer 104. The plurality of interconnections 142 can be coupled to the plurality of interconnections 162. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 142.

[0098] The method decouples (at 745) the carrier and forms (at 745) solder-resistant layers. Stage 11 of Figure 6D illustrates and describes an example of a carrier 600 that is decoupled. The carrier 600 can be separated from the dielectric layer 108. In some implementations, at least part of the seed layer 602 can be removed and / or separated. Stage 12 of Figure 6D illustrates and describes an example where a solder-resistant layer 122 and a solder-resistant layer 124 are formed. The weld-resistant layer 122 may be formed over (e.g., above) the dielectric layer 108. The weld-resistant layer 122 may include openings that expose portions of the plurality of interconnections 182 and / or the plurality of interconnections 184. The weld-resistant layer 124 may be formed over (e.g., below) the dielectric layer 104. The weld-resistant layer 124 may include openings that expose portions of the plurality of interconnections 142.A process of deposition, lamination, masking, exposure and / or. Petition 870250081895, dated 11 / 09 / 2025, page 49 / 179 43 / 71 a revelation can be used to form the solder-resistant layers and the openings in the solder-resistant layers. Stages 1 to 12 can illustrate a sequence for manufacturing a substrate (e.g., 102). Once the substrate is manufactured, an assembly process can be used to attach the substrate to one or more integrated devices to form a package. The assembly process to form the package can be performed by a different factory than the factory that manufactured the substrate, or by the same factory that manufactured the substrate.

[0099] The method couples (at 750) a second integrated device to the substrate. Stage 13 of Figure 6D illustrates and describes an example of an integrated device 105 that is coupled to the plurality of interconnections 184. The integrated device 105 may include the plurality of pillar interconnections 152. The integrated device 105 is coupled to the plurality of interconnections 184 through a plurality of solder interconnections 150. A reflow soldering process may be used to couple the integrated device 105 to the plurality of interconnections 184. The plurality of solder interconnections 150 may be coupled to the plurality of pillar interconnections 152 and to the plurality of interconnections 184. The method may also provide (at 750) an underfill between the second integrated device and the substrate. Stage 14 of Figure 6E illustrates and describes an example of an underfill 110 that is provided between the integrated device 105 and the substrate 102.A deposition and / or injection process can be used to form and / or provide the underfill 110.

[00100] The method couples (in 755) interconnections Petition 870250081895, dated 11 / 09 / 2025, page 50 / 179 44 / 71 solder to substrate. Stage 15 of Figure 6E illustrates and describes an example of a plurality of solder interconnects 120 that are coupled to substrate 102. A reflow soldering process can be used to form and couple the plurality of solder interconnects 120. The plurality of solder interconnects 120 can be coupled to the plurality of interconnects 142. Stage 15 can illustrate package 100. Example Sequence for Manufacturing a Package Comprising a Substrate with an Integrated Embedded Device

[00101] In some implementations, the fabrication of a package includes several processes. Figures 8A to 8E illustrate an example sequence for providing or fabricating a package. In some implementations, the sequence in Figures 8A to 8E can be used to provide or fabricate package 200. However, the process in Figures 8A to 8E can be used to fabricate other packages described in the disclosure.

[00102] It should be noted that the sequence of Figures 8A to 8E may combine one or more stages in order to simplify and / or clarify the sequence for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified. In some implementations, one or more processes may be replaced or exchanged without departing from the scope of the disclosure.

[00103] Stage 1, as shown in Figure 8A, illustrates a state after the provision of a carrier 800 and a seed layer 802. The seed layer 802 may be located on a surface of the carrier 800. The layer Petition 870250081895, dated 11 / 09 / 2025, page 51 / 179 45 / 71 seed 802 may include a copper layer.

[00104] Stage 2 illustrates a state after the formation of a plurality of interconnections 282 on the carrier 800. Forming the plurality of interconnections 282 may include the formation of a plurality of interconnections 284. The seed layer 802 may be part of the plurality of interconnections 282 and / or the plurality of interconnections 284. A masking, galvanizing, and / or pickling process may be used to form the plurality of interconnections 282 and / or the plurality of interconnections 284.

[00105] Stage 3 illustrates a state after an integrated device 103 is coupled to the plurality of interconnects 284. The integrated device 103 may include the plurality of pillar interconnects 132. The integrated device 103 is coupled to the plurality of interconnects 284 through a plurality of solder interconnects 130. A reflow soldering process may be used to couple the integrated device 103 to the plurality of interconnects 284. The plurality of solder interconnects 130 may be coupled to the plurality of pillar interconnects 132 and the plurality of interconnects 284. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 may be configured as a bridge. In some implementations, the plurality of 132 pillar interconnections may be optional.In such instances, the plurality of solder interconnections 130 can be coupled to other interconnections of the integrated device 103. Stage 3 also illustrates an underfill 210 that is provided between the integrated device 103 and the carrier 800. Petition 870250081895, dated 11 / 09 / 2025, page 52 / 179 46 / 71 A deposition and / or injection process can be used to form and / or provide the underfill 210.

[00106] Stage 4 illustrates a state after the provision of a dielectric layer 208. The dielectric layer 208 can be formed over the carrier 800. The dielectric layer 208 can be located laterally around the integrated device 103 and the underfill 210. A lamination process can be used to form the dielectric layer 208. The dielectric layer 208 can include pre-impregnation or ABF. The dielectric layer 208 can be a first dielectric layer.

[00107] Stage 5, as shown in Figure 8B, illustrates a state after a dielectric layer 206 is formed on a surface of the dielectric layer 208 and the integrated device 103. The dielectric layer 206 can be coupled to and touch the back side of the integrated device 103. A deposition and / or lamination process can be used to form the dielectric layer 206. In some implementations, the dielectric layer 206 may include the same material or a different material from the dielectric layer 208. The dielectric layer 206 is provided so that the dielectric layer 206 has a relatively flat surface. The dielectric layer 206 may be a second dielectric layer. The dielectric layer 206 may include ABF (or non-glass reinforced resin).

[00108] Stage 6 illustrates a state after a plurality of 862 cavities is formed in the 206 dielectric layer and the 208 dielectric layer. The plurality of 862 cavities can be formed using a stripping process (e.g., photo-stripping process) or a laser process. Petition 870250081895, dated 11 / 09 / 2025, page 53 / 179 47 / 71 A masking, exposure and / or development process can be used to form the plurality of cavities 862.

[00109] Stage 7 illustrates a state after a plurality of interconnections 262 is formed on and over surfaces of the dielectric layer 206 and / or the dielectric layer 208. The plurality of interconnections 262 can be coupled to the plurality of interconnections 282. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 262.

[00110] Stage 8, as shown in Figure 8C, illustrates a state after a dielectric layer 204 is formed on a surface of dielectric layer 206. A deposition and / or lamination process may be used to form the dielectric layer 204. In some implementations, the dielectric layer 204 may include the same material or a different material from dielectric layer 208 and / or dielectric layer 206. The dielectric layer 204 is provided so that the dielectric layer 204 has a relatively flat surface. The dielectric layer 204 may be a third dielectric layer. The dielectric layer 204 may include pre-impregnation.

[00111] Stage 9 illustrates a state after a plurality of 842 cavities is formed in the 204 dielectric layer. The plurality of 842 cavities can be formed using a stripping process (e.g., photo-stripping process) and / or a laser process. A masking, exposure, and / or development process can be used to form the plurality of 842 cavities.

[00112] Stage 10 illustrates a state after a Petition 870250081895, dated 11 / 09 / 2025, page 54 / 179 48 / 71 plurality of interconnections 242 to be formed in, and on, the dielectric layer 204. The plurality of interconnections 242 can be coupled to the plurality of interconnections 262. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 242.

[00113] Stage 11, as shown in Figure 8D, illustrates a state after carrier 800 is decoupled. Carrier 800 can be separated from dielectric layer 208. In some implementations, at least part of seed layer 802 can be removed and / or separated.

[00114] Stage 12 illustrates a state after a weld-resistant layer 122 and a weld-resistant layer 124 have been formed. The weld-resistant layer 122 may be formed over (e.g., above) the dielectric layer 208. The weld-resistant layer 122 may include openings that expose portions of the plurality of interconnections 282 and / or the plurality of interconnections 284. The weld-resistant layer 124 may be formed over (e.g., below) the dielectric layer 204. The weld-resistant layer 124 may include openings that expose portions of the plurality of interconnections 242. A deposition, lamination, masking, exposure, and / or development process may be used to form the weld-resistant layers and the openings in the weld-resistant layers. Stages 1 through 12 can illustrate a sequence for manufacturing a substrate (e.g., 202).Once the substrate is manufactured, an assembly process can be used to attach the substrate to one or more integrated devices to form a package. The assembly process to form the package can be performed by a different factory than the factory that... Petition 870250081895, dated 11 / 09 / 2025, page 55 / 179 49 / 71 manufactured the substrate, or by the same factory that manufactured the substrate.

[00115] Stage 13 illustrates a state after an integrated device 105 and an integrated device 305 are coupled to the substrate 202. The integrated device 105 can be coupled to the plurality of interconnects 284. The integrated device 105 can include the plurality of pillar interconnects 152. The integrated device 105 is coupled to the plurality of interconnects 284 through a plurality of solder interconnects 150. A reflow soldering process can be used to couple the integrated device 105 to the plurality of interconnects 284. The plurality of solder interconnects 150 can be coupled to the plurality of pillar interconnects 152 and to the plurality of interconnects 284. The integrated device 305 can be coupled to the plurality of interconnects 284. The integrated device 305 can include the plurality of pillar interconnections 352.The integrated device 305 is coupled to the plurality of interconnections 284 through a plurality of solder interconnections 350. A reflow soldering process can be used to couple the integrated device 305 to the plurality of interconnections 284. The plurality of solder interconnections 350 can be coupled to the pillar plurality of interconnections 352 and to the plurality of interconnections 284.

[00116] Stage 14, as shown in Figure 8E, illustrates a state after an underfill 110 is provided between the integrated device 105 and the substrate 202. The underfill 110 can also be provided between the integrated device 305 and the substrate 202. A deposition process Petition 870250081895, dated 11 / 09 / 2025, page 56 / 179 50 / 71 and / or injection can be used to form and / or provide the underfill 110.

[00117] Stage 15 illustrates a state after the plurality of solder interconnects 120 is coupled to the substrate 202. A reflow soldering process can be used to form and couple the plurality of solder interconnects 120. The plurality of solder interconnects 120 can be coupled to the plurality of interconnects 242. Stage 15 can illustrate package 400. Illustrative Flowchart of a Method for Manufacturing a Package Comprising a Substrate with an Embedded Integrated Device

[00118] In some implementations, the fabrication of a package includes several processes. Figure 9 illustrates an example flowchart of a 900 method for providing or fabricating a package. In some implementations, the 900 method in Figure 9 can be used to provide or fabricate any of the packages in Figures 1 to 4. Figure 9 will be described in relation to the fabrication of package 400. However, Figure 9 can be used to fabricate any package.

[00119] It should be noted that method 900 in Figure 9 can combine one or more processes in order to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be altered or modified.

[00120] The method provides (in 905) a carrier with a seed layer. Stage 1 in Figure 8A illustrates and describes an example of a carrier 800 and a seed layer 802 that are provided. The seed layer 802 can be located on a surface of the carrier 800. The layer Petition 870250081895, dated 11 / 09 / 2025, p. 57 / 179 51 / 71 seed 802 may include a copper layer.

[00121] The method forms (in 910) interconnections on the carrier and seed layer. Stage 2 of Figure 8A illustrates and describes an example of a plurality of interconnections 282 that is formed on the carrier 800. Forming the plurality of interconnections 282 may include the formation of a plurality of interconnections 284. The seed layer 802 may be part of the plurality of interconnections 282 and / or the plurality of interconnections 284. A masking, galvanizing and / or pickling process may be used to form the plurality of interconnections 282 and / or the plurality of interconnections 284.

[00122] The method couples (in 915) an integrated device to the plurality of interconnections. Stage 3 of Figure 8A illustrates and describes an example of an integrated device 103 that is coupled to the plurality of interconnections 284. The integrated device 103 may include the plurality of pillar interconnections 132. The integrated device 103 is coupled to the plurality of interconnections 284 through a plurality of solder interconnections 130. A reflow soldering process may be used to couple the integrated device 103 to the plurality of interconnections 284. The plurality of solder interconnections 130 may be coupled to the plurality of pillar interconnections 132 and to the plurality of interconnections 284. In some implementations, the integrated device 103 may be configured as a deep trench capacitor. In some implementations, the integrated device 103 can be configured as a bridge.In some implementations, the plurality of 132-pillar interconnections may be optional. In such cases... Petition 870250081895, dated 11 / 09 / 2025, page 58 / 179 In instances 52 / 71, the plurality of solder interconnections 130 can be coupled to other interconnections of the integrated device 103. The method can also form (in 915) an underfill between the integrated device and the plurality of interconnections. Stage 3 of Figure 8A illustrates and describes an example of an underfill 210 that is provided between the integrated device 103 and the carrier 800. A deposition and / or injection process can be used to form and / or provide the underfill 210.

[00123] The method forms (in 920) a first dielectric layer. Stage 4 of Figure 8A illustrates and describes an example of a dielectric layer 208 that is provided. The dielectric layer 208 can be formed on the carrier 800. The dielectric layer 208 can be located laterally around the integrated device 103 and the underfill 210. A lamination process can be used to form the dielectric layer 208. The dielectric layer 208 can include pre-impregnation or ABF. The dielectric layer 208 can be a first dielectric layer.

[00124] The method forms (in 925) a second dielectric layer. Stage 5 of Figure 8B illustrates and describes an example of a dielectric layer 206 that is formed on a surface of the dielectric layer 208 and the integrated device 103. The dielectric layer 206 can be coupled to and touch the back side of the integrated device 103. A deposition and / or lamination process can be used to form the dielectric layer 206. In some implementations, the dielectric layer 206 may include the same material or a different material from the dielectric layer 208. The dielectric layer 206 may include ABF (or non-glass reinforced resin). The dielectric layer 206 is provided in such a way Petition 870250081895, dated 11 / 09 / 2025, page 59 / 179 53 / 71 that the dielectric layer 206 has a relatively flat surface. The dielectric layer 206 may be a second dielectric layer. The formation of the first and / or second dielectric layer may include the formation of cavities in the dielectric layer(s). Stage 6 of Figure 8B illustrates and describes an example of a plurality of 862 cavities that is formed in the dielectric layer 206 and the dielectric layer 208. The plurality of 862 cavities may be formed using a stripping process (e.g., photo-strip process) or a laser process. A masking, exposure, and / or development process may be used to form the plurality of 862 cavities.

[00125] The method forms (in 930) interconnections in the dielectric layer. Stage 7 of Figure 8B illustrates and describes an example of a plurality of interconnections 262 that are formed on and over surfaces of the dielectric layer 206 and / or the dielectric layer 208. The plurality of interconnections 262 can be coupled to the plurality of interconnections 282. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 262.

[00126] The method forms (in 935) a third dielectric layer. Stage 8 of Figure 8C illustrates and describes an example of a dielectric layer 204 that is formed on a surface of the dielectric layer 206. A deposition and / or lamination process can be used to form the dielectric layer 204. In some implementations, the dielectric layer 204 may include the same material or a different material from the dielectric layer 208 and / or the dielectric layer 206. The dielectric layer 204 is provided so that the layer Petition 870250081895, dated 11 / 09 / 2025, page 60 / 179 54 / 71 dielectric 204 has a relatively flat surface. The dielectric layer 204 may be a third dielectric layer. The dielectric layer 204 may include pre-impregnation. In some implementations, the formation of the dielectric layer may include the formation of cavities in the dielectric layer. Stage 9 of Figure 8C illustrates and describes an example of a plurality of cavities 842 that are formed in the dielectric layer 204. The plurality of cavities 842 may be formed using a stripping process (e.g., photo-stripping process) and / or a laser process. A masking, exposure, and / or development process may be used to form the plurality of cavities 842.

[00127] The method forms (in 940) a plurality of interconnections in the third dielectric layer. Stage 10 of Figure 8C illustrates and describes an example of a plurality of interconnections 242 that are formed on and over the surface of the dielectric layer 204. The plurality of interconnections 242 can be coupled to the plurality of interconnections 262. A masking, galvanizing and / or pickling process can be used to form the plurality of interconnections 242.

[00128] The method decouples (at 945) the carrier and forms (at 945) solder-resistant layers. Stage 11 in Figure 8D illustrates and describes an example of carrier 800 being decoupled. Carrier 800 can be separated from dielectric layer 208. In some implementations, at least part of seed layer 802 can be removed and / or separated. Stage 12 in Figure 8D illustrates and describes an example where solder-resistant layer 122 and solder-resistant layer 124 are formed. Solder-resistant layer 122 can be formed over (e.g., above) the Petition 870250081895, dated 11 / 09 / 2025, p. 61 / 179 55 / 71 dielectric layer 208. The solder-resistant layer 122 may include openings that expose portions of the plurality of interconnections 282 and / or the plurality of interconnections 284. The solder-resistant layer 124 may be formed over (e.g., below) the dielectric layer 204. The solder-resistant layer 124 may include openings that expose portions of the plurality of interconnections 242. A deposition, lamination, masking, exposure, and / or development process may be used to form the solder-resistant layers and the openings in the solder-resistant layers. Stages 1 to 12 may illustrate a sequence for fabricating a substrate (e.g., 202). Once the substrate is fabricated, an assembly process may be used to attach the substrate to one or more integrated devices to form a package.The assembly process to form the package can be carried out by a different factory than the one that manufactured the substrate, or by the same factory that manufactured the substrate.

[00129] The method couples (in 950) at least one second integrated device to the substrate. Stage 13 of Figure 8D illustrates and describes an example of an integrated device 105 and an integrated device 305 that are coupled to a substrate 202. The integrated device 105 can be coupled to a plurality of interconnects 284. The integrated device 105 can include a plurality of pillar interconnects 152. The integrated device 105 is coupled to the plurality of interconnects 284 through a plurality of solder interconnects 150. A reflow soldering process can be used to couple the integrated device 105 to the plurality of interconnects 284. A Petition 870250081895, dated 11 / 09 / 2025, page 62 / 179 56 / 71 A plurality of solder interconnections 150 can be coupled to a pillar interconnection plurality 152 and interconnection plurality 284. The integrated device 305 can be coupled to interconnection plurality 284. The integrated device 305 can include pillar interconnection plurality 352. The integrated device 305 is coupled to interconnection plurality 284 through a solder interconnection plurality 350. A reflow soldering process can be used to couple the integrated device 305 to interconnection plurality 284. The solder interconnection plurality 350 can be coupled to pillar interconnection plurality 352 and interconnection plurality 284. The method can also provide (in 950) an underfill between the integrated devices and the substrate. Stage 14 of Figure 8E illustrates and describes an example of an underfill 110 that is provided between the integrated device 105 and the substrate 202.Underfill 110 can also be provided between the integrated device 305 and the substrate 202. A deposition and / or injection process can be used to form and / or provide underfill 110.

[00130] The method couples (in 955) solder interconnects to the substrate. Stage 15 of Figure 8E illustrates and describes an example of a plurality of solder interconnects 120 that are coupled to the substrate 202. A reflow soldering process can be used to form and couple the plurality of solder interconnects 120. The plurality of solder interconnects 120 can be coupled to the plurality of interconnects 242. Stage 15 can illustrate the package 400. Examples of Electronic Devices Petition 870250081895, dated 11 / 09 / 2025, page 63 / 179 57 / 71

[00131] Figure 10 illustrates various electronic devices that can be integrated into any of the previously mentioned devices, integrated device, integrated circuit (IC) package, integrated circuit device (IC), semiconductor device, integrated circuit, wafer, interposer, package, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1002, a laptop-type computer device 1004, a fixed-location terminal device 1006, a wearable device 1008, or a motor vehicle 1010 may include a device 1000, as described in the present invention. The device 1000 may be, for example, any of the devices and / or integrated circuit (IC) packages described in the present invention.Devices 1002, 1004, 1006, and 1008 and vehicle 1010 illustrated in Figure 10 are merely examples. Other electronic devices may also feature device 1000, including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, signal decoders, music players, video players, entertainment units, fixed location data units such as meter reading equipment, devices for... Petition 870250081895, dated 11 / 09 / 2025, page 64 / 179 58 / 71 communication, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles) or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[00132] One or more of the components, processes, attributes and / or functions illustrated in Figures 1 to 5, 6A to 6E, 7, 8A to 8E and / or 9 to 10 may be rearranged and / or combined into a single component, process, attribute or function, or incorporated into multiple components, processes or functions. Additional elements, components, processes and / or functions may also be added without departing from the disclosure. It should also be noted that Figures 1 to 5, 6A to 6E, 7, 8A to 8E and / or 9 to 10 and their corresponding descriptions in this disclosure are not limited to chips and / or ICs. In some implementations, Figures 1 to 5, 6A to 6E, 7, 8A to 8E and / or 9 to 10, and their corresponding descriptions, may be used to manufacture, create, provide and / or produce devices and / or integrated devices.In some implementations, a device may include a chip, an integrated device, an integrated passive device (IPD), a chip package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer. Petition 870250081895, dated 11 / 09 / 2025, page 65 / 179 59 / 71

[00133] It should be mentioned that the figures in the disclosure may be actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits and / or transistors. In some cases, the figures may not be to scale. In some cases, for clarity, not all components and / or parts may be visible. In some cases, the position, location, sizes and / or shapes of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[00134] The word exemplifier is used in the present invention to mean serving as an example, an instance, or an illustration. Any implementations or aspects described in the present invention as exemplifiers should not necessarily be interpreted as preferential or advantageous in relation to other aspects of the disclosure. Similarly, the term aspects does not require that all aspects of the disclosure include the attribute, advantage, or mode of operation discussed. The term coupled is used in the present invention to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to each other – even if they do not directly physically touch each other.The term electrically coupled can mean that two objects are directly or indirectly coupled to each other in such a way that one... Petition 870250081895, dated 11 / 09 / 2025, page 66 / 179 60 / 71 electric current (e.g., signal, power, ground) can flow between the two objects. Two objects that are electrically coupled may or may not have an electric current flowing between them. The use of the terms first, second, third, and fourth (and / or any value above fourth) is arbitrary. Any of the components described can be the first component, the second component, the third component, or the fourth component. For example, a component that is called a second component can be the first component, the second component, the third component, or the fourth component. The term encapsulation means that the object can partially encapsulate or completely encapsulate another object. The terms top and bottom are arbitrary. A component that is located on top can be located above a component that is located on the bottom. A top component can be considered a bottom component, and vice versa.As described in the disclosure, a first component that is located on a second component can mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located on (e.g., above) a first surface of the second component, and a third component may be located on (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It should be further mentioned that the term "on," as used in this application in the context of a component located on... Petition 870250081895, dated 11 / 09 / 2025, page 67 / 179 61 / 71 another component, can be used to mean a component that is on top of another component and / or inside another component (e.g., on top of a component's surface or embedded in a component). Thus, for example, a first component that is on top of the second component can mean that (1) the first component is on top of the second component but not directly touching the second component, (2) the first component is on top of (e.g., on top of a surface of) the second component, and / or (3) the first component is in (e.g., embedded in) the second component. A value that is approximately X to XX can mean a value that is between X and XX, inclusive of X and XX. The value(s) between X and XX may be distinct or continuous. The term approximately 'value X' or approximately value X, as used in the disclosure, means within 10 percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. A plurality of components may include all possible components or only some of the components among all possible components. For example, if a device includes ten components, the use of the term plurality of components may refer to all ten components or only some of the components among the ten components.

[00135] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a track, a path, a pad, a pillar, a metallic redistribution layer. Petition 870250081895, dated 11 / 09 / 2025, page 68 / 179 62 / 71 and / or an under-bump metallization (UBM) layer. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect is an electrically conductive material that may be configured to provide an electrical path for a current (e.g., a data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form the interconnects. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process are used to form the interconnects.For example, an ion bombardment process, a spray coating, and / or a plating or autocatalytic plating process can be used to form the interconnects.

[00136] Furthermore, it should be mentioned that several disclosures contained in the present invention can be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process is terminated when its operations are completed. Petition 870250081895, dated 11 / 09 / 2025, page 69 / 179 63 / 71

[00137] Additional examples are described below to facilitate understanding of the invention.

[00138] Aspect 1: A package comprising a substrate that includes at least one dielectric layer; a plurality of interconnects comprising a first plurality of interconnects; and a first integrated device located at least partially on the substrate, wherein the first integrated device is coupled to the first plurality of interconnects via a first plurality of solder interconnects. The package includes a second integrated device coupled to the first plurality of interconnects via a second plurality of solder interconnects.

[00139] Aspect 2: The package from aspect 1, where the first integrated device includes a deep trench capacitor.

[00140] Aspect 3: The package of aspects 1 to 2, wherein an electrical path between the first integrated device and the second integrated device includes (i) a solder interconnection of the first plurality of solder interconnections, (ii) an interconnection of the first plurality of interconnections and (iii) a solder interconnection of the second plurality of solder interconnections.

[00141] Aspect 4: The package of aspects 1 to 3, wherein the first integrated device is coupled to the first plurality of interconnections through a first plurality of pad interconnections and a first plurality of solder interconnections, and wherein the second integrated device is coupled to the first plurality of interconnections through a second plurality of Petition 870250081895, dated 11 / 09 / 2025, pp. 70 / 179 64 / 71 pillar interconnections and a second plurality of welded interconnections.

[00142] Aspect 5: The package of aspect 4, wherein an electrical path between the first integrated device and the second integrated device includes (i) a pad interconnection of the first plurality of pad interconnections, (ii) a solder interconnection of the first plurality of solder interconnections, (iii) an interconnection of the first plurality of interconnections, (iv) a solder interconnection of the second plurality of solder interconnections and (v) a pillar interconnection of the second plurality of solder interconnections.

[00143] Aspect 6: The package of aspects 1 to 3, wherein the first integrated device is coupled to the first plurality of interconnections through a first plurality of pillar interconnections and a first plurality of weld interconnections, and wherein the second integrated device is coupled to the first plurality of interconnections through a second plurality of pillar interconnections and a second plurality of weld interconnections.

[00144] Aspect 7: The package of aspect 6, wherein an electrical path between the first integrated device and the second integrated device includes (i) a pillar interconnection of the first plurality of pillar interconnections, (ii) a solder interconnection of the first plurality of solder interconnections, (iii) an interconnection of the first plurality of interconnections, (iv) a solder interconnection of the second plurality of solder interconnections, and (v) a pillar interconnection of the second plurality of Petition 870250081895, dated 11 / 09 / 2025, page 71 / 179 65 / 71 solder interconnections.

[00145] Aspect 8: The package of aspects 1 to 7, which additionally comprises an underfill located between the second integrated device and the substrate.

[00146] Aspect 9: The package of aspects 1 to 7, further comprising: a first underfill located laterally around the first plurality of interconnects and the first plurality of solder interconnects; and a second underfill located between the second integrated device and the substrate, wherein the second underfill is touching the first underfill.

[00147] Aspect 10: The package of aspect 9, in which the first underfill includes a material other than at least one dielectric layer.

[00148] Aspect 11: The package of aspects 1 to 10, in which at least one dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer.

[00149] Aspect 12: The package of aspect 11, in which the plurality of interconnections includes a path extending through the first dielectric layer and the second dielectric layer, and in which the first dielectric layer is coupled to a rear side surface of the first integrated device and to a side surface of the first integrated device.

[00150] Aspect 13: The package of aspects 1 to 12, further comprising a third integrated device coupled to the first plurality of interconnections by means of a third plurality of soldered interconnections, wherein the first integrated device comprises Petition 870250081895, dated 11 / 09 / 2025, page 72 / 179 66 / 71 a bridge, wherein an electrical path between the second integrated device and the third integrated device includes the bridge, wherein the second integrated device includes a first chiplet and wherein the third integrated device includes a second chiplet.

[00151] Aspect 14: The package of aspects 1 to 13, wherein the first integrated device comprises a first front side and a first rear side, wherein the second integrated device comprises a second front side and a second rear side, wherein the first front side of the first integrated device faces in a first direction and wherein the second front side of the second integrated device faces in a second direction that is opposite to the first direction.

[00152] Aspect 15: A device comprising a substrate that includes at least one dielectric layer; a plurality of interconnects comprising a first plurality of interconnects; and a first integrated device located at least partially on the substrate, wherein the first integrated device is coupled to the first plurality of interconnects by means of a first plurality of soldered interconnects. The device includes a second integrated device coupled to the first plurality of interconnects by means of a second plurality of soldered interconnects.

[00153] Aspect 16: The device of aspect 15, in which the first integrated device includes a deep trench capacitor.

[00154] Aspect 17: The device of aspects 15 to 16, in which an electrical path between the first Petition 870250081895, dated 11 / 09 / 2025, p. 73 / 179 67 / 71 integrated device and the second integrated device includes (i) a solder interconnection of the first plurality of solder interconnections, (ii) an interconnection of the first plurality of interconnections and (iii) a solder interconnection of the second plurality of solder interconnections.

[00155] Aspect 18: The device of aspects 15 to 17, which additionally comprises an underfill located between the second integrated device and the substrate.

[00156] Aspect 19: The device of aspects 15 to 17, further comprising a first underfill located laterally around the first plurality of interconnections and the first plurality of solder interconnections; and a second underfill located between the second integrated device and the substrate, wherein the second underfill is touching the first underfill.

[00157] Aspect 20: The device of aspect 19, where the first underfill includes a material other than at least one dielectric layer.

[00158] Aspect 21: The device of aspects 15 to 20, in which at least one dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer.

[00159] Aspect 22: The device of aspect 21, in which the plurality of interconnections includes a path that extends through the first dielectric layer and the second dielectric layer.

[00160] Aspect 23: The device of aspects 21 to 22, in which the first dielectric layer is coupled to a rear lateral surface of the first device. Petition 870250081895, dated 11 / 09 / 2025, p. 74 / 179 68 / 71 integrated and a side surface of the first integrated device.

[00161] Aspect 24: The device of aspects 15 to 23, wherein the first integrated device comprises a first front side and a first rear side, wherein the second integrated device comprises a second front side and a second rear side, wherein the first front side of the first integrated device is oriented in a first direction and wherein the second front side of the second integrated device is oriented in a second direction that is opposite to the first direction.

[00162] Aspect 25: A method for fabricating a substrate, wherein the fabrication of the substrate comprises coupling a first integrated device to a first plurality of carrier interconnects, by means of a first plurality of solder interconnects; forming a first dielectric layer on the carrier and the first integrated device, wherein the first dielectric layer encapsulates the first integrated device, the first plurality of solder interconnects and the first plurality of interconnects; forming a second dielectric layer on a surface of the first dielectric layer; forming a first plurality of cavities in the second dielectric layer and in the first dielectric layer; forming a second plurality of interconnects at least in the first plurality of cavities; forming a third dielectric layer on the second dielectric layer; forming a second plurality of cavities in the third dielectric layer;and to form a third plurality of interconnections, at least within the second plurality of; Petition 870250081895, dated 11 / 09 / 2025, page 75 / 179 69 / 71 cavities.

[00163] Aspect 26: The method of aspect 25, wherein after forming the substrate, the method further comprises coupling a second integrated device to the first plurality of interconnections by means of a second plurality of soldered interconnections.

[00164] Aspect 27: The method of aspect 26, wherein after coupling the second integrated device, the method further comprises forming an underfill between the second integrated device and the first dielectric layer.

[00165] Aspect 28: The method of aspects 25 to 26, in which the first dielectric layer includes ABF and the third dielectric layer includes pre-impregnation.

[00166] Aspect 29: The method of aspects 25 to 27, wherein the first integrated device and the first plurality of solder interconnections are located on the substrate.

[00167] Aspect 30: A method for fabricating a substrate, wherein the fabrication of the substrate comprises coupling a first integrated device to a first plurality of carrier interconnects, through a first plurality of solder interconnects; forming a first underfill between the first integrated device and the carrier, wherein the first underfill laterally encircles the first plurality of solder interconnects; forming a first dielectric layer on the carrier; forming a second dielectric layer on the first integrated device and a surface of the first dielectric layer; forming a first plurality of cavities in the second Petition 870250081895, dated 11 / 09 / 2025, pp. 76 / 179 70 / 71 dielectric layer and in the first dielectric layer; form a second plurality of interconnections at least in the first plurality of cavities; form a third dielectric layer over the second dielectric layer; form a second plurality of cavities in the third dielectric layer; and form a third plurality of interconnections at least in the second plurality of cavities.

[00168] Aspect 31: The method of aspect 30, wherein after forming the substrate, the method further comprises coupling a second integrated device to the first plurality of interconnections by means of a second plurality of soldered interconnections.

[00169] Aspect 32: The method of aspect 31, wherein after coupling the second integrated device, the method further comprises forming a second underfill between the second integrated device and the first underfill.

[00170] Aspect 33: The method of aspects 30 to 32, where the first dielectric layer includes ABF or pre-impregnation, the second dielectric layer includes ABF and the third dielectric layer includes pre-impregnation.

[00171] Aspect 34: The method of aspects 30 to 33, wherein the first integrated device, the first plurality of solder interconnections and the first underfill are located on the substrate.

[00172] The various disclosure attributes described in the present invention can be implemented in different systems without deviating from the scope of the disclosure. It should be mentioned that the aforementioned aspects of the disclosure are merely examples and should not be... Petition 870250081895, dated 11 / 09 / 2025, p. 77 / 179 71 / 71 should not be interpreted as limiting the disclosure. The description of the aspects of this disclosure is intended to be illustrative and not to limit the scope of the aspects. Thus, the present teachings can be readily applied to other types of apparatus, and many alternatives, modifications, and variations will be evident to those skilled in the art. Petition 870250081895, dated 11 / 09 / 2025, pp. 78 / 179

Claims

1 / 6 CLAIMS 1. Package characterized by comprising: a substrate comprising: at least one dielectric layer; a plurality of interconnects comprising a first plurality of interconnects; and a first integrated device located at least partially on the substrate, wherein the first integrated device is coupled to the first plurality of interconnects by means of a first plurality of soldered interconnects; and a second integrated device coupled to the first plurality of interconnects by means of a second plurality of soldered interconnects.

2. Package according to claim 1, characterized in that the first integrated device includes a deep trench capacitor.

3. Package according to claim 1, characterized by an electrical path between the first integrated device and the second integrated device including (i) a solder interconnection of the first plurality of solder interconnections, (ii) an interconnection of the first plurality of interconnections and (iii) a solder interconnection of the second plurality of solder interconnections.

4. Package, according to claim 1, characterized in that the first integrated device is coupled to the first plurality of interconnections through a first plurality of pad interconnections and a first plurality of solder interconnections, and in that the second integrated device is coupled to the first plurality of interconnections through a second plurality of pillar interconnections and a second plurality of solder interconnections.

5. Package according to claim 4, characterized in that an electrical path between the first integrated device and the second integrated device includes (i) a pad interconnection of the first plurality of pad interconnections, (ii) a solder interconnection of the first plurality of solder interconnections, (iii) an interconnection of the first plurality of interconnections, (iv) a solder interconnection of the second plurality of solder interconnections and (v) a pillar interconnection of the second plurality of solder interconnections.

6. Package, according to claim 1, characterized in that the first integrated device is coupled to the first plurality of interconnections through a first plurality of pillar interconnections and a first plurality of weld interconnections, and in that the second integrated device is coupled to the first plurality of interconnections through a second plurality of pillar interconnections and a second plurality of weld interconnections.

7. Package according to claim 6, characterized by an electrical pathway between the first integrated device and the second integrated device including (i) a pillar interconnection of the first plurality of pillar interconnections, (ii) a solder interconnection of the first plurality of solder interconnections, (iii) an interconnection of the first plurality of interconnections, (iv) a solder interconnection of the second plurality of solder interconnections and (v) a pillar interconnection of the second plurality of solder interconnections.

8. Package, according to claim 1, characterized by further comprising an underfill located between the second integrated device and the substrate.

9. Package, according to claim 1, characterized by further comprising: a first underfill located laterally around the first plurality of interconnects and the first plurality of solder interconnects; and a second underfill located between the second integrated device and the substrate, wherein the second underfill is touching the first underfill.

10. Package according to claim 9, characterized in that the first underfill includes a material other than at least one dielectric layer.

11. Package, according to claim 1, characterized in that at least one dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer.

12. Package according to claim 11, characterized in that the plurality of interconnections includes a path extending through the first dielectric layer and the second dielectric layer, and wherein the first dielectric layer is coupled to a rear lateral surface of the first integrated device and to a lateral surface of the first integrated device.

13. Package, according to claim 1, Petition 870250081895, dated 11 / 09 / 2025, pp. 153 / 179 4 / 6 characterized by further comprising a third integrated device coupled to the first plurality of interconnections through a third plurality of soldered interconnections, wherein the first integrated device comprises a bridge, wherein an electrical path between the second integrated device and the third integrated device includes the bridge, wherein the second integrated device includes a first chiplet, and wherein the third integrated device includes a second chiplet.

14. Package, according to claim 1, characterized in that the first integrated device comprises a first front side and a first rear side, wherein the second integrated device comprises a second front side and a second rear side, wherein the first front side of the first integrated device faces a first direction, and wherein the second front side of the second integrated device faces a second direction that is opposite to the first direction.

15. Device characterized by comprising: a substrate comprising: at least one dielectric layer; a plurality of interconnections comprising a first plurality of interconnections; and Petition 870250081895, dated 11 / 09 / 2025, page 154 / 179 5 / 6 a first integrated device located at least partially on the substrate, wherein the first integrated device is coupled to the first plurality of interconnections by means of a first plurality of soldered interconnections; and a second integrated device coupled to the first plurality of interconnections by means of a second plurality of soldered interconnections.

16. Device according to claim 15, characterized in that the first integrated device includes a deep trench capacitor.

17. Device according to claim 15, characterized in that an electrical path between the first integrated device and the second integrated device includes (i) a solder interconnection of the first plurality of solder interconnections, (ii) an interconnection of the first plurality of interconnections and (iii) a solder interconnection of the second plurality of solder interconnections.

18. Device according to claim 15, characterized by further comprising an underfill located between the second integrated device and the substrate.

19. Device according to claim 15, characterized by further comprising: a first underfill located laterally around the first plurality of interconnections and the first plurality of solder interconnections; and a second underfill located between the second integrated device and the substrate, wherein the second underfill is touching the first underfill. Petition 870250081895, dated 11 / 09 / 2025, pp. 155 / 179 6 / 6 20. Device according to claim 19, characterized in that the first underfill includes a material other than at least one dielectric layer.

21. Device according to claim 15, characterized in that at least one dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer.

22. Device according to claim 21, characterized in that the plurality of interconnections includes a path extending through the first dielectric layer and the second dielectric layer.

23. Device according to claim 21, characterized in that the first dielectric layer is coupled to a rear lateral surface of the first integrated device and to a lateral surface of the first integrated device.

24. Device according to claim 15, characterized in that the first integrated device comprises a first front side and a first rear side, wherein the second integrated device comprises a second front side and a second rear side, wherein the first front side of the first integrated device faces a first direction, and wherein the second front side of the second integrated device faces a second direction that is opposite to the first direction. Petition 870250081895, dated 11 / 09 / 2025, pp. 156 / 179

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